#include "vk_util.h"
#include "radv_radeon_winsys.h"
#include "sid.h"
-#include "gfx9d.h"
#include "util/debug.h"
#include "util/u_atomic.h"
+
static unsigned
radv_choose_tiling(struct radv_device *device,
const struct radv_image_create_info *create_info)
if (!vk_format_is_compressed(pCreateInfo->format) &&
!vk_format_is_depth_or_stencil(pCreateInfo->format)
- && device->physical_device->rad_info.chip_class <= VI) {
+ && device->physical_device->rad_info.chip_class <= GFX8) {
/* this causes hangs in some VK CTS tests on GFX9. */
/* Textures with a very small height are recommended to be linear. */
if (pCreateInfo->imageType == VK_IMAGE_TYPE_1D ||
const VkImageCreateInfo *pCreateInfo)
{
/* TC-compat HTILE is only available for GFX8+. */
- if (device->physical_device->rad_info.chip_class < VI)
+ if (device->physical_device->rad_info.chip_class < GFX8)
return false;
if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
(pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT))
return false;
+ /* TODO: Implement layout transitions with variable sample locations
+ * before enabling HTILE for depth/stencil images created with this
+ * flags because the depth decompress pass needs to know them.
+ */
+ if (pCreateInfo->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT)
+ return false;
+
if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
return false;
return true;
}
+static bool
+radv_surface_has_scanout(struct radv_device *device, const struct radv_image_create_info *info)
+{
+ if (info->scanout)
+ return true;
+
+ if (!info->bo_metadata)
+ return false;
+
+ if (device->physical_device->rad_info.chip_class >= GFX9) {
+ return info->bo_metadata->u.gfx9.swizzle_mode == 0 || info->bo_metadata->u.gfx9.swizzle_mode % 4 == 2;
+ } else {
+ return info->bo_metadata->u.legacy.scanout;
+ }
+}
+
static bool
radv_use_dcc_for_image(struct radv_device *device,
const struct radv_image *image,
bool blendable;
/* DCC (Delta Color Compression) is only available for GFX8+. */
- if (device->physical_device->rad_info.chip_class < VI)
+ if (device->physical_device->rad_info.chip_class < GFX8)
return false;
if (device->instance->debug_flags & RADV_DEBUG_NO_DCC)
if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
return false;
+ if (vk_format_is_subsampled(pCreateInfo->format) ||
+ vk_format_get_plane_count(pCreateInfo->format) > 1)
+ return false;
+
/* TODO: Enable DCC for mipmaps and array layers. */
if (pCreateInfo->mipLevels > 1 || pCreateInfo->arrayLayers > 1)
return false;
- if (create_info->scanout)
+ if (radv_surface_has_scanout(device, create_info))
return false;
/* FIXME: DCC for MSAA with 4x and 8x samples doesn't work yet, while
return true;
}
+static void
+radv_prefill_surface_from_metadata(struct radv_device *device,
+ struct radeon_surf *surface,
+ const struct radv_image_create_info *create_info)
+{
+ const struct radeon_bo_metadata *md = create_info->bo_metadata;
+ if (device->physical_device->rad_info.chip_class >= GFX9) {
+ if (md->u.gfx9.swizzle_mode > 0)
+ surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
+ else
+ surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
+
+ surface->u.gfx9.surf.swizzle_mode = md->u.gfx9.swizzle_mode;
+ } else {
+ surface->u.legacy.pipe_config = md->u.legacy.pipe_config;
+ surface->u.legacy.bankw = md->u.legacy.bankw;
+ surface->u.legacy.bankh = md->u.legacy.bankh;
+ surface->u.legacy.tile_split = md->u.legacy.tile_split;
+ surface->u.legacy.mtilea = md->u.legacy.mtilea;
+ surface->u.legacy.num_banks = md->u.legacy.num_banks;
+
+ if (md->u.legacy.macrotile == RADEON_LAYOUT_TILED)
+ surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
+ else if (md->u.legacy.microtile == RADEON_LAYOUT_TILED)
+ surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
+ else
+ surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
+
+ }
+}
+
static int
radv_init_surface(struct radv_device *device,
const struct radv_image *image,
struct radeon_surf *surface,
+ unsigned plane_id,
const struct radv_image_create_info *create_info)
{
const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
unsigned array_mode = radv_choose_tiling(device, create_info);
- const struct vk_format_description *desc =
- vk_format_description(pCreateInfo->format);
+ VkFormat format = vk_format_get_plane_format(pCreateInfo->format, plane_id);
+ const struct vk_format_description *desc = vk_format_description(format);
bool is_depth, is_stencil;
is_depth = vk_format_has_depth(desc);
is_stencil = vk_format_has_stencil(desc);
- surface->blk_w = vk_format_get_blockwidth(pCreateInfo->format);
- surface->blk_h = vk_format_get_blockheight(pCreateInfo->format);
+ surface->blk_w = vk_format_get_blockwidth(format);
+ surface->blk_h = vk_format_get_blockheight(format);
- surface->bpe = vk_format_get_blocksize(vk_format_depth_only(pCreateInfo->format));
+ surface->bpe = vk_format_get_blocksize(vk_format_depth_only(format));
/* align byte per element on dword */
if (surface->bpe == 3) {
surface->bpe = 4;
}
- surface->flags = RADEON_SURF_SET(array_mode, MODE);
+ if (create_info->bo_metadata) {
+ radv_prefill_surface_from_metadata(device, surface, create_info);
+ } else {
+ surface->flags = RADEON_SURF_SET(array_mode, MODE);
+ }
switch (pCreateInfo->imageType){
case VK_IMAGE_TYPE_1D:
if (!radv_use_dcc_for_image(device, image, create_info, pCreateInfo))
surface->flags |= RADEON_SURF_DISABLE_DCC;
- if (create_info->scanout)
+ if (radv_surface_has_scanout(device, create_info))
surface->flags |= RADEON_SURF_SCANOUT;
+
return 0;
}
}
static inline unsigned
-si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
+si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
{
if (stencil)
- return image->surface.u.legacy.stencil_tiling_index[level];
+ return plane->surface.u.legacy.stencil_tiling_index[level];
else
- return image->surface.u.legacy.tiling_index[level];
+ return plane->surface.u.legacy.tiling_index[level];
}
static unsigned radv_map_swizzle(unsigned swizzle)
state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
S_008F04_STRIDE(stride);
- if (device->physical_device->rad_info.chip_class != VI && stride) {
+ if (device->physical_device->rad_info.chip_class != GFX8 && stride) {
range /= stride;
}
si_set_mutable_tex_desc_fields(struct radv_device *device,
struct radv_image *image,
const struct legacy_surf_level *base_level_info,
+ unsigned plane_id,
unsigned base_level, unsigned first_level,
unsigned block_width, bool is_stencil,
bool is_storage_image, uint32_t *state)
{
+ struct radv_image_plane *plane = &image->planes[plane_id];
uint64_t gpu_address = image->bo ? radv_buffer_get_va(image->bo) + image->offset : 0;
- uint64_t va = gpu_address;
+ uint64_t va = gpu_address + plane->offset;
enum chip_class chip_class = device->physical_device->rad_info.chip_class;
uint64_t meta_va = 0;
if (chip_class >= GFX9) {
if (is_stencil)
- va += image->surface.u.gfx9.stencil_offset;
+ va += plane->surface.u.gfx9.stencil_offset;
else
- va += image->surface.u.gfx9.surf_offset;
+ va += plane->surface.u.gfx9.surf_offset;
} else
va += base_level_info->offset;
state[0] = va >> 8;
if (chip_class >= GFX9 ||
base_level_info->mode == RADEON_SURF_MODE_2D)
- state[0] |= image->surface.tile_swizzle;
+ state[0] |= plane->surface.tile_swizzle;
state[1] &= C_008F14_BASE_ADDRESS_HI;
state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
- if (chip_class >= VI) {
+ if (chip_class >= GFX8) {
state[6] &= C_008F28_COMPRESSION_EN;
state[7] = 0;
if (!is_storage_image && radv_dcc_enabled(image, first_level)) {
meta_va = gpu_address + image->dcc_offset;
- if (chip_class <= VI)
+ if (chip_class <= GFX8)
meta_va += base_level_info->dcc_offset;
} else if (!is_storage_image &&
radv_image_is_tc_compat_htile(image)) {
if (meta_va) {
state[6] |= S_008F28_COMPRESSION_EN(1);
state[7] = meta_va >> 8;
- state[7] |= image->surface.tile_swizzle;
+ state[7] |= plane->surface.tile_swizzle;
}
}
if (chip_class >= GFX9) {
state[3] &= C_008F1C_SW_MODE;
- state[4] &= C_008F20_PITCH_GFX9;
+ state[4] &= C_008F20_PITCH;
if (is_stencil) {
- state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.stencil.swizzle_mode);
- state[4] |= S_008F20_PITCH_GFX9(image->surface.u.gfx9.stencil.epitch);
+ state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.stencil.swizzle_mode);
+ state[4] |= S_008F20_PITCH(plane->surface.u.gfx9.stencil.epitch);
} else {
- state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.surf.swizzle_mode);
- state[4] |= S_008F20_PITCH_GFX9(image->surface.u.gfx9.surf.epitch);
+ state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.surf.swizzle_mode);
+ state[4] |= S_008F20_PITCH(plane->surface.u.gfx9.surf.epitch);
}
state[5] &= C_008F24_META_DATA_ADDRESS &
struct gfx9_surf_meta_flags meta;
if (image->dcc_offset)
- meta = image->surface.u.gfx9.dcc;
+ meta = plane->surface.u.gfx9.dcc;
else
- meta = image->surface.u.gfx9.htile;
+ meta = plane->surface.u.gfx9.htile;
state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |
S_008F24_META_RB_ALIGNED(meta.rb_aligned);
}
} else {
- /* SI-CI-VI */
+ /* GFX6-GFX8 */
unsigned pitch = base_level_info->nblk_x * block_width;
- unsigned index = si_tile_mode_index(image, base_level, is_stencil);
+ unsigned index = si_tile_mode_index(plane, base_level, is_stencil);
state[3] &= C_008F1C_TILING_INDEX;
state[3] |= S_008F1C_TILING_INDEX(index);
- state[4] &= C_008F20_PITCH_GFX6;
- state[4] |= S_008F20_PITCH_GFX6(pitch - 1);
+ state[4] &= C_008F20_PITCH;
+ state[4] |= S_008F20_PITCH(pitch - 1);
}
}
depth = image->info.array_size / 6;
state[0] = 0;
- state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
- S_008F14_NUM_FORMAT_GFX6(num_format));
+ state[1] = (S_008F14_DATA_FORMAT(data_format) |
+ S_008F14_NUM_FORMAT(num_format));
state[2] = (S_008F18_WIDTH(width - 1) |
S_008F18_HEIGHT(height - 1) |
S_008F18_PERF_MOD(4));
/* The last dword is unused by hw. The shader uses it to clear
* bits in the first dword of sampler state.
*/
- if (device->physical_device->rad_info.chip_class <= CIK && image->info.samples <= 1) {
+ if (device->physical_device->rad_info.chip_class <= GFX7 && image->info.samples <= 1) {
if (first_level == last_level)
state[7] = C_008F30_MAX_ANISO_RATIO;
else
uint64_t gpu_address = radv_buffer_get_va(image->bo);
uint64_t va;
+ assert(image->plane_count == 1);
+
va = gpu_address + image->offset + image->fmask.offset;
if (device->physical_device->rad_info.chip_class >= GFX9) {
fmask_state[0] = va >> 8;
fmask_state[0] |= image->fmask.tile_swizzle;
fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
- S_008F14_DATA_FORMAT_GFX6(fmask_format) |
- S_008F14_NUM_FORMAT_GFX6(num_format);
+ S_008F14_DATA_FORMAT(fmask_format) |
+ S_008F14_NUM_FORMAT(num_format);
fmask_state[2] = S_008F18_WIDTH(width - 1) |
S_008F18_HEIGHT(height - 1);
fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
fmask_state[7] = 0;
if (device->physical_device->rad_info.chip_class >= GFX9) {
- fmask_state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.fmask.swizzle_mode);
+ fmask_state[3] |= S_008F1C_SW_MODE(image->planes[0].surface.u.gfx9.fmask.swizzle_mode);
fmask_state[4] |= S_008F20_DEPTH(last_layer) |
- S_008F20_PITCH_GFX9(image->surface.u.gfx9.fmask.epitch);
- fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(image->surface.u.gfx9.cmask.pipe_aligned) |
- S_008F24_META_RB_ALIGNED(image->surface.u.gfx9.cmask.rb_aligned);
+ S_008F20_PITCH(image->planes[0].surface.u.gfx9.fmask.epitch);
+ fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(image->planes[0].surface.u.gfx9.cmask.pipe_aligned) |
+ S_008F24_META_RB_ALIGNED(image->planes[0].surface.u.gfx9.cmask.rb_aligned);
} else {
fmask_state[3] |= S_008F1C_TILING_INDEX(image->fmask.tile_mode_index);
fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
- S_008F20_PITCH_GFX6(image->fmask.pitch_in_pixels - 1);
+ S_008F20_PITCH(image->fmask.pitch_in_pixels - 1);
fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
}
} else if (fmask_state)
static const VkComponentMapping fixedmapping;
uint32_t desc[8], i;
+ assert(image->plane_count == 1);
+
/* Metadata image format format version 1:
* [0] = 1 (metadata format identifier)
* [1] = (VENDOR_ID << 16) | PCI_ID
image->info.depth,
desc, NULL);
- si_set_mutable_tex_desc_fields(device, image, &image->surface.u.legacy.level[0], 0, 0,
- image->surface.blk_w, false, false, desc);
+ si_set_mutable_tex_desc_fields(device, image, &image->planes[0].surface.u.legacy.level[0], 0, 0, 0,
+ image->planes[0].surface.blk_w, false, false, desc);
/* Clear the base address and set the relative DCC offset. */
desc[0] = 0;
memcpy(&md->metadata[2], desc, sizeof(desc));
/* Dwords [10:..] contain the mipmap level offsets. */
- if (device->physical_device->rad_info.chip_class <= VI) {
+ if (device->physical_device->rad_info.chip_class <= GFX8) {
for (i = 0; i <= image->info.levels - 1; i++)
- md->metadata[10+i] = image->surface.u.legacy.level[i].offset >> 8;
+ md->metadata[10+i] = image->planes[0].surface.u.legacy.level[i].offset >> 8;
md->size_metadata = (11 + image->info.levels - 1) * 4;
}
}
struct radv_image *image,
struct radeon_bo_metadata *metadata)
{
- struct radeon_surf *surface = &image->surface;
+ struct radeon_surf *surface = &image->planes[0].surface;
memset(metadata, 0, sizeof(*metadata));
radv_query_opaque_metadata(device, image, metadata);
}
+void
+radv_image_override_offset_stride(struct radv_device *device,
+ struct radv_image *image,
+ uint64_t offset, uint32_t stride)
+{
+ struct radeon_surf *surface = &image->planes[0].surface;
+ unsigned bpe = vk_format_get_blocksizebits(image->vk_format) / 8;
+
+ if (device->physical_device->rad_info.chip_class >= GFX9) {
+ if (stride) {
+ surface->u.gfx9.surf_pitch = stride;
+ surface->u.gfx9.surf_slice_size =
+ (uint64_t)stride * surface->u.gfx9.surf_height * bpe;
+ }
+ surface->u.gfx9.surf_offset = offset;
+ } else {
+ surface->u.legacy.level[0].nblk_x = stride;
+ surface->u.legacy.level[0].slice_size_dw =
+ ((uint64_t)stride * surface->u.legacy.level[0].nblk_y * bpe) / 4;
+
+ if (offset) {
+ for (unsigned i = 0; i < ARRAY_SIZE(surface->u.legacy.level); ++i)
+ surface->u.legacy.level[i].offset += offset;
+ }
+
+ }
+}
+
/* The number of samples can be specified independently of the texture. */
static void
radv_image_get_fmask_info(struct radv_device *device,
struct radv_fmask_info *out)
{
if (device->physical_device->rad_info.chip_class >= GFX9) {
- out->alignment = image->surface.fmask_alignment;
- out->size = image->surface.fmask_size;
- out->tile_swizzle = image->surface.fmask_tile_swizzle;
+ out->alignment = image->planes[0].surface.fmask_alignment;
+ out->size = image->planes[0].surface.fmask_size;
+ out->tile_swizzle = image->planes[0].surface.fmask_tile_swizzle;
return;
}
- out->slice_tile_max = image->surface.u.legacy.fmask.slice_tile_max;
- out->tile_mode_index = image->surface.u.legacy.fmask.tiling_index;
- out->pitch_in_pixels = image->surface.u.legacy.fmask.pitch_in_pixels;
- out->bank_height = image->surface.u.legacy.fmask.bankh;
- out->tile_swizzle = image->surface.fmask_tile_swizzle;
- out->alignment = image->surface.fmask_alignment;
- out->size = image->surface.fmask_size;
+ out->slice_tile_max = image->planes[0].surface.u.legacy.fmask.slice_tile_max;
+ out->tile_mode_index = image->planes[0].surface.u.legacy.fmask.tiling_index;
+ out->pitch_in_pixels = image->planes[0].surface.u.legacy.fmask.pitch_in_pixels;
+ out->bank_height = image->planes[0].surface.u.legacy.fmask.bankh;
+ out->tile_swizzle = image->planes[0].surface.fmask_tile_swizzle;
+ out->alignment = image->planes[0].surface.fmask_alignment;
+ out->size = image->planes[0].surface.fmask_size;
assert(!out->tile_swizzle || !image->shareable);
}
unsigned num_pipes = device->physical_device->rad_info.num_tile_pipes;
unsigned cl_width, cl_height;
+ assert(image->plane_count == 1);
+
if (device->physical_device->rad_info.chip_class >= GFX9) {
- out->alignment = image->surface.cmask_alignment;
- out->size = image->surface.cmask_size;
+ out->alignment = image->planes[0].surface.cmask_alignment;
+ out->size = image->planes[0].surface.cmask_size;
return;
}
unsigned base_align = num_pipes * pipe_interleave_bytes;
- unsigned width = align(image->surface.u.legacy.level[0].nblk_x, cl_width*8);
- unsigned height = align(image->surface.u.legacy.level[0].nblk_y, cl_height*8);
+ unsigned width = align(image->planes[0].surface.u.legacy.level[0].nblk_x, cl_width*8);
+ unsigned height = align(image->planes[0].surface.u.legacy.level[0].nblk_y, cl_height*8);
unsigned slice_elements = (width * height) / (8*8);
/* Each element of CMASK is a nibble. */
static void
radv_image_alloc_dcc(struct radv_image *image)
{
- image->dcc_offset = align64(image->size, image->surface.dcc_alignment);
+ assert(image->plane_count == 1);
+
+ image->dcc_offset = align64(image->size, image->planes[0].surface.dcc_alignment);
/* + 16 for storing the clear values + dcc pred */
- image->clear_value_offset = image->dcc_offset + image->surface.dcc_size;
+ image->clear_value_offset = image->dcc_offset + image->planes[0].surface.dcc_size;
image->fce_pred_offset = image->clear_value_offset + 8;
image->dcc_pred_offset = image->clear_value_offset + 16;
- image->size = image->dcc_offset + image->surface.dcc_size + 24;
- image->alignment = MAX2(image->alignment, image->surface.dcc_alignment);
+ image->size = image->dcc_offset + image->planes[0].surface.dcc_size + 24;
+ image->alignment = MAX2(image->alignment, image->planes[0].surface.dcc_alignment);
}
static void
radv_image_alloc_htile(struct radv_image *image)
{
- image->htile_offset = align64(image->size, image->surface.htile_alignment);
+ image->htile_offset = align64(image->size, image->planes[0].surface.htile_alignment);
/* + 8 for storing the clear values */
- image->clear_value_offset = image->htile_offset + image->surface.htile_size;
+ image->clear_value_offset = image->htile_offset + image->planes[0].surface.htile_size;
image->size = image->clear_value_offset + 8;
if (radv_image_is_tc_compat_htile(image)) {
/* Metadata for the TC-compatible HTILE hardware bug which
image->tc_compat_zrange_offset = image->clear_value_offset + 8;
image->size = image->clear_value_offset + 16;
}
- image->alignment = align64(image->alignment, image->surface.htile_alignment);
+ image->alignment = align64(image->alignment, image->planes[0].surface.htile_alignment);
}
static inline bool
static inline bool
radv_image_can_enable_cmask(struct radv_image *image)
{
- if (image->surface.bpe > 8 && image->info.samples == 1) {
+ if (image->planes[0].surface.bpe > 8 && image->info.samples == 1) {
/* Do not enable CMASK for non-MSAA images (fast color clear)
* because 128 bit formats are not supported, but FMASK might
* still be used.
return radv_image_can_enable_dcc_or_cmask(image) &&
image->info.levels == 1 &&
image->info.depth == 1 &&
- !image->surface.is_linear;
+ !image->planes[0].surface.is_linear;
}
static inline bool
image->info.width * image->info.height >= 8 * 8;
}
+static void radv_image_disable_dcc(struct radv_image *image)
+{
+ for (unsigned i = 0; i < image->plane_count; ++i)
+ image->planes[i].surface.dcc_size = 0;
+}
+
+static void radv_image_disable_htile(struct radv_image *image)
+{
+ for (unsigned i = 0; i < image->plane_count; ++i)
+ image->planes[i].surface.htile_size = 0;
+}
+
VkResult
radv_image_create(VkDevice _device,
const struct radv_image_create_info *create_info,
struct radv_image *image = NULL;
assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
+ const unsigned plane_count = vk_format_get_plane_count(pCreateInfo->format);
+ const size_t image_struct_size = sizeof(*image) + sizeof(struct radv_image_plane) * plane_count;
+
radv_assert(pCreateInfo->mipLevels > 0);
radv_assert(pCreateInfo->arrayLayers > 0);
radv_assert(pCreateInfo->samples > 0);
radv_assert(pCreateInfo->extent.height > 0);
radv_assert(pCreateInfo->extent.depth > 0);
- image = vk_zalloc2(&device->alloc, alloc, sizeof(*image), 8,
+ image = vk_zalloc2(&device->alloc, alloc, image_struct_size, 8,
VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
if (!image)
return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
image->shareable = vk_find_struct_const(pCreateInfo->pNext,
EXTERNAL_MEMORY_IMAGE_CREATE_INFO) != NULL;
- if (!vk_format_is_depth_or_stencil(pCreateInfo->format) && !create_info->scanout && !image->shareable) {
+ if (!vk_format_is_depth_or_stencil(pCreateInfo->format) &&
+ !radv_surface_has_scanout(device, create_info) && !image->shareable) {
image->info.surf_index = &device->image_mrt_offset_counter;
}
- radv_init_surface(device, image, &image->surface, create_info);
+ image->plane_count = plane_count;
+ image->size = 0;
+ image->alignment = 1;
+ for (unsigned plane = 0; plane < plane_count; ++plane) {
+ struct ac_surf_info info = image->info;
+ radv_init_surface(device, image, &image->planes[plane].surface, plane, create_info);
+
+ if (plane) {
+ const struct vk_format_description *desc = vk_format_description(pCreateInfo->format);
+ assert(info.width % desc->width_divisor == 0);
+ assert(info.height % desc->height_divisor == 0);
- device->ws->surface_init(device->ws, &image->info, &image->surface);
+ info.width /= desc->width_divisor;
+ info.height /= desc->height_divisor;
+ }
+
+ device->ws->surface_init(device->ws, &info, &image->planes[plane].surface);
- image->size = image->surface.surf_size;
- image->alignment = image->surface.surf_alignment;
+ image->planes[plane].offset = align(image->size, image->planes[plane].surface.surf_alignment);
+ image->size = image->planes[plane].offset + image->planes[plane].surface.surf_size;
+ image->alignment = image->planes[plane].surface.surf_alignment;
+
+ image->planes[plane].format = vk_format_get_plane_format(image->vk_format, plane);
+ }
if (!create_info->no_metadata_planes) {
/* Try to enable DCC first. */
}
} else {
/* When DCC cannot be enabled, try CMASK. */
- image->surface.dcc_size = 0;
+ radv_image_disable_dcc(image);
if (radv_image_can_enable_cmask(image)) {
radv_image_alloc_cmask(device, image);
}
/* Otherwise, try to enable HTILE for depth surfaces. */
if (radv_image_can_enable_htile(image) &&
!(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) {
- image->tc_compatible_htile = image->surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
+ image->tc_compatible_htile = image->planes[0].surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
radv_image_alloc_htile(image);
} else {
- image->surface.htile_size = 0;
+ radv_image_disable_htile(image);
}
}
} else {
- image->surface.dcc_size = 0;
- image->surface.htile_size = 0;
+ radv_image_disable_dcc(image);
+ radv_image_disable_htile(image);
}
if (pCreateInfo->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) {
image->offset = 0;
image->bo = device->ws->buffer_create(device->ws, image->size, image->alignment,
- 0, RADEON_FLAG_VIRTUAL);
+ 0, RADEON_FLAG_VIRTUAL, RADV_BO_PRIORITY_VIRTUAL);
if (!image->bo) {
vk_free2(&device->alloc, alloc, image);
return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
static void
radv_image_view_make_descriptor(struct radv_image_view *iview,
struct radv_device *device,
+ VkFormat vk_format,
const VkComponentMapping *components,
- bool is_storage_image)
+ bool is_storage_image, unsigned plane_id,
+ unsigned descriptor_plane_id)
{
struct radv_image *image = iview->image;
+ struct radv_image_plane *plane = &image->planes[plane_id];
+ const struct vk_format_description *format_desc = vk_format_description(image->vk_format);
bool is_stencil = iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT;
uint32_t blk_w;
- uint32_t *descriptor;
+ union radv_descriptor *descriptor;
uint32_t hw_level = 0;
if (is_storage_image) {
- descriptor = iview->storage_descriptor;
+ descriptor = &iview->storage_descriptor;
} else {
- descriptor = iview->descriptor;
+ descriptor = &iview->descriptor;
}
- assert(image->surface.blk_w % vk_format_get_blockwidth(image->vk_format) == 0);
- blk_w = image->surface.blk_w / vk_format_get_blockwidth(image->vk_format) * vk_format_get_blockwidth(iview->vk_format);
+ assert(vk_format_get_plane_count(vk_format) == 1);
+ assert(plane->surface.blk_w % vk_format_get_blockwidth(plane->format) == 0);
+ blk_w = plane->surface.blk_w / vk_format_get_blockwidth(plane->format) * vk_format_get_blockwidth(vk_format);
if (device->physical_device->rad_info.chip_class >= GFX9)
hw_level = iview->base_mip;
si_make_texture_descriptor(device, image, is_storage_image,
iview->type,
- iview->vk_format,
+ vk_format,
components,
hw_level, hw_level + iview->level_count - 1,
iview->base_layer,
iview->base_layer + iview->layer_count - 1,
- iview->extent.width,
- iview->extent.height,
+ iview->extent.width / (plane_id ? format_desc->width_divisor : 1),
+ iview->extent.height / (plane_id ? format_desc->height_divisor : 1),
iview->extent.depth,
- descriptor,
- descriptor + 8);
+ descriptor->plane_descriptors[descriptor_plane_id],
+ descriptor_plane_id ? NULL : descriptor->fmask_descriptor);
const struct legacy_surf_level *base_level_info = NULL;
if (device->physical_device->rad_info.chip_class <= GFX9) {
if (is_stencil)
- base_level_info = &image->surface.u.legacy.stencil_level[iview->base_mip];
+ base_level_info = &plane->surface.u.legacy.stencil_level[iview->base_mip];
else
- base_level_info = &image->surface.u.legacy.level[iview->base_mip];
+ base_level_info = &plane->surface.u.legacy.level[iview->base_mip];
}
si_set_mutable_tex_desc_fields(device, image,
base_level_info,
+ plane_id,
iview->base_mip,
iview->base_mip,
- blk_w, is_stencil, is_storage_image, descriptor);
+ blk_w, is_stencil, is_storage_image, descriptor->plane_descriptors[descriptor_plane_id]);
+}
+
+static unsigned
+radv_plane_from_aspect(VkImageAspectFlags mask)
+{
+ switch(mask) {
+ case VK_IMAGE_ASPECT_PLANE_1_BIT:
+ return 1;
+ case VK_IMAGE_ASPECT_PLANE_2_BIT:
+ return 2;
+ default:
+ return 0;
+ }
+}
+
+VkFormat
+radv_get_aspect_format(struct radv_image *image, VkImageAspectFlags mask)
+{
+ switch(mask) {
+ case VK_IMAGE_ASPECT_PLANE_0_BIT:
+ return image->planes[0].format;
+ case VK_IMAGE_ASPECT_PLANE_1_BIT:
+ return image->planes[1].format;
+ case VK_IMAGE_ASPECT_PLANE_2_BIT:
+ return image->planes[2].format;
+ case VK_IMAGE_ASPECT_STENCIL_BIT:
+ return vk_format_stencil_only(image->vk_format);
+ case VK_IMAGE_ASPECT_DEPTH_BIT:
+ return vk_format_depth_only(image->vk_format);
+ case VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT:
+ return vk_format_depth_only(image->vk_format);
+ default:
+ return image->vk_format;
+ }
}
void
iview->image = image;
iview->bo = image->bo;
iview->type = pCreateInfo->viewType;
- iview->vk_format = pCreateInfo->format;
+ iview->plane_id = radv_plane_from_aspect(pCreateInfo->subresourceRange.aspectMask);
iview->aspect_mask = pCreateInfo->subresourceRange.aspectMask;
+ iview->multiple_planes = vk_format_get_plane_count(image->vk_format) > 1 && iview->aspect_mask == VK_IMAGE_ASPECT_COLOR_BIT;
+ iview->vk_format = pCreateInfo->format;
if (iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
iview->vk_format = vk_format_stencil_only(iview->vk_format);
};
}
- if (iview->vk_format != image->vk_format) {
+ if (iview->vk_format != image->planes[iview->plane_id].format) {
unsigned view_bw = vk_format_get_blockwidth(iview->vk_format);
unsigned view_bh = vk_format_get_blockheight(iview->vk_format);
unsigned img_bw = vk_format_get_blockwidth(image->vk_format);
lvl_width <<= range->baseMipLevel;
lvl_height <<= range->baseMipLevel;
- iview->extent.width = CLAMP(lvl_width, iview->extent.width, iview->image->surface.u.gfx9.surf_pitch);
- iview->extent.height = CLAMP(lvl_height, iview->extent.height, iview->image->surface.u.gfx9.surf_height);
+ iview->extent.width = CLAMP(lvl_width, iview->extent.width, iview->image->planes[0].surface.u.gfx9.surf_pitch);
+ iview->extent.height = CLAMP(lvl_height, iview->extent.height, iview->image->planes[0].surface.u.gfx9.surf_height);
}
}
iview->base_mip = range->baseMipLevel;
iview->level_count = radv_get_levelCount(image, range);
- radv_image_view_make_descriptor(iview, device, &pCreateInfo->components, false);
- radv_image_view_make_descriptor(iview, device, &pCreateInfo->components, true);
+ for (unsigned i = 0; i < (iview->multiple_planes ? vk_format_get_plane_count(image->vk_format) : 1); ++i) {
+ VkFormat format = vk_format_get_plane_format(iview->vk_format, i);
+ radv_image_view_make_descriptor(iview, device, format, &pCreateInfo->components, false, iview->plane_id + i, i);
+ radv_image_view_make_descriptor(iview, device, format, &pCreateInfo->components, true, iview->plane_id + i, i);
+ }
}
bool radv_layout_has_htile(const struct radv_image *image,
return radv_image_has_htile(image) &&
(layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
- layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL) &&
- queue_mask == (1u << RADV_QUEUE_GENERAL);
+ (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
+ queue_mask == (1u << RADV_QUEUE_GENERAL)));
}
bool radv_layout_is_htile_compressed(const struct radv_image *image,
return radv_image_has_htile(image) &&
(layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
- layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL) &&
- queue_mask == (1u << RADV_QUEUE_GENERAL);
+ (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
+ queue_mask == (1u << RADV_QUEUE_GENERAL)));
}
bool radv_layout_can_fast_clear(const struct radv_image *image,
VkImageLayout layout,
unsigned queue_mask)
{
- return layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL &&
- queue_mask == (1u << RADV_QUEUE_GENERAL);
+ return layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL;
}
bool radv_layout_dcc_compressed(const struct radv_image *image,
RADV_FROM_HANDLE(radv_device, device, _device);
int level = pSubresource->mipLevel;
int layer = pSubresource->arrayLayer;
- struct radeon_surf *surface = &image->surface;
+
+ unsigned plane_id = radv_plane_from_aspect(pSubresource->aspectMask);
+
+ struct radv_image_plane *plane = &image->planes[plane_id];
+ struct radeon_surf *surface = &plane->surface;
if (device->physical_device->rad_info.chip_class >= GFX9) {
- pLayout->offset = surface->u.gfx9.offset[level] + surface->u.gfx9.surf_slice_size * layer;
- pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe;
+ pLayout->offset = plane->offset + surface->u.gfx9.offset[level] + surface->u.gfx9.surf_slice_size * layer;
+ if (image->vk_format == VK_FORMAT_R32G32B32_UINT ||
+ image->vk_format == VK_FORMAT_R32G32B32_SINT ||
+ image->vk_format == VK_FORMAT_R32G32B32_SFLOAT) {
+ /* Adjust the number of bytes between each row because
+ * the pitch is actually the number of components per
+ * row.
+ */
+ pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe / 3;
+ } else {
+ assert(util_is_power_of_two_nonzero(surface->bpe));
+ pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe;
+ }
+
pLayout->arrayPitch = surface->u.gfx9.surf_slice_size;
pLayout->depthPitch = surface->u.gfx9.surf_slice_size;
pLayout->size = surface->u.gfx9.surf_slice_size;
if (image->type == VK_IMAGE_TYPE_3D)
pLayout->size *= u_minify(image->info.depth, level);
} else {
- pLayout->offset = surface->u.legacy.level[level].offset + (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4 * layer;
+ pLayout->offset = plane->offset + surface->u.legacy.level[level].offset + (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4 * layer;
pLayout->rowPitch = surface->u.legacy.level[level].nblk_x * surface->bpe;
pLayout->arrayPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
pLayout->depthPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
projects / mesa.git / blobdiff