amd/common: add declare_vs_input_vgprs() helper

[mesa.git] / src / amd / vulkan / radv_image.c

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index b145e81f826313e73133820b96b1c84081eb7e73..b1c4f3340eddd75011e1db77cd34fc0ec46278a2 100644 (file)
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -127,7 +127,7 @@ radv_init_surface(struct radv_device *device,
 
        surface->flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
 
-       bool dcc_compatible_formats = !radv_is_colorbuffer_format_supported(pCreateInfo->format, &blendable);
+       bool dcc_compatible_formats = radv_is_colorbuffer_format_supported(pCreateInfo->format, &blendable);
        if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
                const struct  VkImageFormatListCreateInfoKHR *format_list =
                          (const struct  VkImageFormatListCreateInfoKHR *)
@@ -416,6 +416,12 @@ si_make_texture_descriptor(struct radv_device *device,
                data_format = 0;
        }
 
+       /* S8 with Z32 HTILE needs a special format. */
+       if (device->physical_device->rad_info.chip_class >= GFX9 &&
+           vk_format == VK_FORMAT_S8_UINT &&
+           image->tc_compatible_htile)
+               data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
+
        type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
                            is_storage_image, device->physical_device->rad_info.chip_class >= GFX9);
        if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
@@ -806,6 +812,16 @@ radv_image_alloc_htile(struct radv_image *image)
 static inline bool
 radv_image_can_enable_dcc_or_cmask(struct radv_image *image)
 {
+       if (image->info.samples <= 1 &&
+           image->info.width * image->info.height <= 512 * 512) {
+               /* Do not enable CMASK or DCC for small surfaces where the cost
+                * of the eliminate pass can be higher than the benefit of fast
+                * clear. RadeonSI does this, but the image threshold is
+                * different.
+                */
+               return false;
+       }
+
        return image->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT &&
               (image->exclusive || image->queue_family_mask == 1);
 }
@@ -1111,11 +1127,15 @@ radv_CreateImage(VkDevice device,
                 const VkAllocationCallbacks *pAllocator,
                 VkImage *pImage)
 {
+       const struct wsi_image_create_info *wsi_info =
+               vk_find_struct_const(pCreateInfo->pNext, WSI_IMAGE_CREATE_INFO_MESA);
+       bool scanout = wsi_info && wsi_info->scanout;
+
        return radv_image_create(device,
                                 &(struct radv_image_create_info) {
                                         .vk_info = pCreateInfo,
-                                                .scanout = false,
-                                                },
+                                        .scanout = scanout,
+                                },
                                 pAllocator,
                                 pImage);
 }