radv: fix buffer views on SI/CIK.

[mesa.git] / src / amd / vulkan / radv_image.c

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 17ee74b5f5b31dd8b7d7ed903955bc180fafc5b0..ce1ee24036ea4f50c954d1bb7acb4882e0efcbc6 100644 (file)
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -32,6 +32,7 @@
 #include "sid.h"
 #include "gfx9d.h"
 #include "util/debug.h"
+#include "util/u_atomic.h"
 static unsigned
 radv_choose_tiling(struct radv_device *Device,
                   const struct radv_image_create_info *create_info)
@@ -108,6 +109,7 @@ radv_init_surface(struct radv_device *device,
                surface->flags |= RADEON_SURF_SBUFFER;
 
        surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
+       surface->flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
 
        if ((pCreateInfo->usage & (VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
                                   VK_IMAGE_USAGE_STORAGE_BIT)) ||
@@ -179,6 +181,11 @@ radv_make_buffer_descriptor(struct radv_device *device,
        state[0] = va;
        state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
                S_008F04_STRIDE(stride);
+
+       if (device->physical_device->rad_info.chip_class < VI && stride) {
+               range /= stride;
+       }
+
        state[2] = range;
        state[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc->swizzle[0])) |
                   S_008F0C_DST_SEL_Y(radv_map_swizzle(desc->swizzle[1])) |
@@ -196,7 +203,7 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
                               unsigned block_width, bool is_stencil,
                               uint32_t *state)
 {
-       uint64_t gpu_address = device->ws->buffer_get_va(image->bo) + image->offset;
+       uint64_t gpu_address = image->bo ? device->ws->buffer_get_va(image->bo) + image->offset : 0;
        uint64_t va = gpu_address;
        unsigned pitch = base_level_info->nblk_x * block_width;
        enum chip_class chip_class = device->physical_device->rad_info.chip_class;
@@ -210,6 +217,8 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
                va += base_level_info->offset;
 
        state[0] = va >> 8;
+       if (chip_class < GFX9)
+               state[0] |= image->surface.u.legacy.tile_swizzle;
        state[1] &= C_008F14_BASE_ADDRESS_HI;
        state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
        state[3] |= S_008F1C_TILING_INDEX(si_tile_mode_index(image, base_level,
@@ -220,12 +229,13 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
                state[6] &= C_008F28_COMPRESSION_EN;
                state[7] = 0;
                if (image->surface.dcc_size && first_level < image->surface.num_dcc_levels) {
-                       uint64_t meta_va = gpu_address + image->dcc_offset;
+                       meta_va = gpu_address + image->dcc_offset;
                        if (chip_class <= VI)
                                meta_va += base_level_info->dcc_offset;
                        state[6] |= S_008F28_COMPRESSION_EN(1);
                        state[7] = meta_va >> 8;
-
+                       if (chip_class < GFX9)
+                               state[7] |= image->surface.u.legacy.tile_swizzle;
                }
        }
 
@@ -473,6 +483,8 @@ si_make_texture_descriptor(struct radv_device *device,
                }
 
                fmask_state[0] = va >> 8;
+               if (device->physical_device->rad_info.chip_class < GFX9)
+                       fmask_state[0] |= image->surface.u.legacy.tile_swizzle;
                fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
                        S_008F14_DATA_FORMAT_GFX6(fmask_format) |
                        S_008F14_NUM_FORMAT_GFX6(num_format);
@@ -706,12 +718,16 @@ static void
 radv_image_alloc_cmask(struct radv_device *device,
                       struct radv_image *image)
 {
+       uint32_t clear_value_size = 0;
        radv_image_get_cmask_info(device, image, &image->cmask);
 
        image->cmask.offset = align64(image->size, image->cmask.alignment);
        /* + 8 for storing the clear values */
-       image->clear_value_offset = image->cmask.offset + image->cmask.size;
-       image->size = image->cmask.offset + image->cmask.size + 8;
+       if (!image->clear_value_offset) {
+               image->clear_value_offset = image->cmask.offset + image->cmask.size;
+               clear_value_size = 8;
+       }
+       image->size = image->cmask.offset + image->cmask.size + clear_value_size;
        image->alignment = MAX2(image->alignment, image->cmask.alignment);
 }
 
@@ -720,9 +736,10 @@ radv_image_alloc_dcc(struct radv_device *device,
                       struct radv_image *image)
 {
        image->dcc_offset = align64(image->size, image->surface.dcc_alignment);
-       /* + 8 for storing the clear values */
+       /* + 16 for storing the clear values + dcc pred */
        image->clear_value_offset = image->dcc_offset + image->surface.dcc_size;
-       image->size = image->dcc_offset + image->surface.dcc_size + 8;
+       image->dcc_pred_offset = image->clear_value_offset + 8;
+       image->size = image->dcc_offset + image->surface.dcc_size + 16;
        image->alignment = MAX2(image->alignment, image->surface.dcc_alignment);
 }
 
@@ -792,6 +809,9 @@ radv_image_create(VkDevice _device,
 
        image->shareable = vk_find_struct_const(pCreateInfo->pNext,
                                                EXTERNAL_MEMORY_IMAGE_CREATE_INFO_KHR) != NULL;
+       if (!vk_format_is_depth(pCreateInfo->format) && !create_info->scanout && !image->shareable) {
+               image->info.surf_index = p_atomic_inc_return(&device->image_mrt_offset_counter) - 1;
+       }
 
        radv_init_surface(device, &image->surface, create_info);
 
@@ -930,10 +950,7 @@ radv_image_view_init(struct radv_image_view *iview,
        iview->base_mip = range->baseMipLevel;
 
        radv_image_view_make_descriptor(iview, device, pCreateInfo, false);
-
-       /* For transfers we may use the image as a storage image. */
-       if (image->usage & (VK_IMAGE_USAGE_STORAGE_BIT | VK_IMAGE_USAGE_TRANSFER_DST_BIT))
-               radv_image_view_make_descriptor(iview, device, pCreateInfo, true);
+       radv_image_view_make_descriptor(iview, device, pCreateInfo, true);
 }
 
 bool radv_layout_has_htile(const struct radv_image *image,