#include "radv_private.h"
#include "vk_format.h"
+#include "vk_util.h"
#include "radv_radeon_winsys.h"
#include "sid.h"
+#include "gfx9d.h"
#include "util/debug.h"
+#include "util/u_atomic.h"
static unsigned
radv_choose_tiling(struct radv_device *Device,
const struct radv_image_create_info *create_info)
return RADEON_SURF_MODE_LINEAR_ALIGNED;
}
+ /* Textures with a very small height are recommended to be linear. */
+ if (pCreateInfo->imageType == VK_IMAGE_TYPE_1D ||
+ /* Only very thin and long 2D textures should benefit from
+ * linear_aligned. */
+ (pCreateInfo->extent.width > 8 && pCreateInfo->extent.height <= 2))
+ return RADEON_SURF_MODE_LINEAR_ALIGNED;
+
/* MSAA resources must be 2D tiled. */
if (pCreateInfo->samples > 1)
return RADEON_SURF_MODE_2D;
is_depth = vk_format_has_depth(desc);
is_stencil = vk_format_has_stencil(desc);
- surface->npix_x = pCreateInfo->extent.width;
- surface->npix_y = pCreateInfo->extent.height;
- surface->npix_z = pCreateInfo->extent.depth;
surface->blk_w = vk_format_get_blockwidth(pCreateInfo->format);
surface->blk_h = vk_format_get_blockheight(pCreateInfo->format);
- surface->blk_d = 1;
- surface->array_size = pCreateInfo->arrayLayers;
- surface->last_level = pCreateInfo->mipLevels - 1;
- surface->bpe = vk_format_get_blocksize(pCreateInfo->format);
+ surface->bpe = vk_format_get_blocksize(vk_format_depth_only(pCreateInfo->format));
/* align byte per element on dword */
if (surface->bpe == 3) {
surface->bpe = 4;
}
- surface->nsamples = pCreateInfo->samples ? pCreateInfo->samples : 1;
surface->flags = RADEON_SURF_SET(array_mode, MODE);
switch (pCreateInfo->imageType){
}
if (is_stencil)
- surface->flags |= RADEON_SURF_SBUFFER |
- RADEON_SURF_HAS_SBUFFER_MIPTREE;
+ surface->flags |= RADEON_SURF_SBUFFER;
surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
+ surface->flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
if ((pCreateInfo->usage & (VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
VK_IMAGE_USAGE_STORAGE_BIT)) ||
(pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) ||
(pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) ||
- device->instance->physicalDevice.rad_info.chip_class < VI ||
- create_info->scanout || !device->allow_dcc ||
+ device->physical_device->rad_info.chip_class < VI ||
+ create_info->scanout || (device->debug_flags & RADV_DEBUG_NO_DCC) ||
!radv_is_colorbuffer_format_supported(pCreateInfo->format, &blendable))
surface->flags |= RADEON_SURF_DISABLE_DCC;
if (create_info->scanout)
#define ATI_VENDOR_ID 0x1002
static uint32_t si_get_bo_metadata_word1(struct radv_device *device)
{
- return (ATI_VENDOR_ID << 16) | device->instance->physicalDevice.rad_info.pci_id;
+ return (ATI_VENDOR_ID << 16) | device->physical_device->rad_info.pci_id;
}
static inline unsigned
si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
{
if (stencil)
- return image->surface.stencil_tiling_index[level];
+ return image->surface.u.legacy.stencil_tiling_index[level];
else
- return image->surface.tiling_index[level];
+ return image->surface.u.legacy.tiling_index[level];
}
static unsigned radv_map_swizzle(unsigned swizzle)
state[0] = va;
state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
S_008F04_STRIDE(stride);
+
+ if (device->physical_device->rad_info.chip_class < VI && stride) {
+ range /= stride;
+ }
+
state[2] = range;
state[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc->swizzle[0])) |
S_008F0C_DST_SEL_Y(radv_map_swizzle(desc->swizzle[1])) |
static void
si_set_mutable_tex_desc_fields(struct radv_device *device,
struct radv_image *image,
- const struct radeon_surf_level *base_level_info,
+ const struct legacy_surf_level *base_level_info,
unsigned base_level, unsigned first_level,
unsigned block_width, bool is_stencil,
uint32_t *state)
{
- uint64_t gpu_address = device->ws->buffer_get_va(image->bo) + image->offset;
- uint64_t va = gpu_address + base_level_info->offset;
+ uint64_t gpu_address = image->bo ? device->ws->buffer_get_va(image->bo) + image->offset : 0;
+ uint64_t va = gpu_address;
unsigned pitch = base_level_info->nblk_x * block_width;
-
- state[1] &= C_008F14_BASE_ADDRESS_HI;
- state[3] &= C_008F1C_TILING_INDEX;
- state[4] &= C_008F20_PITCH;
- state[6] &= C_008F28_COMPRESSION_EN;
-
- assert(!(va & 255));
+ enum chip_class chip_class = device->physical_device->rad_info.chip_class;
+ uint64_t meta_va = 0;
+ if (chip_class >= GFX9) {
+ if (is_stencil)
+ va += image->surface.u.gfx9.stencil_offset;
+ else
+ va += image->surface.u.gfx9.surf_offset;
+ } else
+ va += base_level_info->offset;
state[0] = va >> 8;
+ if (chip_class < GFX9)
+ state[0] |= image->surface.u.legacy.tile_swizzle;
+ state[1] &= C_008F14_BASE_ADDRESS_HI;
state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
state[3] |= S_008F1C_TILING_INDEX(si_tile_mode_index(image, base_level,
is_stencil));
- state[4] |= S_008F20_PITCH(pitch - 1);
+ state[4] |= S_008F20_PITCH_GFX6(pitch - 1);
+
+ if (chip_class >= VI) {
+ state[6] &= C_008F28_COMPRESSION_EN;
+ state[7] = 0;
+ if (image->surface.dcc_size && first_level < image->surface.num_dcc_levels) {
+ meta_va = gpu_address + image->dcc_offset;
+ if (chip_class <= VI)
+ meta_va += base_level_info->dcc_offset;
+ state[6] |= S_008F28_COMPRESSION_EN(1);
+ state[7] = meta_va >> 8;
+ if (chip_class < GFX9)
+ state[7] |= image->surface.u.legacy.tile_swizzle;
+ }
+ }
+
+ if (chip_class >= GFX9) {
+ state[3] &= C_008F1C_SW_MODE;
+ state[4] &= C_008F20_PITCH_GFX9;
+
+ if (is_stencil) {
+ state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.stencil.swizzle_mode);
+ state[4] |= S_008F20_PITCH_GFX9(image->surface.u.gfx9.stencil.epitch);
+ } else {
+ state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.surf.swizzle_mode);
+ state[4] |= S_008F20_PITCH_GFX9(image->surface.u.gfx9.surf.epitch);
+ }
- if (image->surface.dcc_size && image->surface.level[first_level].dcc_enabled) {
- state[6] |= S_008F28_COMPRESSION_EN(1);
- state[7] = (gpu_address +
- image->dcc_offset +
- base_level_info->dcc_offset) >> 8;
+ state[5] &= C_008F24_META_DATA_ADDRESS &
+ C_008F24_META_PIPE_ALIGNED &
+ C_008F24_META_RB_ALIGNED;
+ if (meta_va) {
+ struct gfx9_surf_meta_flags meta;
+
+ if (image->dcc_offset)
+ meta = image->surface.u.gfx9.dcc;
+ else
+ meta = image->surface.u.gfx9.htile;
+
+ state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
+ S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |
+ S_008F24_META_RB_ALIGNED(meta.rb_aligned);
+ }
+ } else {
+ /* SI-CI-VI */
+ unsigned pitch = base_level_info->nblk_x * block_width;
+ unsigned index = si_tile_mode_index(image, base_level, is_stencil);
+
+ state[3] &= C_008F1C_TILING_INDEX;
+ state[3] |= S_008F1C_TILING_INDEX(index);
+ state[4] &= C_008F20_PITCH_GFX6;
+ state[4] |= S_008F20_PITCH_GFX6(pitch - 1);
}
}
unreachable("illegale image type");
}
}
+
+static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
+{
+ unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
+
+ if (swizzle[3] == VK_SWIZZLE_X) {
+ /* For the pre-defined border color values (white, opaque
+ * black, transparent black), the only thing that matters is
+ * that the alpha channel winds up in the correct place
+ * (because the RGB channels are all the same) so either of
+ * these enumerations will work.
+ */
+ if (swizzle[2] == VK_SWIZZLE_Y)
+ bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
+ else
+ bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
+ } else if (swizzle[0] == VK_SWIZZLE_X) {
+ if (swizzle[1] == VK_SWIZZLE_Y)
+ bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
+ else
+ bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
+ } else if (swizzle[1] == VK_SWIZZLE_X) {
+ bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
+ } else if (swizzle[2] == VK_SWIZZLE_X) {
+ bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
+ }
+
+ return bc_swizzle;
+}
+
/**
* Build the sampler view descriptor for a texture.
*/
static void
si_make_texture_descriptor(struct radv_device *device,
struct radv_image *image,
- bool sampler,
+ bool is_storage_image,
VkImageViewType view_type,
VkFormat vk_format,
const VkComponentMapping *mapping,
if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
- const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
-
- switch (vk_format) {
- case VK_FORMAT_X8_D24_UNORM_PACK32:
- case VK_FORMAT_D24_UNORM_S8_UINT:
- case VK_FORMAT_D32_SFLOAT_S8_UINT:
- vk_format_compose_swizzles(mapping, swizzle_yyyy, swizzle);
- break;
- default:
- vk_format_compose_swizzles(mapping, swizzle_xxxx, swizzle);
- }
+ vk_format_compose_swizzles(mapping, swizzle_xxxx, swizzle);
} else {
vk_format_compose_swizzles(mapping, desc->swizzle, swizzle);
}
data_format = 0;
}
- type = radv_tex_dim(image->type, view_type, image->array_size, image->samples,
- (image->usage & VK_IMAGE_USAGE_STORAGE_BIT));
+ type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
+ is_storage_image);
if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
height = 1;
- depth = image->array_size;
+ depth = image->info.array_size;
} else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
if (view_type != VK_IMAGE_VIEW_TYPE_3D)
- depth = image->array_size;
+ depth = image->info.array_size;
} else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
- depth = image->array_size / 6;
+ depth = image->info.array_size / 6;
state[0] = 0;
- state[1] = (S_008F14_DATA_FORMAT(data_format) |
- S_008F14_NUM_FORMAT(num_format));
+ state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
+ S_008F14_NUM_FORMAT_GFX6(num_format));
state[2] = (S_008F18_WIDTH(width - 1) |
- S_008F18_HEIGHT(height - 1));
+ S_008F18_HEIGHT(height - 1) |
+ S_008F18_PERF_MOD(4));
state[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle[0])) |
S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) |
S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) |
S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle[3])) |
- S_008F1C_BASE_LEVEL(image->samples > 1 ?
+ S_008F1C_BASE_LEVEL(image->info.samples > 1 ?
0 : first_level) |
- S_008F1C_LAST_LEVEL(image->samples > 1 ?
- util_logbase2(image->samples) :
+ S_008F1C_LAST_LEVEL(image->info.samples > 1 ?
+ util_logbase2(image->info.samples) :
last_level) |
- S_008F1C_POW2_PAD(image->levels > 1) |
S_008F1C_TYPE(type));
- state[4] = S_008F20_DEPTH(depth - 1);
- state[5] = (S_008F24_BASE_ARRAY(first_layer) |
- S_008F24_LAST_ARRAY(last_layer));
+ state[4] = 0;
+ state[5] = S_008F24_BASE_ARRAY(first_layer);
state[6] = 0;
state[7] = 0;
+ if (device->physical_device->rad_info.chip_class >= GFX9) {
+ unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
+
+ /* Depth is the the last accessible layer on Gfx9.
+ * The hw doesn't need to know the total number of layers.
+ */
+ if (type == V_008F1C_SQ_RSRC_IMG_3D)
+ state[4] |= S_008F20_DEPTH(depth - 1);
+ else
+ state[4] |= S_008F20_DEPTH(last_layer);
+
+ state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
+ state[5] |= S_008F24_MAX_MIP(image->info.samples > 1 ?
+ util_logbase2(image->info.samples) :
+ last_level);
+ } else {
+ state[3] |= S_008F1C_POW2_PAD(image->info.levels > 1);
+ state[4] |= S_008F20_DEPTH(depth - 1);
+ state[5] |= S_008F24_LAST_ARRAY(last_layer);
+ }
if (image->dcc_offset) {
unsigned swap = radv_translate_colorswap(vk_format, FALSE);
/* The last dword is unused by hw. The shader uses it to clear
* bits in the first dword of sampler state.
*/
- if (device->instance->physicalDevice.rad_info.chip_class <= CIK && image->samples <= 1) {
+ if (device->physical_device->rad_info.chip_class <= CIK && image->info.samples <= 1) {
if (first_level == last_level)
state[7] = C_008F30_MAX_ANISO_RATIO;
else
/* Initialize the sampler view for FMASK. */
if (image->fmask.size) {
- uint32_t fmask_format;
+ uint32_t fmask_format, num_format;
uint64_t gpu_address = device->ws->buffer_get_va(image->bo);
uint64_t va;
va = gpu_address + image->offset + image->fmask.offset;
- switch (image->samples) {
- case 2:
- fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
- break;
- case 4:
- fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
- break;
- case 8:
- fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
- break;
- default:
- assert(0);
- fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
+ if (device->physical_device->rad_info.chip_class >= GFX9) {
+ fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK;
+ switch (image->info.samples) {
+ case 2:
+ num_format = V_008F14_IMG_FMASK_8_2_2;
+ break;
+ case 4:
+ num_format = V_008F14_IMG_FMASK_8_4_4;
+ break;
+ case 8:
+ num_format = V_008F14_IMG_FMASK_32_8_8;
+ break;
+ default:
+ unreachable("invalid nr_samples");
+ }
+ } else {
+ switch (image->info.samples) {
+ case 2:
+ fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
+ break;
+ case 4:
+ fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
+ break;
+ case 8:
+ fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
+ break;
+ default:
+ assert(0);
+ fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
+ }
+ num_format = V_008F14_IMG_NUM_FORMAT_UINT;
}
fmask_state[0] = va >> 8;
+ if (device->physical_device->rad_info.chip_class < GFX9)
+ fmask_state[0] |= image->surface.u.legacy.tile_swizzle;
fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
- S_008F14_DATA_FORMAT(fmask_format) |
- S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
+ S_008F14_DATA_FORMAT_GFX6(fmask_format) |
+ S_008F14_NUM_FORMAT_GFX6(num_format);
fmask_state[2] = S_008F18_WIDTH(width - 1) |
S_008F18_HEIGHT(height - 1);
fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
- S_008F1C_TILING_INDEX(image->fmask.tile_mode_index) |
S_008F1C_TYPE(radv_tex_dim(image->type, view_type, 1, 0, false));
- fmask_state[4] = S_008F20_DEPTH(depth - 1) |
- S_008F20_PITCH(image->fmask.pitch_in_pixels - 1);
- fmask_state[5] = S_008F24_BASE_ARRAY(first_layer) |
- S_008F24_LAST_ARRAY(last_layer);
+ fmask_state[4] = 0;
+ fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
fmask_state[6] = 0;
fmask_state[7] = 0;
- }
+
+ if (device->physical_device->rad_info.chip_class >= GFX9) {
+ fmask_state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.fmask.swizzle_mode);
+ fmask_state[4] |= S_008F20_DEPTH(last_layer) |
+ S_008F20_PITCH_GFX9(image->surface.u.gfx9.fmask.epitch);
+ fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(image->surface.u.gfx9.cmask.pipe_aligned) |
+ S_008F24_META_RB_ALIGNED(image->surface.u.gfx9.cmask.rb_aligned);
+ } else {
+ fmask_state[3] |= S_008F1C_TILING_INDEX(image->fmask.tile_mode_index);
+ fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
+ S_008F20_PITCH_GFX6(image->fmask.pitch_in_pixels - 1);
+ fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
+ }
+ } else if (fmask_state)
+ memset(fmask_state, 0, 8 * 4);
}
static void
md->metadata[1] = si_get_bo_metadata_word1(device);
- si_make_texture_descriptor(device, image, true,
+ si_make_texture_descriptor(device, image, false,
(VkImageViewType)image->type, image->vk_format,
- &fixedmapping, 0, image->levels - 1, 0,
- image->array_size,
- image->extent.width, image->extent.height,
- image->extent.depth,
+ &fixedmapping, 0, image->info.levels - 1, 0,
+ image->info.array_size,
+ image->info.width, image->info.height,
+ image->info.depth,
desc, NULL);
- si_set_mutable_tex_desc_fields(device, image, &image->surface.level[0], 0, 0,
+ si_set_mutable_tex_desc_fields(device, image, &image->surface.u.legacy.level[0], 0, 0,
image->surface.blk_w, false, desc);
/* Clear the base address and set the relative DCC offset. */
memcpy(&md->metadata[2], desc, sizeof(desc));
/* Dwords [10:..] contain the mipmap level offsets. */
- for (i = 0; i <= image->levels - 1; i++)
- md->metadata[10+i] = image->surface.level[i].offset >> 8;
+ for (i = 0; i <= image->info.levels - 1; i++)
+ md->metadata[10+i] = image->surface.u.legacy.level[i].offset >> 8;
- md->size_metadata = (11 + image->levels - 1) * 4;
+ md->size_metadata = (11 + image->info.levels - 1) * 4;
}
void
struct radeon_surf *surface = &image->surface;
memset(metadata, 0, sizeof(*metadata));
- metadata->microtile = surface->level[0].mode >= RADEON_SURF_MODE_1D ?
- RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
- metadata->macrotile = surface->level[0].mode >= RADEON_SURF_MODE_2D ?
- RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
- metadata->pipe_config = surface->pipe_config;
- metadata->bankw = surface->bankw;
- metadata->bankh = surface->bankh;
- metadata->tile_split = surface->tile_split;
- metadata->mtilea = surface->mtilea;
- metadata->num_banks = surface->num_banks;
- metadata->stride = surface->level[0].pitch_bytes;
- metadata->scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
+ if (device->physical_device->rad_info.chip_class >= GFX9) {
+ metadata->u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode;
+ } else {
+ metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
+ RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
+ metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
+ RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
+ metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
+ metadata->u.legacy.bankw = surface->u.legacy.bankw;
+ metadata->u.legacy.bankh = surface->u.legacy.bankh;
+ metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
+ metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
+ metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
+ metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
+ metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
+ }
radv_query_opaque_metadata(device, image, metadata);
}
struct radv_fmask_info *out)
{
/* FMASK is allocated like an ordinary texture. */
- struct radeon_surf fmask = image->surface;
-
+ struct radeon_surf fmask = {};
+ struct ac_surf_info info = image->info;
memset(out, 0, sizeof(*out));
- fmask.bo_alignment = 0;
- fmask.bo_size = 0;
- fmask.nsamples = 1;
- fmask.flags |= RADEON_SURF_FMASK;
+ if (device->physical_device->rad_info.chip_class >= GFX9) {
+ out->alignment = image->surface.u.gfx9.fmask_alignment;
+ out->size = image->surface.u.gfx9.fmask_size;
+ return;
+ }
+
+ fmask.blk_w = image->surface.blk_w;
+ fmask.blk_h = image->surface.blk_h;
+ info.samples = 1;
+ fmask.flags = image->surface.flags | RADEON_SURF_FMASK;
/* Force 2D tiling if it wasn't set. This may occur when creating
* FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
fmask.flags = RADEON_SURF_CLR(fmask.flags, MODE);
fmask.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
- fmask.flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
-
switch (nr_samples) {
case 2:
case 4:
return;
}
- device->ws->surface_init(device->ws, &fmask);
- assert(fmask.level[0].mode == RADEON_SURF_MODE_2D);
+ device->ws->surface_init(device->ws, &info, &fmask);
+ assert(fmask.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
- out->slice_tile_max = (fmask.level[0].nblk_x * fmask.level[0].nblk_y) / 64;
+ out->slice_tile_max = (fmask.u.legacy.level[0].nblk_x * fmask.u.legacy.level[0].nblk_y) / 64;
if (out->slice_tile_max)
out->slice_tile_max -= 1;
- out->tile_mode_index = fmask.tiling_index[0];
- out->pitch_in_pixels = fmask.level[0].nblk_x;
- out->bank_height = fmask.bankh;
- out->alignment = MAX2(256, fmask.bo_alignment);
- out->size = fmask.bo_size;
+ out->tile_mode_index = fmask.u.legacy.tiling_index[0];
+ out->pitch_in_pixels = fmask.u.legacy.level[0].nblk_x;
+ out->bank_height = fmask.u.legacy.bankh;
+ out->alignment = MAX2(256, fmask.surf_alignment);
+ out->size = fmask.surf_size;
}
static void
radv_image_alloc_fmask(struct radv_device *device,
struct radv_image *image)
{
- radv_image_get_fmask_info(device, image, image->samples, &image->fmask);
+ radv_image_get_fmask_info(device, image, image->info.samples, &image->fmask);
image->fmask.offset = align64(image->size, image->fmask.alignment);
image->size = image->fmask.offset + image->fmask.size;
+ image->alignment = MAX2(image->alignment, image->fmask.alignment);
}
static void
struct radv_image *image,
struct radv_cmask_info *out)
{
- unsigned pipe_interleave_bytes = device->instance->physicalDevice.rad_info.pipe_interleave_bytes;
- unsigned num_pipes = device->instance->physicalDevice.rad_info.num_tile_pipes;
+ unsigned pipe_interleave_bytes = device->physical_device->rad_info.pipe_interleave_bytes;
+ unsigned num_pipes = device->physical_device->rad_info.num_tile_pipes;
unsigned cl_width, cl_height;
+ if (device->physical_device->rad_info.chip_class >= GFX9) {
+ out->alignment = image->surface.u.gfx9.cmask_alignment;
+ out->size = image->surface.u.gfx9.cmask_size;
+ return;
+ }
+
switch (num_pipes) {
case 2:
cl_width = 32;
unsigned base_align = num_pipes * pipe_interleave_bytes;
- unsigned width = align(image->surface.npix_x, cl_width*8);
- unsigned height = align(image->surface.npix_y, cl_height*8);
+ unsigned width = align(image->info.width, cl_width*8);
+ unsigned height = align(image->info.height, cl_height*8);
unsigned slice_elements = (width * height) / (8*8);
/* Each element of CMASK is a nibble. */
unsigned slice_bytes = slice_elements / 2;
- out->pitch = width;
- out->height = height;
- out->xalign = cl_width * 8;
- out->yalign = cl_height * 8;
out->slice_tile_max = (width * height) / (128*128);
if (out->slice_tile_max)
out->slice_tile_max -= 1;
out->alignment = MAX2(256, base_align);
- out->size = (image->type == VK_IMAGE_TYPE_3D ? image->extent.depth : image->array_size) *
+ out->size = (image->type == VK_IMAGE_TYPE_3D ? image->info.depth : image->info.array_size) *
align(slice_bytes, base_align);
}
radv_image_alloc_cmask(struct radv_device *device,
struct radv_image *image)
{
+ uint32_t clear_value_size = 0;
radv_image_get_cmask_info(device, image, &image->cmask);
image->cmask.offset = align64(image->size, image->cmask.alignment);
/* + 8 for storing the clear values */
- image->clear_value_offset = image->cmask.offset + image->cmask.size;
- image->size = image->cmask.offset + image->cmask.size + 8;
+ if (!image->clear_value_offset) {
+ image->clear_value_offset = image->cmask.offset + image->cmask.size;
+ clear_value_size = 8;
+ }
+ image->size = image->cmask.offset + image->cmask.size + clear_value_size;
+ image->alignment = MAX2(image->alignment, image->cmask.alignment);
}
static void
struct radv_image *image)
{
image->dcc_offset = align64(image->size, image->surface.dcc_alignment);
- /* + 8 for storing the clear values */
+ /* + 16 for storing the clear values + dcc pred */
image->clear_value_offset = image->dcc_offset + image->surface.dcc_size;
- image->size = image->dcc_offset + image->surface.dcc_size + 8;
-}
-
-static unsigned
-radv_image_get_htile_size(struct radv_device *device,
- struct radv_image *image)
-{
- unsigned cl_width, cl_height, width, height;
- unsigned slice_elements, slice_bytes, base_align;
- unsigned num_pipes = device->instance->physicalDevice.rad_info.num_tile_pipes;
- unsigned pipe_interleave_bytes = device->instance->physicalDevice.rad_info.pipe_interleave_bytes;
-
- /* Overalign HTILE on P2 configs to work around GPU hangs in
- * piglit/depthstencil-render-miplevels 585.
- *
- * This has been confirmed to help Kabini & Stoney, where the hangs
- * are always reproducible. I think I have seen the test hang
- * on Carrizo too, though it was very rare there.
- */
- if (device->instance->physicalDevice.rad_info.chip_class >= CIK && num_pipes < 4)
- num_pipes = 4;
-
- switch (num_pipes) {
- case 1:
- cl_width = 32;
- cl_height = 16;
- break;
- case 2:
- cl_width = 32;
- cl_height = 32;
- break;
- case 4:
- cl_width = 64;
- cl_height = 32;
- break;
- case 8:
- cl_width = 64;
- cl_height = 64;
- break;
- case 16:
- cl_width = 128;
- cl_height = 64;
- break;
- default:
- assert(0);
- return 0;
- }
-
- width = align(image->surface.npix_x, cl_width * 8);
- height = align(image->surface.npix_y, cl_height * 8);
-
- slice_elements = (width * height) / (8 * 8);
- slice_bytes = slice_elements * 4;
-
- base_align = num_pipes * pipe_interleave_bytes;
-
- image->htile.pitch = width;
- image->htile.height = height;
- image->htile.xalign = cl_width * 8;
- image->htile.yalign = cl_height * 8;
-
- return image->array_size *
- align(slice_bytes, base_align);
+ image->dcc_pred_offset = image->clear_value_offset + 8;
+ image->size = image->dcc_offset + image->surface.dcc_size + 16;
+ image->alignment = MAX2(image->alignment, image->surface.dcc_alignment);
}
static void
radv_image_alloc_htile(struct radv_device *device,
struct radv_image *image)
{
- if (env_var_as_boolean("RADV_HIZ_DISABLE", false))
- return;
-
- image->htile.size = radv_image_get_htile_size(device, image);
-
- if (!image->htile.size)
+ if ((device->debug_flags & RADV_DEBUG_NO_HIZ) || image->info.levels > 1) {
+ image->surface.htile_size = 0;
return;
+ }
- image->htile.offset = align64(image->size, 32768);
+ image->htile_offset = align64(image->size, image->surface.htile_alignment);
/* + 8 for storing the clear values */
- image->clear_value_offset = image->htile.offset + image->htile.size;
- image->size = image->htile.offset + image->htile.size + 8;
- image->alignment = align64(image->alignment, 32768);
+ image->clear_value_offset = image->htile_offset + image->surface.htile_size;
+ image->size = image->clear_value_offset + 8;
+ image->alignment = align64(image->alignment, image->surface.htile_alignment);
}
VkResult
RADV_FROM_HANDLE(radv_device, device, _device);
const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
struct radv_image *image = NULL;
-
+ bool can_cmask_dcc = false;
assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
radv_assert(pCreateInfo->mipLevels > 0);
memset(image, 0, sizeof(*image));
image->type = pCreateInfo->imageType;
- image->extent = pCreateInfo->extent;
+ image->info.width = pCreateInfo->extent.width;
+ image->info.height = pCreateInfo->extent.height;
+ image->info.depth = pCreateInfo->extent.depth;
+ image->info.samples = pCreateInfo->samples;
+ image->info.array_size = pCreateInfo->arrayLayers;
+ image->info.levels = pCreateInfo->mipLevels;
+
image->vk_format = pCreateInfo->format;
- image->levels = pCreateInfo->mipLevels;
- image->array_size = pCreateInfo->arrayLayers;
- image->samples = pCreateInfo->samples;
image->tiling = pCreateInfo->tiling;
image->usage = pCreateInfo->usage;
+ image->flags = pCreateInfo->flags;
+
+ image->exclusive = pCreateInfo->sharingMode == VK_SHARING_MODE_EXCLUSIVE;
+ if (pCreateInfo->sharingMode == VK_SHARING_MODE_CONCURRENT) {
+ for (uint32_t i = 0; i < pCreateInfo->queueFamilyIndexCount; ++i)
+ if (pCreateInfo->pQueueFamilyIndices[i] == VK_QUEUE_FAMILY_EXTERNAL_KHR)
+ image->queue_family_mask |= (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
+ else
+ image->queue_family_mask |= 1u << pCreateInfo->pQueueFamilyIndices[i];
+ }
+
+ image->shareable = vk_find_struct_const(pCreateInfo->pNext,
+ EXTERNAL_MEMORY_IMAGE_CREATE_INFO_KHR) != NULL;
+ if (!vk_format_is_depth(pCreateInfo->format) && !create_info->scanout && !image->shareable) {
+ image->info.surf_index = p_atomic_inc_return(&device->image_mrt_offset_counter) - 1;
+ }
+
radv_init_surface(device, &image->surface, create_info);
- device->ws->surface_init(device->ws, &image->surface);
+ device->ws->surface_init(device->ws, &image->info, &image->surface);
+
+ image->size = image->surface.surf_size;
+ image->alignment = image->surface.surf_alignment;
- image->size = image->surface.bo_size;
- image->alignment = image->surface.bo_alignment;
+ if (image->exclusive || image->queue_family_mask == 1)
+ can_cmask_dcc = true;
if ((pCreateInfo->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT) &&
- image->surface.dcc_size)
+ image->surface.dcc_size && can_cmask_dcc)
radv_image_alloc_dcc(device, image);
else
image->surface.dcc_size = 0;
if ((pCreateInfo->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT) &&
pCreateInfo->mipLevels == 1 &&
- !image->surface.dcc_size && image->extent.depth == 1)
+ !image->surface.dcc_size && image->info.depth == 1 && can_cmask_dcc)
radv_image_alloc_cmask(device, image);
- if (image->samples > 1 && vk_format_is_color(pCreateInfo->format)) {
+ if (image->info.samples > 1 && vk_format_is_color(pCreateInfo->format)) {
radv_image_alloc_fmask(device, image);
} else if (vk_format_is_depth(pCreateInfo->format)) {
radv_image_alloc_htile(device, image);
}
+ if (pCreateInfo->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) {
+ image->alignment = MAX2(image->alignment, 4096);
+ image->size = align64(image->size, image->alignment);
+ image->offset = 0;
- if (create_info->stride && create_info->stride != image->surface.level[0].pitch_bytes) {
- image->surface.level[0].nblk_x = create_info->stride / image->surface.bpe;
- image->surface.level[0].pitch_bytes = create_info->stride;
- image->surface.level[0].slice_size = create_info->stride * image->surface.level[0].nblk_y;
+ image->bo = device->ws->buffer_create(device->ws, image->size, image->alignment,
+ 0, RADEON_FLAG_VIRTUAL);
+ if (!image->bo) {
+ vk_free2(&device->alloc, alloc, image);
+ return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
+ }
}
+
*pImage = radv_image_to_handle(image);
return VK_SUCCESS;
}
+static void
+radv_image_view_make_descriptor(struct radv_image_view *iview,
+ struct radv_device *device,
+ const VkImageViewCreateInfo* pCreateInfo,
+ bool is_storage_image)
+{
+ RADV_FROM_HANDLE(radv_image, image, pCreateInfo->image);
+ const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
+ bool is_stencil = iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT;
+ uint32_t blk_w;
+ uint32_t *descriptor;
+ uint32_t *fmask_descriptor;
+
+ if (is_storage_image) {
+ descriptor = iview->storage_descriptor;
+ fmask_descriptor = iview->storage_fmask_descriptor;
+ } else {
+ descriptor = iview->descriptor;
+ fmask_descriptor = iview->fmask_descriptor;
+ }
+
+ assert(image->surface.blk_w % vk_format_get_blockwidth(image->vk_format) == 0);
+ blk_w = image->surface.blk_w / vk_format_get_blockwidth(image->vk_format) * vk_format_get_blockwidth(iview->vk_format);
+
+ si_make_texture_descriptor(device, image, is_storage_image,
+ iview->type,
+ iview->vk_format,
+ &pCreateInfo->components,
+ 0, radv_get_levelCount(image, range) - 1,
+ range->baseArrayLayer,
+ range->baseArrayLayer + radv_get_layerCount(image, range) - 1,
+ iview->extent.width,
+ iview->extent.height,
+ iview->extent.depth,
+ descriptor,
+ fmask_descriptor);
+ si_set_mutable_tex_desc_fields(device, image,
+ is_stencil ? &image->surface.u.legacy.stencil_level[range->baseMipLevel]
+ : &image->surface.u.legacy.level[range->baseMipLevel],
+ range->baseMipLevel,
+ range->baseMipLevel,
+ blk_w, is_stencil, descriptor);
+}
+
void
radv_image_view_init(struct radv_image_view *iview,
struct radv_device *device,
- const VkImageViewCreateInfo* pCreateInfo,
- struct radv_cmd_buffer *cmd_buffer,
- VkImageUsageFlags usage_mask)
+ const VkImageViewCreateInfo* pCreateInfo)
{
RADV_FROM_HANDLE(radv_image, image, pCreateInfo->image);
const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
- bool is_stencil = false;
+
switch (image->type) {
case VK_IMAGE_TYPE_1D:
case VK_IMAGE_TYPE_2D:
- assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1 <= image->array_size);
+ assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1 <= image->info.array_size);
break;
case VK_IMAGE_TYPE_3D:
assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1
- <= radv_minify(image->extent.depth, range->baseMipLevel));
+ <= radv_minify(image->info.depth, range->baseMipLevel));
break;
default:
unreachable("bad VkImageType");
iview->vk_format = pCreateInfo->format;
iview->aspect_mask = pCreateInfo->subresourceRange.aspectMask;
- if (iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT)
- is_stencil = true;
+ if (iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
+ iview->vk_format = vk_format_stencil_only(iview->vk_format);
+ } else if (iview->aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
+ iview->vk_format = vk_format_depth_only(iview->vk_format);
+ }
+
iview->extent = (VkExtent3D) {
- .width = radv_minify(image->extent.width , range->baseMipLevel),
- .height = radv_minify(image->extent.height, range->baseMipLevel),
- .depth = radv_minify(image->extent.depth , range->baseMipLevel),
+ .width = radv_minify(image->info.width , range->baseMipLevel),
+ .height = radv_minify(image->info.height, range->baseMipLevel),
+ .depth = radv_minify(image->info.depth , range->baseMipLevel),
};
iview->extent.width = round_up_u32(iview->extent.width * vk_format_get_blockwidth(iview->vk_format),
iview->layer_count = radv_get_layerCount(image, range);
iview->base_mip = range->baseMipLevel;
- si_make_texture_descriptor(device, image, false,
- iview->type,
- pCreateInfo->format,
- &pCreateInfo->components,
- 0, radv_get_levelCount(image, range) - 1,
- range->baseArrayLayer,
- range->baseArrayLayer + radv_get_layerCount(image, range) - 1,
- iview->extent.width,
- iview->extent.height,
- iview->extent.depth,
- iview->descriptor,
- iview->fmask_descriptor);
- si_set_mutable_tex_desc_fields(device, image,
- is_stencil ? &image->surface.stencil_level[range->baseMipLevel] : &image->surface.level[range->baseMipLevel], range->baseMipLevel,
- range->baseMipLevel,
- image->surface.blk_w, is_stencil, iview->descriptor);
-}
-
-void radv_image_set_optimal_micro_tile_mode(struct radv_device *device,
- struct radv_image *image, uint32_t micro_tile_mode)
-{
- /* These magic numbers were copied from addrlib. It doesn't use any
- * definitions for them either. They are all 2D_TILED_THIN1 modes with
- * different bpp and micro tile mode.
- */
- if (device->instance->physicalDevice.rad_info.chip_class >= CIK) {
- switch (micro_tile_mode) {
- case 0: /* displayable */
- image->surface.tiling_index[0] = 10;
- break;
- case 1: /* thin */
- image->surface.tiling_index[0] = 14;
- break;
- case 3: /* rotated */
- image->surface.tiling_index[0] = 28;
- break;
- default: /* depth, thick */
- assert(!"unexpected micro mode");
- return;
- }
- } else { /* SI */
- switch (micro_tile_mode) {
- case 0: /* displayable */
- switch (image->surface.bpe) {
- case 8:
- image->surface.tiling_index[0] = 10;
- break;
- case 16:
- image->surface.tiling_index[0] = 11;
- break;
- default: /* 32, 64 */
- image->surface.tiling_index[0] = 12;
- break;
- }
- break;
- case 1: /* thin */
- switch (image->surface.bpe) {
- case 8:
- image->surface.tiling_index[0] = 14;
- break;
- case 16:
- image->surface.tiling_index[0] = 15;
- break;
- case 32:
- image->surface.tiling_index[0] = 16;
- break;
- default: /* 64, 128 */
- image->surface.tiling_index[0] = 17;
- break;
- }
- break;
- default: /* depth, thick */
- assert(!"unexpected micro mode");
- return;
- }
- }
-
- image->surface.micro_tile_mode = micro_tile_mode;
+ radv_image_view_make_descriptor(iview, device, pCreateInfo, false);
+ radv_image_view_make_descriptor(iview, device, pCreateInfo, true);
}
bool radv_layout_has_htile(const struct radv_image *image,
- VkImageLayout layout)
+ VkImageLayout layout,
+ unsigned queue_mask)
{
- return (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
- layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL);
+ return image->surface.htile_size &&
+ (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
+ layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL) &&
+ queue_mask == (1u << RADV_QUEUE_GENERAL);
}
bool radv_layout_is_htile_compressed(const struct radv_image *image,
- VkImageLayout layout)
+ VkImageLayout layout,
+ unsigned queue_mask)
{
- return layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL;
+ return image->surface.htile_size &&
+ (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
+ layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL) &&
+ queue_mask == (1u << RADV_QUEUE_GENERAL);
}
-bool radv_layout_can_expclear(const struct radv_image *image,
- VkImageLayout layout)
+bool radv_layout_can_fast_clear(const struct radv_image *image,
+ VkImageLayout layout,
+ unsigned queue_mask)
{
- return (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
- layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL);
+ return layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL &&
+ queue_mask == (1u << RADV_QUEUE_GENERAL);
}
-bool radv_layout_has_cmask(const struct radv_image *image,
- VkImageLayout layout)
+
+unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family)
{
- return (layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL ||
- layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL);
+ if (!image->exclusive)
+ return image->queue_family_mask;
+ if (family == VK_QUEUE_FAMILY_EXTERNAL_KHR)
+ return (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
+ if (family == VK_QUEUE_FAMILY_IGNORED)
+ return 1u << queue_family;
+ return 1u << family;
}
VkResult
const VkAllocationCallbacks *pAllocator)
{
RADV_FROM_HANDLE(radv_device, device, _device);
+ RADV_FROM_HANDLE(radv_image, image, _image);
- if (!_image)
+ if (!image)
return;
- vk_free2(&device->alloc, pAllocator, radv_image_from_handle(_image));
+ if (image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT)
+ device->ws->buffer_destroy(image->bo);
+
+ vk_free2(&device->alloc, pAllocator, image);
}
void radv_GetImageSubresourceLayout(
RADV_FROM_HANDLE(radv_image, image, _image);
int level = pSubresource->mipLevel;
int layer = pSubresource->arrayLayer;
+ struct radeon_surf *surface = &image->surface;
- pLayout->offset = image->surface.level[level].offset + image->surface.level[level].slice_size * layer;
- pLayout->rowPitch = image->surface.level[level].pitch_bytes;
- pLayout->arrayPitch = image->surface.level[level].slice_size;
- pLayout->depthPitch = image->surface.level[level].slice_size;
- pLayout->size = image->surface.level[level].slice_size;
+ pLayout->offset = surface->u.legacy.level[level].offset + surface->u.legacy.level[level].slice_size * layer;
+ pLayout->rowPitch = surface->u.legacy.level[level].nblk_x * surface->bpe;
+ pLayout->arrayPitch = surface->u.legacy.level[level].slice_size;
+ pLayout->depthPitch = surface->u.legacy.level[level].slice_size;
+ pLayout->size = surface->u.legacy.level[level].slice_size;
if (image->type == VK_IMAGE_TYPE_3D)
- pLayout->size *= image->surface.level[level].nblk_z;
+ pLayout->size *= u_minify(image->info.depth, level);
}
if (view == NULL)
return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
- radv_image_view_init(view, device, pCreateInfo, NULL, ~0);
+ radv_image_view_init(view, device, pCreateInfo);
*pView = radv_image_view_to_handle(view);
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