radv: fix buffer views on SI/CIK.

[mesa.git] / src / amd / vulkan / radv_image.c

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 9e54b95ac3f77a065eb7fe3bb52331e47b3b3892..ce1ee24036ea4f50c954d1bb7acb4882e0efcbc6 100644 (file)
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -109,6 +109,7 @@ radv_init_surface(struct radv_device *device,
                surface->flags |= RADEON_SURF_SBUFFER;
 
        surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
+       surface->flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
 
        if ((pCreateInfo->usage & (VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
                                   VK_IMAGE_USAGE_STORAGE_BIT)) ||
@@ -180,6 +181,11 @@ radv_make_buffer_descriptor(struct radv_device *device,
        state[0] = va;
        state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
                S_008F04_STRIDE(stride);
+
+       if (device->physical_device->rad_info.chip_class < VI && stride) {
+               range /= stride;
+       }
+
        state[2] = range;
        state[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc->swizzle[0])) |
                   S_008F0C_DST_SEL_Y(radv_map_swizzle(desc->swizzle[1])) |
@@ -197,7 +203,7 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
                               unsigned block_width, bool is_stencil,
                               uint32_t *state)
 {
-       uint64_t gpu_address = device->ws->buffer_get_va(image->bo) + image->offset;
+       uint64_t gpu_address = image->bo ? device->ws->buffer_get_va(image->bo) + image->offset : 0;
        uint64_t va = gpu_address;
        unsigned pitch = base_level_info->nblk_x * block_width;
        enum chip_class chip_class = device->physical_device->rad_info.chip_class;
@@ -223,7 +229,7 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
                state[6] &= C_008F28_COMPRESSION_EN;
                state[7] = 0;
                if (image->surface.dcc_size && first_level < image->surface.num_dcc_levels) {
-                       uint64_t meta_va = gpu_address + image->dcc_offset;
+                       meta_va = gpu_address + image->dcc_offset;
                        if (chip_class <= VI)
                                meta_va += base_level_info->dcc_offset;
                        state[6] |= S_008F28_COMPRESSION_EN(1);
@@ -944,10 +950,7 @@ radv_image_view_init(struct radv_image_view *iview,
        iview->base_mip = range->baseMipLevel;
 
        radv_image_view_make_descriptor(iview, device, pCreateInfo, false);
-
-       /* For transfers we may use the image as a storage image. */
-       if (image->usage & (VK_IMAGE_USAGE_STORAGE_BIT | VK_IMAGE_USAGE_TRANSFER_DST_BIT))
-               radv_image_view_make_descriptor(iview, device, pCreateInfo, true);
+       radv_image_view_make_descriptor(iview, device, pCreateInfo, true);
 }
 
 bool radv_layout_has_htile(const struct radv_image *image,