radv: fix buffer views on SI/CIK.

[mesa.git] / src / amd / vulkan / radv_image.c

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index d8b7e8f421f824b9dbac1d55a2d936314bebcf59..ce1ee24036ea4f50c954d1bb7acb4882e0efcbc6 100644 (file)
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -181,6 +181,11 @@ radv_make_buffer_descriptor(struct radv_device *device,
        state[0] = va;
        state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
                S_008F04_STRIDE(stride);
+
+       if (device->physical_device->rad_info.chip_class < VI && stride) {
+               range /= stride;
+       }
+
        state[2] = range;
        state[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc->swizzle[0])) |
                   S_008F0C_DST_SEL_Y(radv_map_swizzle(desc->swizzle[1])) |
@@ -198,7 +203,7 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
                               unsigned block_width, bool is_stencil,
                               uint32_t *state)
 {
-       uint64_t gpu_address = device->ws->buffer_get_va(image->bo) + image->offset;
+       uint64_t gpu_address = image->bo ? device->ws->buffer_get_va(image->bo) + image->offset : 0;
        uint64_t va = gpu_address;
        unsigned pitch = base_level_info->nblk_x * block_width;
        enum chip_class chip_class = device->physical_device->rad_info.chip_class;