return RADEON_SURF_MODE_2D;
}
+
+static bool
+radv_image_is_tc_compat_htile(struct radv_device *device,
+ const VkImageCreateInfo *pCreateInfo)
+{
+ /* TC-compat HTILE is only available for GFX8+. */
+ if (device->physical_device->rad_info.chip_class < VI)
+ return false;
+
+ if (pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT)
+ return false;
+
+ if (pCreateInfo->flags & (VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT |
+ VK_IMAGE_CREATE_EXTENDED_USAGE_BIT_KHR))
+ return false;
+
+ if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
+ return false;
+
+ if (pCreateInfo->mipLevels > 1)
+ return false;
+
+ /* FIXME: for some reason TC compat with 2/4/8 samples breaks some cts
+ * tests - disable for now */
+ if (pCreateInfo->samples >= 2 &&
+ pCreateInfo->format == VK_FORMAT_D32_SFLOAT_S8_UINT)
+ return false;
+
+ /* GFX9 supports both 32-bit and 16-bit depth surfaces, while GFX8 only
+ * supports 32-bit. Though, it's possible to enable TC-compat for
+ * 16-bit depth surfaces if no Z planes are compressed.
+ */
+ if (pCreateInfo->format != VK_FORMAT_D32_SFLOAT_S8_UINT &&
+ pCreateInfo->format != VK_FORMAT_D32_SFLOAT &&
+ pCreateInfo->format != VK_FORMAT_D16_UNORM)
+ return false;
+
+ return true;
+}
+
static int
radv_init_surface(struct radv_device *device,
struct radeon_surf *surface,
if (is_depth) {
surface->flags |= RADEON_SURF_ZBUFFER;
- if (!(pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) &&
- !(pCreateInfo->flags & (VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT |
- VK_IMAGE_CREATE_EXTENDED_USAGE_BIT_KHR)) &&
- pCreateInfo->tiling != VK_IMAGE_TILING_LINEAR &&
- pCreateInfo->mipLevels <= 1 &&
- device->physical_device->rad_info.chip_class >= VI &&
- ((pCreateInfo->format == VK_FORMAT_D32_SFLOAT ||
- pCreateInfo->format == VK_FORMAT_D32_SFLOAT_S8_UINT) ||
- (device->physical_device->rad_info.chip_class >= GFX9 &&
- pCreateInfo->format == VK_FORMAT_D16_UNORM)))
+ if (radv_image_is_tc_compat_htile(device, pCreateInfo))
surface->flags |= RADEON_SURF_TC_COMPATIBLE_HTILE;
}
surface->flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
- bool dcc_compatible_formats = !radv_is_colorbuffer_format_supported(pCreateInfo->format, &blendable);
+ bool dcc_compatible_formats = radv_is_colorbuffer_format_supported(pCreateInfo->format, &blendable);
if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
const struct VkImageFormatListCreateInfoKHR *format_list =
(const struct VkImageFormatListCreateInfoKHR *)
}
}
- if ((pCreateInfo->usage & (VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
- VK_IMAGE_USAGE_STORAGE_BIT)) ||
+ if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
(pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT_KHR) ||
!dcc_compatible_formats ||
(pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) ||
const struct legacy_surf_level *base_level_info,
unsigned base_level, unsigned first_level,
unsigned block_width, bool is_stencil,
- uint32_t *state)
+ bool is_storage_image, uint32_t *state)
{
uint64_t gpu_address = image->bo ? radv_buffer_get_va(image->bo) + image->offset : 0;
uint64_t va = gpu_address;
if (chip_class >= VI) {
state[6] &= C_008F28_COMPRESSION_EN;
state[7] = 0;
- if (radv_vi_dcc_enabled(image, first_level)) {
+ if (!is_storage_image && radv_vi_dcc_enabled(image, first_level)) {
meta_va = gpu_address + image->dcc_offset;
if (chip_class <= VI)
meta_va += base_level_info->dcc_offset;
- } else if(image->tc_compatible_htile && image->surface.htile_size) {
+ } else if(!is_storage_image && image->tc_compatible_htile &&
+ image->surface.htile_size) {
meta_va = gpu_address + image->htile_offset;
}
}
}
-static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
+static unsigned gfx9_border_color_swizzle(const enum vk_swizzle swizzle[4])
{
unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
data_format = 0;
}
+ /* S8 with either Z16 or Z32 HTILE need a special format. */
+ if (device->physical_device->rad_info.chip_class >= GFX9 &&
+ vk_format == VK_FORMAT_S8_UINT &&
+ image->tc_compatible_htile) {
+ if (image->vk_format == VK_FORMAT_D32_SFLOAT_S8_UINT)
+ data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
+ else if (image->vk_format == VK_FORMAT_D16_UNORM_S8_UINT)
+ data_format = V_008F14_IMG_DATA_FORMAT_S8_16;
+ }
type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
is_storage_image, device->physical_device->rad_info.chip_class >= GFX9);
if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
state[7] = 0;
if (device->physical_device->rad_info.chip_class >= GFX9) {
- unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
+ unsigned bc_swizzle = gfx9_border_color_swizzle(swizzle);
/* Depth is the the last accessible layer on Gfx9.
* The hw doesn't need to know the total number of layers.
desc, NULL);
si_set_mutable_tex_desc_fields(device, image, &image->surface.u.legacy.level[0], 0, 0,
- image->surface.blk_w, false, desc);
+ image->surface.blk_w, false, false, desc);
/* Clear the base address and set the relative DCC offset. */
desc[0] = 0;
radv_image_can_enable_dcc_or_cmask(struct radv_image *image)
{
if (image->info.samples <= 1 &&
- image->info.width <= 512 && image->info.height <= 512) {
+ image->info.width * image->info.height <= 512 * 512) {
/* Do not enable CMASK or DCC for small surfaces where the cost
* of the eliminate pass can be higher than the benefit of fast
* clear. RadeonSI does this, but the image threshold is
image->size = image->surface.surf_size;
image->alignment = image->surface.surf_alignment;
- /* Try to enable DCC first. */
- if (radv_image_can_enable_dcc(image)) {
- radv_image_alloc_dcc(image);
- } else {
- /* When DCC cannot be enabled, try CMASK. */
- image->surface.dcc_size = 0;
- if (radv_image_can_enable_cmask(image)) {
- radv_image_alloc_cmask(device, image);
+ if (!create_info->no_metadata_planes) {
+ /* Try to enable DCC first. */
+ if (radv_image_can_enable_dcc(image)) {
+ radv_image_alloc_dcc(image);
+ } else {
+ /* When DCC cannot be enabled, try CMASK. */
+ image->surface.dcc_size = 0;
+ if (radv_image_can_enable_cmask(image)) {
+ radv_image_alloc_cmask(device, image);
+ }
}
- }
- /* Try to enable FMASK for multisampled images. */
- if (radv_image_can_enable_fmask(image)) {
- radv_image_alloc_fmask(device, image);
- } else {
- /* Otherwise, try to enable HTILE for depth surfaces. */
- if (radv_image_can_enable_htile(image) &&
- !(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) {
- radv_image_alloc_htile(image);
- image->tc_compatible_htile = image->surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
+ /* Try to enable FMASK for multisampled images. */
+ if (radv_image_can_enable_fmask(image)) {
+ radv_image_alloc_fmask(device, image);
} else {
- image->surface.htile_size = 0;
+ /* Otherwise, try to enable HTILE for depth surfaces. */
+ if (radv_image_can_enable_htile(image) &&
+ !(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) {
+ radv_image_alloc_htile(image);
+ image->tc_compatible_htile = image->surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
+ } else {
+ image->surface.htile_size = 0;
+ }
}
+ } else {
+ image->surface.dcc_size = 0;
+ image->surface.htile_size = 0;
}
if (pCreateInfo->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) {
base_level_info,
iview->base_mip,
iview->base_mip,
- blk_w, is_stencil, descriptor);
+ blk_w, is_stencil, is_storage_image, descriptor);
}
void
}
if (iview->vk_format != image->vk_format) {
- iview->extent.width = round_up_u32(iview->extent.width * vk_format_get_blockwidth(iview->vk_format),
- vk_format_get_blockwidth(image->vk_format));
- iview->extent.height = round_up_u32(iview->extent.height * vk_format_get_blockheight(iview->vk_format),
- vk_format_get_blockheight(image->vk_format));
+ unsigned view_bw = vk_format_get_blockwidth(iview->vk_format);
+ unsigned view_bh = vk_format_get_blockheight(iview->vk_format);
+ unsigned img_bw = vk_format_get_blockwidth(image->vk_format);
+ unsigned img_bh = vk_format_get_blockheight(image->vk_format);
+
+ iview->extent.width = round_up_u32(iview->extent.width * view_bw, img_bw);
+ iview->extent.height = round_up_u32(iview->extent.height * view_bh, img_bh);
+
+ /* Comment ported from amdvlk -
+ * If we have the following image:
+ * Uncompressed pixels Compressed block sizes (4x4)
+ * mip0: 22 x 22 6 x 6
+ * mip1: 11 x 11 3 x 3
+ * mip2: 5 x 5 2 x 2
+ * mip3: 2 x 2 1 x 1
+ * mip4: 1 x 1 1 x 1
+ *
+ * On GFX9 the descriptor is always programmed with the WIDTH and HEIGHT of the base level and the HW is
+ * calculating the degradation of the block sizes down the mip-chain as follows (straight-up
+ * divide-by-two integer math):
+ * mip0: 6x6
+ * mip1: 3x3
+ * mip2: 1x1
+ * mip3: 1x1
+ *
+ * This means that mip2 will be missing texels.
+ *
+ * Fix this by calculating the base mip's width and height, then convert that, and round it
+ * back up to get the level 0 size.
+ * Clamp the converted size between the original values, and next power of two, which
+ * means we don't oversize the image.
+ */
+ if (device->physical_device->rad_info.chip_class >= GFX9 &&
+ vk_format_is_compressed(image->vk_format) &&
+ !vk_format_is_compressed(iview->vk_format)) {
+ unsigned rounded_img_w = util_next_power_of_two(iview->extent.width);
+ unsigned rounded_img_h = util_next_power_of_two(iview->extent.height);
+ unsigned lvl_width = radv_minify(image->info.width , range->baseMipLevel);
+ unsigned lvl_height = radv_minify(image->info.height, range->baseMipLevel);
+
+ lvl_width = round_up_u32(lvl_width * view_bw, img_bw);
+ lvl_height = round_up_u32(lvl_height * view_bh, img_bh);
+
+ lvl_width <<= range->baseMipLevel;
+ lvl_height <<= range->baseMipLevel;
+
+ iview->extent.width = CLAMP(lvl_width, iview->extent.width, rounded_img_w);
+ iview->extent.height = CLAMP(lvl_height, iview->extent.height, rounded_img_h);
+ }
}
iview->base_layer = range->baseArrayLayer;
queue_mask == (1u << RADV_QUEUE_GENERAL);
}
+bool radv_layout_dcc_compressed(const struct radv_image *image,
+ VkImageLayout layout,
+ unsigned queue_mask)
+{
+ /* Don't compress compute transfer dst, as image stores are not supported. */
+ if (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
+ (queue_mask & (1u << RADV_QUEUE_COMPUTE)))
+ return false;
+
+ return image->surface.num_dcc_levels > 0 && layout != VK_IMAGE_LAYOUT_GENERAL;
+}
+
unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family)
{
const VkAllocationCallbacks *pAllocator,
VkImage *pImage)
{
+#ifdef ANDROID
+ const VkNativeBufferANDROID *gralloc_info =
+ vk_find_struct_const(pCreateInfo->pNext, NATIVE_BUFFER_ANDROID);
+
+ if (gralloc_info)
+ return radv_image_from_gralloc(device, pCreateInfo, gralloc_info,
+ pAllocator, pImage);
+#endif
+
const struct wsi_image_create_info *wsi_info =
vk_find_struct_const(pCreateInfo->pNext, WSI_IMAGE_CREATE_INFO_MESA);
bool scanout = wsi_info && wsi_info->scanout;
if (image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT)
device->ws->buffer_destroy(image->bo);
+ if (image->owned_memory != VK_NULL_HANDLE)
+ radv_FreeMemory(_device, image->owned_memory, pAllocator);
+
vk_free2(&device->alloc, pAllocator, image);
}
projects / mesa.git / blobdiff