radv: wrap cs_add_buffer in an inline. (v2)

[mesa.git] / src / amd / vulkan / radv_meta_buffer.c

diff --git a/src/amd/vulkan/radv_meta_buffer.c b/src/amd/vulkan/radv_meta_buffer.c
index f7ffcbbc90bb0493bfd9e8c8ce8b78c2b93450fd..41cdc76b95b8f8fe2ad5ac00f829ffb339ab61bd 100644 (file)
--- a/src/amd/vulkan/radv_meta_buffer.c
+++ b/src/amd/vulkan/radv_meta_buffer.c
@@ -421,7 +421,7 @@ uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
        } else if (size) {
                uint64_t va = radv_buffer_get_va(bo);
                va += offset;
-               cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
+               radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, bo, 8);
                si_cp_dma_clear_buffer(cmd_buffer, va, size, value);
        }
 
@@ -444,8 +444,8 @@ void radv_copy_buffer(struct radv_cmd_buffer *cmd_buffer,
                src_va += src_offset;
                dst_va += dst_offset;
 
-               cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, src_bo, 8);
-               cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, dst_bo, 8);
+               radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, src_bo, 8);
+               radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, dst_bo, 8);
 
                si_cp_dma_buffer_copy(cmd_buffer, src_va, dst_va, size);
        }
@@ -512,7 +512,7 @@ void radv_CmdUpdateBuffer(
        if (dataSize < RADV_BUFFER_OPS_CS_THRESHOLD) {
                si_emit_cache_flush(cmd_buffer);
 
-               cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, dst_buffer->bo, 8);
+               radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, dst_buffer->bo, 8);
 
                radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, words + 4);