radv: Update CTS version.

[mesa.git] / src / amd / vulkan / radv_meta_bufimage.c

diff --git a/src/amd/vulkan/radv_meta_bufimage.c b/src/amd/vulkan/radv_meta_bufimage.c
index 89bb8535b098e2f0e6fa096ef8b2bcb921a00c4f..913d14de4a13e6ac9a880b7e9cd9d247bdd9a05f 100644 (file)
--- a/src/amd/vulkan/radv_meta_bufimage.c
+++ b/src/amd/vulkan/radv_meta_bufimage.c
@@ -41,10 +41,9 @@ build_nir_itob_compute_shader(struct radv_device *dev, bool is_3d)
                                                                 false,
                                                                 false,
                                                                 GLSL_TYPE_FLOAT);
-       const struct glsl_type *img_type = glsl_sampler_type(GLSL_SAMPLER_DIM_BUF,
-                                                            false,
-                                                            false,
-                                                            GLSL_TYPE_FLOAT);
+       const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_BUF,
+                                                          false,
+                                                          GLSL_TYPE_FLOAT);
        nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL);
        b.shader->info.name = ralloc_strdup(b.shader, is_3d ? "meta_itob_cs_3d" : "meta_itob_cs");
        b.shader->info.cs.local_size[0] = 16;
@@ -61,7 +60,7 @@ build_nir_itob_compute_shader(struct radv_device *dev, bool is_3d)
        output_img->data.binding = 1;
 
        nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b);
-       nir_ssa_def *wg_id = nir_load_work_group_id(&b);
+       nir_ssa_def *wg_id = nir_load_work_group_id(&b, 32);
        nir_ssa_def *block_size = nir_imm_ivec4(&b,
                                                b.shader->info.cs.local_size[0],
                                                b.shader->info.cs.local_size[1],
@@ -121,6 +120,7 @@ build_nir_itob_compute_shader(struct radv_device *dev, bool is_3d)
        store->src[1] = nir_src_for_ssa(coord);
        store->src[2] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32));
        store->src[3] = nir_src_for_ssa(outval);
+       store->src[4] = nir_src_for_ssa(nir_imm_int(&b, 0));
 
        nir_builder_instr_insert(&b, &store->instr);
        return b.shader;
@@ -135,7 +135,7 @@ radv_device_init_meta_itob_state(struct radv_device *device)
        struct radv_shader_module cs_3d = { .nir = NULL };
 
        cs.nir = build_nir_itob_compute_shader(device, false);
-       if (device->physical_device->rad_info.chip_class == GFX9)
+       if (device->physical_device->rad_info.chip_class >= GFX9)
                cs_3d.nir = build_nir_itob_compute_shader(device, true);
 
        /*
@@ -211,7 +211,7 @@ radv_device_init_meta_itob_state(struct radv_device *device)
        if (result != VK_SUCCESS)
                goto fail;
 
-       if (device->physical_device->rad_info.chip_class == GFX9) {
+       if (device->physical_device->rad_info.chip_class >= GFX9) {
                VkPipelineShaderStageCreateInfo pipeline_shader_stage_3d = {
                        .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
                        .stage = VK_SHADER_STAGE_COMPUTE_BIT,
@@ -256,7 +256,7 @@ radv_device_finish_meta_itob_state(struct radv_device *device)
                                        &state->alloc);
        radv_DestroyPipeline(radv_device_to_handle(device),
                             state->itob.pipeline, &state->alloc);
-       if (device->physical_device->rad_info.chip_class == GFX9)
+       if (device->physical_device->rad_info.chip_class >= GFX9)
                radv_DestroyPipeline(radv_device_to_handle(device),
                                     state->itob.pipeline_3d, &state->alloc);
 }
@@ -270,10 +270,9 @@ build_nir_btoi_compute_shader(struct radv_device *dev, bool is_3d)
                                                             false,
                                                             false,
                                                             GLSL_TYPE_FLOAT);
-       const struct glsl_type *img_type = glsl_sampler_type(dim,
-                                                            false,
-                                                            false,
-                                                            GLSL_TYPE_FLOAT);
+       const struct glsl_type *img_type = glsl_image_type(dim,
+                                                          false,
+                                                          GLSL_TYPE_FLOAT);
        nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL);
        b.shader->info.name = ralloc_strdup(b.shader, is_3d ? "meta_btoi_cs_3d" : "meta_btoi_cs");
        b.shader->info.cs.local_size[0] = 16;
@@ -290,7 +289,7 @@ build_nir_btoi_compute_shader(struct radv_device *dev, bool is_3d)
        output_img->data.binding = 1;
 
        nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b);
-       nir_ssa_def *wg_id = nir_load_work_group_id(&b);
+       nir_ssa_def *wg_id = nir_load_work_group_id(&b, 32);
        nir_ssa_def *block_size = nir_imm_ivec4(&b,
                                                b.shader->info.cs.local_size[0],
                                                b.shader->info.cs.local_size[1],
@@ -348,6 +347,7 @@ build_nir_btoi_compute_shader(struct radv_device *dev, bool is_3d)
        store->src[1] = nir_src_for_ssa(img_coord);
        store->src[2] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32));
        store->src[3] = nir_src_for_ssa(outval);
+       store->src[4] = nir_src_for_ssa(nir_imm_int(&b, 0));
 
        nir_builder_instr_insert(&b, &store->instr);
        return b.shader;
@@ -361,7 +361,7 @@ radv_device_init_meta_btoi_state(struct radv_device *device)
        struct radv_shader_module cs = { .nir = NULL };
        struct radv_shader_module cs_3d = { .nir = NULL };
        cs.nir = build_nir_btoi_compute_shader(device, false);
-       if (device->physical_device->rad_info.chip_class == GFX9)
+       if (device->physical_device->rad_info.chip_class >= GFX9)
                cs_3d.nir = build_nir_btoi_compute_shader(device, true);
        /*
         * two descriptors one for the image being sampled
@@ -436,7 +436,7 @@ radv_device_init_meta_btoi_state(struct radv_device *device)
        if (result != VK_SUCCESS)
                goto fail;
 
-       if (device->physical_device->rad_info.chip_class == GFX9) {
+       if (device->physical_device->rad_info.chip_class >= GFX9) {
                VkPipelineShaderStageCreateInfo pipeline_shader_stage_3d = {
                        .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
                        .stage = VK_SHADER_STAGE_COMPUTE_BIT,
@@ -492,10 +492,9 @@ build_nir_btoi_r32g32b32_compute_shader(struct radv_device *dev)
                                                             false,
                                                             false,
                                                             GLSL_TYPE_FLOAT);
-       const struct glsl_type *img_type = glsl_sampler_type(GLSL_SAMPLER_DIM_BUF,
-                                                            false,
-                                                            false,
-                                                            GLSL_TYPE_FLOAT);
+       const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_BUF,
+                                                          false,
+                                                          GLSL_TYPE_FLOAT);
        nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL);
        b.shader->info.name = ralloc_strdup(b.shader, "meta_btoi_r32g32b32_cs");
        b.shader->info.cs.local_size[0] = 16;
@@ -512,7 +511,7 @@ build_nir_btoi_r32g32b32_compute_shader(struct radv_device *dev)
        output_img->data.binding = 1;
 
        nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b);
-       nir_ssa_def *wg_id = nir_load_work_group_id(&b);
+       nir_ssa_def *wg_id = nir_load_work_group_id(&b, 32);
        nir_ssa_def *block_size = nir_imm_ivec4(&b,
                                                b.shader->info.cs.local_size[0],
                                                b.shader->info.cs.local_size[1],
@@ -591,6 +590,7 @@ build_nir_btoi_r32g32b32_compute_shader(struct radv_device *dev)
                store->src[1] = nir_src_for_ssa(coord);
                store->src[2] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32));
                store->src[3] = nir_src_for_ssa(nir_channel(&b, outval, chan));
+               store->src[4] = nir_src_for_ssa(nir_imm_int(&b, 0));
                nir_builder_instr_insert(&b, &store->instr);
        }
 
@@ -700,10 +700,9 @@ build_nir_itoi_compute_shader(struct radv_device *dev, bool is_3d)
                                                             false,
                                                             false,
                                                             GLSL_TYPE_FLOAT);
-       const struct glsl_type *img_type = glsl_sampler_type(dim,
-                                                            false,
-                                                            false,
-                                                            GLSL_TYPE_FLOAT);
+       const struct glsl_type *img_type = glsl_image_type(dim,
+                                                          false,
+                                                          GLSL_TYPE_FLOAT);
        nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL);
        b.shader->info.name = ralloc_strdup(b.shader, is_3d ? "meta_itoi_cs_3d" : "meta_itoi_cs");
        b.shader->info.cs.local_size[0] = 16;
@@ -720,7 +719,7 @@ build_nir_itoi_compute_shader(struct radv_device *dev, bool is_3d)
        output_img->data.binding = 1;
 
        nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b);
-       nir_ssa_def *wg_id = nir_load_work_group_id(&b);
+       nir_ssa_def *wg_id = nir_load_work_group_id(&b, 32);
        nir_ssa_def *block_size = nir_imm_ivec4(&b,
                                                b.shader->info.cs.local_size[0],
                                                b.shader->info.cs.local_size[1],
@@ -772,6 +771,7 @@ build_nir_itoi_compute_shader(struct radv_device *dev, bool is_3d)
        store->src[1] = nir_src_for_ssa(dst_coord);
        store->src[2] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32));
        store->src[3] = nir_src_for_ssa(outval);
+       store->src[4] = nir_src_for_ssa(nir_imm_int(&b, 0));
 
        nir_builder_instr_insert(&b, &store->instr);
        return b.shader;
@@ -785,7 +785,7 @@ radv_device_init_meta_itoi_state(struct radv_device *device)
        struct radv_shader_module cs = { .nir = NULL };
        struct radv_shader_module cs_3d = { .nir = NULL };
        cs.nir = build_nir_itoi_compute_shader(device, false);
-       if (device->physical_device->rad_info.chip_class == GFX9)
+       if (device->physical_device->rad_info.chip_class >= GFX9)
                cs_3d.nir = build_nir_itoi_compute_shader(device, true);
        /*
         * two descriptors one for the image being sampled
@@ -860,7 +860,7 @@ radv_device_init_meta_itoi_state(struct radv_device *device)
        if (result != VK_SUCCESS)
                goto fail;
 
-       if (device->physical_device->rad_info.chip_class == GFX9) {
+       if (device->physical_device->rad_info.chip_class >= GFX9) {
                VkPipelineShaderStageCreateInfo pipeline_shader_stage_3d = {
                        .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
 .stage = VK_SHADER_STAGE_COMPUTE_BIT,
@@ -904,7 +904,7 @@ radv_device_finish_meta_itoi_state(struct radv_device *device)
                                        &state->alloc);
        radv_DestroyPipeline(radv_device_to_handle(device),
                             state->itoi.pipeline, &state->alloc);
-       if (device->physical_device->rad_info.chip_class == GFX9)
+       if (device->physical_device->rad_info.chip_class >= GFX9)
                radv_DestroyPipeline(radv_device_to_handle(device),
                                     state->itoi.pipeline_3d, &state->alloc);
 }
@@ -917,6 +917,9 @@ build_nir_itoi_r32g32b32_compute_shader(struct radv_device *dev)
                                                         false,
                                                         false,
                                                         GLSL_TYPE_FLOAT);
+       const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_BUF,
+                                                          false,
+                                                          GLSL_TYPE_FLOAT);
        nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL);
        b.shader->info.name = ralloc_strdup(b.shader, "meta_itoi_r32g32b32_cs");
        b.shader->info.cs.local_size[0] = 16;
@@ -928,12 +931,12 @@ build_nir_itoi_r32g32b32_compute_shader(struct radv_device *dev)
        input_img->data.binding = 0;
 
        nir_variable *output_img = nir_variable_create(b.shader, nir_var_uniform,
-                                                     type, "output_img");
+                                                     img_type, "output_img");
        output_img->data.descriptor_set = 0;
        output_img->data.binding = 1;
 
        nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b);
-       nir_ssa_def *wg_id = nir_load_work_group_id(&b);
+       nir_ssa_def *wg_id = nir_load_work_group_id(&b, 32);
        nir_ssa_def *block_size = nir_imm_ivec4(&b,
                                                b.shader->info.cs.local_size[0],
                                                b.shader->info.cs.local_size[1],
@@ -1018,6 +1021,7 @@ build_nir_itoi_r32g32b32_compute_shader(struct radv_device *dev)
                store->src[1] = nir_src_for_ssa(dst_coord);
                store->src[2] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32));
                store->src[3] = nir_src_for_ssa(nir_channel(&b, outval, 0));
+               store->src[4] = nir_src_for_ssa(nir_imm_int(&b, 0));
                nir_builder_instr_insert(&b, &store->instr);
        }
 
@@ -1124,10 +1128,9 @@ build_nir_cleari_compute_shader(struct radv_device *dev, bool is_3d)
 {
        nir_builder b;
        enum glsl_sampler_dim dim = is_3d ? GLSL_SAMPLER_DIM_3D : GLSL_SAMPLER_DIM_2D;
-       const struct glsl_type *img_type = glsl_sampler_type(dim,
-                                                            false,
-                                                            false,
-                                                            GLSL_TYPE_FLOAT);
+       const struct glsl_type *img_type = glsl_image_type(dim,
+                                                          false,
+                                                          GLSL_TYPE_FLOAT);
        nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL);
        b.shader->info.name = ralloc_strdup(b.shader, is_3d ? "meta_cleari_cs_3d" : "meta_cleari_cs");
        b.shader->info.cs.local_size[0] = 16;
@@ -1140,7 +1143,7 @@ build_nir_cleari_compute_shader(struct radv_device *dev, bool is_3d)
        output_img->data.binding = 0;
 
        nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b);
-       nir_ssa_def *wg_id = nir_load_work_group_id(&b);
+       nir_ssa_def *wg_id = nir_load_work_group_id(&b, 32);
        nir_ssa_def *block_size = nir_imm_ivec4(&b,
                                                b.shader->info.cs.local_size[0],
                                                b.shader->info.cs.local_size[1],
@@ -1179,6 +1182,7 @@ build_nir_cleari_compute_shader(struct radv_device *dev, bool is_3d)
        store->src[1] = nir_src_for_ssa(global_id);
        store->src[2] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32));
        store->src[3] = nir_src_for_ssa(&clear_val->dest.ssa);
+       store->src[4] = nir_src_for_ssa(nir_imm_int(&b, 0));
 
        nir_builder_instr_insert(&b, &store->instr);
        return b.shader;
@@ -1191,7 +1195,7 @@ radv_device_init_meta_cleari_state(struct radv_device *device)
        struct radv_shader_module cs = { .nir = NULL };
        struct radv_shader_module cs_3d = { .nir = NULL };
        cs.nir = build_nir_cleari_compute_shader(device, false);
-       if (device->physical_device->rad_info.chip_class == GFX9)
+       if (device->physical_device->rad_info.chip_class >= GFX9)
                cs_3d.nir = build_nir_cleari_compute_shader(device, true);
 
        /*
@@ -1261,7 +1265,7 @@ radv_device_init_meta_cleari_state(struct radv_device *device)
                goto fail;
 
 
-       if (device->physical_device->rad_info.chip_class == GFX9) {
+       if (device->physical_device->rad_info.chip_class >= GFX9) {
                /* compute shader */
                VkPipelineShaderStageCreateInfo pipeline_shader_stage_3d = {
                        .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
@@ -1316,10 +1320,9 @@ static nir_shader *
 build_nir_cleari_r32g32b32_compute_shader(struct radv_device *dev)
 {
        nir_builder b;
-       const struct glsl_type *img_type = glsl_sampler_type(GLSL_SAMPLER_DIM_BUF,
-                                                            false,
-                                                            false,
-                                                            GLSL_TYPE_FLOAT);
+       const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_BUF,
+                                                          false,
+                                                          GLSL_TYPE_FLOAT);
        nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL);
        b.shader->info.name = ralloc_strdup(b.shader, "meta_cleari_r32g32b32_cs");
        b.shader->info.cs.local_size[0] = 16;
@@ -1332,7 +1335,7 @@ build_nir_cleari_r32g32b32_compute_shader(struct radv_device *dev)
        output_img->data.binding = 0;
 
        nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b);
-       nir_ssa_def *wg_id = nir_load_work_group_id(&b);
+       nir_ssa_def *wg_id = nir_load_work_group_id(&b, 32);
        nir_ssa_def *block_size = nir_imm_ivec4(&b,
                                                b.shader->info.cs.local_size[0],
                                                b.shader->info.cs.local_size[1],
@@ -1377,6 +1380,7 @@ build_nir_cleari_r32g32b32_compute_shader(struct radv_device *dev)
                store->src[1] = nir_src_for_ssa(coord);
                store->src[2] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32));
                store->src[3] = nir_src_for_ssa(nir_channel(&b, &clear_val->dest.ssa, chan));
+               store->src[4] = nir_src_for_ssa(nir_imm_int(&b, 0));
                nir_builder_instr_insert(&b, &store->instr);
        }
 
@@ -1706,7 +1710,7 @@ radv_meta_image_to_buffer(struct radv_cmd_buffer *cmd_buffer,
        create_bview(cmd_buffer, dst->buffer, dst->offset, dst->format, &dst_view);
        itob_bind_descriptors(cmd_buffer, &src_view, &dst_view);
 
-       if (device->physical_device->rad_info.chip_class == GFX9 &&
+       if (device->physical_device->rad_info.chip_class >= GFX9 &&
            src->image->type == VK_IMAGE_TYPE_3D)
                pipeline = cmd_buffer->device->meta_state.itob.pipeline_3d;
 
@@ -1875,7 +1879,7 @@ radv_meta_buffer_to_image_cs(struct radv_cmd_buffer *cmd_buffer,
        create_iview(cmd_buffer, dst, &dst_view);
        btoi_bind_descriptors(cmd_buffer, &src_view, &dst_view);
 
-       if (device->physical_device->rad_info.chip_class == GFX9 &&
+       if (device->physical_device->rad_info.chip_class >= GFX9 &&
            dst->image->type == VK_IMAGE_TYPE_3D)
                pipeline = cmd_buffer->device->meta_state.btoi.pipeline_3d;
        radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
@@ -2060,7 +2064,7 @@ radv_meta_image_to_image_cs(struct radv_cmd_buffer *cmd_buffer,
 
        itoi_bind_descriptors(cmd_buffer, &src_view, &dst_view);
 
-       if (device->physical_device->rad_info.chip_class == GFX9 &&
+       if (device->physical_device->rad_info.chip_class >= GFX9 &&
            (src->image->type == VK_IMAGE_TYPE_3D || dst->image->type == VK_IMAGE_TYPE_3D))
                pipeline = cmd_buffer->device->meta_state.itoi.pipeline_3d;
        radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
@@ -2201,7 +2205,7 @@ radv_meta_clear_image_cs(struct radv_cmd_buffer *cmd_buffer,
        create_iview(cmd_buffer, dst, &dst_iview);
        cleari_bind_descriptors(cmd_buffer, &dst_iview);
 
-       if (device->physical_device->rad_info.chip_class == GFX9 &&
+       if (device->physical_device->rad_info.chip_class >= GFX9 &&
            dst->image->type == VK_IMAGE_TYPE_3D)
                pipeline = cmd_buffer->device->meta_state.cleari.pipeline_3d;