#include "util/format_rgb9e5.h"
#include "vk_format.h"
-/** Vertex attributes for color clears. */
-struct color_clear_vattrs {
- float position[2];
- VkClearColorValue color;
-};
-
-/** Vertex attributes for depthstencil clears. */
-struct depthstencil_clear_vattrs {
- float position[2];
- float depth_clear;
-};
enum {
DEPTH_CLEAR_SLOW,
nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL);
nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
- vs_b.shader->info->name = ralloc_strdup(vs_b.shader, "meta_clear_color_vs");
- fs_b.shader->info->name = ralloc_strdup(fs_b.shader, "meta_clear_color_fs");
+ vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_color_vs");
+ fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_color_fs");
const struct glsl_type *position_type = glsl_vec4_type();
const struct glsl_type *color_type = glsl_vec4_type();
- nir_variable *vs_in_pos =
- nir_variable_create(vs_b.shader, nir_var_shader_in, position_type,
- "a_position");
- vs_in_pos->data.location = VERT_ATTRIB_GENERIC0;
-
nir_variable *vs_out_pos =
nir_variable_create(vs_b.shader, nir_var_shader_out, position_type,
"gl_Position");
vs_out_pos->data.location = VARYING_SLOT_POS;
- nir_variable *vs_in_color =
- nir_variable_create(vs_b.shader, nir_var_shader_in, color_type,
- "a_color");
- vs_in_color->data.location = VERT_ATTRIB_GENERIC1;
-
- nir_variable *vs_out_color =
- nir_variable_create(vs_b.shader, nir_var_shader_out, color_type,
- "v_color");
- vs_out_color->data.location = VARYING_SLOT_VAR0;
- vs_out_color->data.interpolation = INTERP_MODE_FLAT;
-
- nir_variable *fs_in_color =
- nir_variable_create(fs_b.shader, nir_var_shader_in, color_type,
- "v_color");
- fs_in_color->data.location = vs_out_color->data.location;
- fs_in_color->data.interpolation = vs_out_color->data.interpolation;
+ nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(fs_b.shader, nir_intrinsic_load_push_constant);
+ nir_intrinsic_set_base(in_color_load, 0);
+ nir_intrinsic_set_range(in_color_load, 16);
+ in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&fs_b, 0));
+ in_color_load->num_components = 4;
+ nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 4, 32, "clear color");
+ nir_builder_instr_insert(&fs_b, &in_color_load->instr);
nir_variable *fs_out_color =
nir_variable_create(fs_b.shader, nir_var_shader_out, color_type,
"f_color");
fs_out_color->data.location = FRAG_RESULT_DATA0 + frag_output;
- nir_copy_var(&vs_b, vs_out_pos, vs_in_pos);
- nir_copy_var(&vs_b, vs_out_color, vs_in_color);
- nir_copy_var(&fs_b, fs_out_color, fs_in_color);
+ nir_store_var(&fs_b, fs_out_color, &in_color_load->dest.ssa, 0xf);
+
+ nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&vs_b);
+ nir_store_var(&vs_b, vs_out_pos, outvec, 0xf);
+
+ const struct glsl_type *layer_type = glsl_int_type();
+ nir_variable *vs_out_layer =
+ nir_variable_create(vs_b.shader, nir_var_shader_out, layer_type,
+ "v_layer");
+ vs_out_layer->data.location = VARYING_SLOT_LAYER;
+ vs_out_layer->data.interpolation = INTERP_MODE_FLAT;
+ nir_ssa_def *inst_id = nir_load_system_value(&vs_b, nir_intrinsic_load_instance_id, 0);
+
+ nir_store_var(&vs_b, vs_out_layer, inst_id, 0x1);
*out_vs = vs_b.shader;
*out_fs = fs_b.shader;
const VkPipelineVertexInputStateCreateInfo *vi_state,
const VkPipelineDepthStencilStateCreateInfo *ds_state,
const VkPipelineColorBlendStateCreateInfo *cb_state,
+ const VkPipelineLayout layout,
const struct radv_graphics_pipeline_create_info *extra,
const VkAllocationCallbacks *alloc,
struct radv_pipeline **pipeline)
},
.pViewportState = &(VkPipelineViewportStateCreateInfo) {
.sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
- .viewportCount = 0,
- .scissorCount = 0,
+ .viewportCount = 1,
+ .scissorCount = 1,
},
.pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
.sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
* we need only restore dynamic state was vkCmdSet.
*/
.sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
- .dynamicStateCount = 6,
+ .dynamicStateCount = 8,
.pDynamicStates = (VkDynamicState[]) {
/* Everything except stencil write mask */
+ VK_DYNAMIC_STATE_VIEWPORT,
+ VK_DYNAMIC_STATE_SCISSOR,
VK_DYNAMIC_STATE_LINE_WIDTH,
VK_DYNAMIC_STATE_DEPTH_BIAS,
VK_DYNAMIC_STATE_BLEND_CONSTANTS,
VK_DYNAMIC_STATE_STENCIL_REFERENCE,
},
},
- .flags = 0,
- .renderPass = radv_render_pass_to_handle(render_pass),
- .subpass = 0,
- },
+ .layout = layout,
+ .flags = 0,
+ .renderPass = radv_render_pass_to_handle(render_pass),
+ .subpass = 0,
+ },
extra,
alloc,
&pipeline_h);
return result;
}
+static VkResult
+create_color_renderpass(struct radv_device *device,
+ VkFormat vk_format,
+ uint32_t samples,
+ VkRenderPass *pass)
+{
+ return radv_CreateRenderPass(radv_device_to_handle(device),
+ &(VkRenderPassCreateInfo) {
+ .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
+ .attachmentCount = 1,
+ .pAttachments = &(VkAttachmentDescription) {
+ .format = vk_format,
+ .samples = samples,
+ .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
+ .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
+ .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
+ .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
+ },
+ .subpassCount = 1,
+ .pSubpasses = &(VkSubpassDescription) {
+ .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
+ .inputAttachmentCount = 0,
+ .colorAttachmentCount = 1,
+ .pColorAttachments = &(VkAttachmentReference) {
+ .attachment = 0,
+ .layout = VK_IMAGE_LAYOUT_GENERAL,
+ },
+ .pResolveAttachments = NULL,
+ .pDepthStencilAttachment = &(VkAttachmentReference) {
+ .attachment = VK_ATTACHMENT_UNUSED,
+ .layout = VK_IMAGE_LAYOUT_GENERAL,
+ },
+ .preserveAttachmentCount = 1,
+ .pPreserveAttachments = (uint32_t[]) { 0 },
+ },
+ .dependencyCount = 0,
+ }, &device->meta_state.alloc, pass);
+}
+
static VkResult
create_color_pipeline(struct radv_device *device,
- VkFormat vk_format,
uint32_t samples,
uint32_t frag_output,
struct radv_pipeline **pipeline,
- VkRenderPass *pass)
+ VkRenderPass pass)
{
struct nir_shader *vs_nir;
struct nir_shader *fs_nir;
const VkPipelineVertexInputStateCreateInfo vi_state = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
- .vertexBindingDescriptionCount = 1,
- .pVertexBindingDescriptions = (VkVertexInputBindingDescription[]) {
- {
- .binding = 0,
- .stride = sizeof(struct color_clear_vattrs),
- .inputRate = VK_VERTEX_INPUT_RATE_VERTEX
- },
- },
- .vertexAttributeDescriptionCount = 2,
- .pVertexAttributeDescriptions = (VkVertexInputAttributeDescription[]) {
- {
- /* Position */
- .location = 0,
- .binding = 0,
- .format = VK_FORMAT_R32G32_SFLOAT,
- .offset = offsetof(struct color_clear_vattrs, position),
- },
- {
- /* Color */
- .location = 1,
- .binding = 0,
- .format = VK_FORMAT_R32G32B32A32_SFLOAT,
- .offset = offsetof(struct color_clear_vattrs, color),
- },
- },
+ .vertexBindingDescriptionCount = 0,
+ .vertexAttributeDescriptionCount = 0,
};
const VkPipelineDepthStencilStateCreateInfo ds_state = {
.pAttachments = blend_attachment_state
};
- result = radv_CreateRenderPass(radv_device_to_handle(device),
- &(VkRenderPassCreateInfo) {
- .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
- .attachmentCount = 1,
- .pAttachments = &(VkAttachmentDescription) {
- .format = vk_format,
- .samples = samples,
- .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
- .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
- .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
- .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
- },
- .subpassCount = 1,
- .pSubpasses = &(VkSubpassDescription) {
- .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
- .inputAttachmentCount = 0,
- .colorAttachmentCount = 1,
- .pColorAttachments = &(VkAttachmentReference) {
- .attachment = 0,
- .layout = VK_IMAGE_LAYOUT_GENERAL,
- },
- .pResolveAttachments = NULL,
- .pDepthStencilAttachment = &(VkAttachmentReference) {
- .attachment = VK_ATTACHMENT_UNUSED,
- .layout = VK_IMAGE_LAYOUT_GENERAL,
- },
- .preserveAttachmentCount = 1,
- .pPreserveAttachments = (uint32_t[]) { 0 },
- },
- .dependencyCount = 0,
- }, &device->meta_state.alloc, pass);
- if (result != VK_SUCCESS)
- return result;
struct radv_graphics_pipeline_create_info extra = {
.use_rectlist = true,
};
- result = create_pipeline(device, radv_render_pass_from_handle(*pass),
+ result = create_pipeline(device, radv_render_pass_from_handle(pass),
samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
+ device->meta_state.clear_color_p_layout,
&extra, &device->meta_state.alloc, pipeline);
return result;
for (uint32_t j = 0; j < NUM_DEPTH_CLEAR_PIPELINES; j++) {
destroy_pipeline(device, state->clear[i].depth_only_pipeline[j]);
- destroy_render_pass(device, state->clear[i].depth_only_rp[j]);
destroy_pipeline(device, state->clear[i].stencil_only_pipeline[j]);
- destroy_render_pass(device, state->clear[i].stencil_only_rp[j]);
destroy_pipeline(device, state->clear[i].depthstencil_pipeline[j]);
- destroy_render_pass(device, state->clear[i].depthstencil_rp[j]);
}
+ destroy_render_pass(device, state->clear[i].depthstencil_rp);
}
-
+ radv_DestroyPipelineLayout(radv_device_to_handle(device),
+ state->clear_color_p_layout,
+ &state->alloc);
+ radv_DestroyPipelineLayout(radv_device_to_handle(device),
+ state->clear_depth_p_layout,
+ &state->alloc);
}
static void
const uint32_t subpass_att = clear_att->colorAttachment;
const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
- const uint32_t samples = iview->image->samples;
+ const uint32_t samples = iview->image->info.samples;
const uint32_t samples_log2 = ffs(samples) - 1;
unsigned fs_key = radv_format_meta_fs_key(iview->vk_format);
struct radv_pipeline *pipeline;
VkClearColorValue clear_value = clear_att->clearValue.color;
VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
VkPipeline pipeline_h;
- uint32_t offset;
if (fs_key == -1) {
radv_finishme("color clears incomplete");
assert(clear_att->aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
assert(clear_att->colorAttachment < subpass->color_count);
- const struct color_clear_vattrs vertex_data[3] = {
- {
- .position = {
- clear_rect->rect.offset.x,
- clear_rect->rect.offset.y,
- },
- .color = clear_value,
- },
- {
- .position = {
- clear_rect->rect.offset.x,
- clear_rect->rect.offset.y + clear_rect->rect.extent.height,
- },
- .color = clear_value,
- },
- {
- .position = {
- clear_rect->rect.offset.x + clear_rect->rect.extent.width,
- clear_rect->rect.offset.y,
- },
- .color = clear_value,
- },
- };
+ radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
+ device->meta_state.clear_color_p_layout,
+ VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16,
+ &clear_value);
struct radv_subpass clear_subpass = {
.color_count = 1,
radv_cmd_buffer_set_subpass(cmd_buffer, &clear_subpass, false);
- radv_cmd_buffer_upload_data(cmd_buffer, sizeof(vertex_data), 16, vertex_data, &offset);
- struct radv_buffer vertex_buffer = {
- .device = device,
- .size = sizeof(vertex_data),
- .bo = cmd_buffer->upload.upload_bo,
- .offset = offset,
- };
-
-
- radv_CmdBindVertexBuffers(cmd_buffer_h, 0, 1,
- (VkBuffer[]) { radv_buffer_to_handle(&vertex_buffer) },
- (VkDeviceSize[]) { 0 });
-
if (cmd_buffer->state.pipeline != pipeline) {
radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
pipeline_h);
}
- radv_CmdDraw(cmd_buffer_h, 3, 1, 0, 0);
+ radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
+ .x = clear_rect->rect.offset.x,
+ .y = clear_rect->rect.offset.y,
+ .width = clear_rect->rect.extent.width,
+ .height = clear_rect->rect.extent.height,
+ .minDepth = 0.0f,
+ .maxDepth = 1.0f
+ });
+
+ radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
+
+ radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, 0);
radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
}
nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL);
nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
- vs_b.shader->info->name = ralloc_strdup(vs_b.shader, "meta_clear_depthstencil_vs");
- fs_b.shader->info->name = ralloc_strdup(fs_b.shader, "meta_clear_depthstencil_fs");
- const struct glsl_type *position_type = glsl_vec4_type();
-
- nir_variable *vs_in_pos =
- nir_variable_create(vs_b.shader, nir_var_shader_in, position_type,
- "a_position");
- vs_in_pos->data.location = VERT_ATTRIB_GENERIC0;
+ vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_depthstencil_vs");
+ fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_depthstencil_fs");
+ const struct glsl_type *position_out_type = glsl_vec4_type();
nir_variable *vs_out_pos =
- nir_variable_create(vs_b.shader, nir_var_shader_out, position_type,
+ nir_variable_create(vs_b.shader, nir_var_shader_out, position_out_type,
"gl_Position");
vs_out_pos->data.location = VARYING_SLOT_POS;
- nir_copy_var(&vs_b, vs_out_pos, vs_in_pos);
+ nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(vs_b.shader, nir_intrinsic_load_push_constant);
+ nir_intrinsic_set_base(in_color_load, 0);
+ nir_intrinsic_set_range(in_color_load, 4);
+ in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&vs_b, 0));
+ in_color_load->num_components = 1;
+ nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 1, 32, "depth value");
+ nir_builder_instr_insert(&vs_b, &in_color_load->instr);
+
+ nir_ssa_def *outvec = radv_meta_gen_rect_vertices_comp2(&vs_b, &in_color_load->dest.ssa);
+ nir_store_var(&vs_b, vs_out_pos, outvec, 0xf);
+
+ const struct glsl_type *layer_type = glsl_int_type();
+ nir_variable *vs_out_layer =
+ nir_variable_create(vs_b.shader, nir_var_shader_out, layer_type,
+ "v_layer");
+ vs_out_layer->data.location = VARYING_SLOT_LAYER;
+ vs_out_layer->data.interpolation = INTERP_MODE_FLAT;
+ nir_ssa_def *inst_id = nir_load_system_value(&vs_b, nir_intrinsic_load_instance_id, 0);
+ nir_store_var(&vs_b, vs_out_layer, inst_id, 0x1);
*out_vs = vs_b.shader;
*out_fs = fs_b.shader;
}
+static VkResult
+create_depthstencil_renderpass(struct radv_device *device,
+ uint32_t samples,
+ VkRenderPass *render_pass)
+{
+ return radv_CreateRenderPass(radv_device_to_handle(device),
+ &(VkRenderPassCreateInfo) {
+ .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
+ .attachmentCount = 1,
+ .pAttachments = &(VkAttachmentDescription) {
+ .format = VK_FORMAT_UNDEFINED,
+ .samples = samples,
+ .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
+ .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
+ .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
+ .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
+ },
+ .subpassCount = 1,
+ .pSubpasses = &(VkSubpassDescription) {
+ .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
+ .inputAttachmentCount = 0,
+ .colorAttachmentCount = 0,
+ .pColorAttachments = NULL,
+ .pResolveAttachments = NULL,
+ .pDepthStencilAttachment = &(VkAttachmentReference) {
+ .attachment = 0,
+ .layout = VK_IMAGE_LAYOUT_GENERAL,
+ },
+ .preserveAttachmentCount = 1,
+ .pPreserveAttachments = (uint32_t[]) { 0 },
+ },
+ .dependencyCount = 0,
+ }, &device->meta_state.alloc, render_pass);
+}
+
static VkResult
create_depthstencil_pipeline(struct radv_device *device,
VkImageAspectFlags aspects,
uint32_t samples,
int index,
struct radv_pipeline **pipeline,
- VkRenderPass *render_pass)
+ VkRenderPass render_pass)
{
struct nir_shader *vs_nir, *fs_nir;
VkResult result;
const VkPipelineVertexInputStateCreateInfo vi_state = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
- .vertexBindingDescriptionCount = 1,
- .pVertexBindingDescriptions = (VkVertexInputBindingDescription[]) {
- {
- .binding = 0,
- .stride = sizeof(struct depthstencil_clear_vattrs),
- .inputRate = VK_VERTEX_INPUT_RATE_VERTEX
- },
- },
- .vertexAttributeDescriptionCount = 1,
- .pVertexAttributeDescriptions = (VkVertexInputAttributeDescription[]) {
- {
- /* Position */
- .location = 0,
- .binding = 0,
- .format = VK_FORMAT_R32G32B32_SFLOAT,
- .offset = offsetof(struct depthstencil_clear_vattrs, position),
- },
- },
+ .vertexBindingDescriptionCount = 0,
+ .vertexAttributeDescriptionCount = 0,
};
const VkPipelineDepthStencilStateCreateInfo ds_state = {
.pAttachments = NULL,
};
- result = radv_CreateRenderPass(radv_device_to_handle(device),
- &(VkRenderPassCreateInfo) {
- .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
- .attachmentCount = 1,
- .pAttachments = &(VkAttachmentDescription) {
- .format = VK_FORMAT_UNDEFINED,
- .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
- .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
- .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
- .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
- },
- .subpassCount = 1,
- .pSubpasses = &(VkSubpassDescription) {
- .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
- .inputAttachmentCount = 0,
- .colorAttachmentCount = 0,
- .pColorAttachments = NULL,
- .pResolveAttachments = NULL,
- .pDepthStencilAttachment = &(VkAttachmentReference) {
- .attachment = 0,
- .layout = VK_IMAGE_LAYOUT_GENERAL,
- },
- .preserveAttachmentCount = 1,
- .pPreserveAttachments = (uint32_t[]) { 0 },
- },
- .dependencyCount = 0,
- }, &device->meta_state.alloc, render_pass);
- if (result != VK_SUCCESS)
- return result;
-
struct radv_graphics_pipeline_create_info extra = {
.use_rectlist = true,
};
extra.db_stencil_clear = index == DEPTH_CLEAR_SLOW ? false : true;
extra.db_stencil_disable_expclear = index == DEPTH_CLEAR_FAST_NO_EXPCLEAR ? true : false;
}
- result = create_pipeline(device, radv_render_pass_from_handle(*render_pass),
+ result = create_pipeline(device, radv_render_pass_from_handle(render_pass),
samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
+ device->meta_state.clear_depth_p_layout,
&extra, &device->meta_state.alloc, pipeline);
return result;
}
-static bool depth_view_can_fast_clear(const struct radv_image_view *iview,
+static bool depth_view_can_fast_clear(struct radv_cmd_buffer *cmd_buffer,
+ const struct radv_image_view *iview,
VkImageLayout layout,
const VkClearRect *clear_rect)
{
+ uint32_t queue_mask = radv_image_queue_family_mask(iview->image,
+ cmd_buffer->queue_family_index,
+ cmd_buffer->queue_family_index);
if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
clear_rect->rect.extent.width != iview->extent.width ||
clear_rect->rect.extent.height != iview->extent.height)
return false;
- if (iview->image->htile.size &&
+ if (iview->image->surface.htile_size &&
iview->base_mip == 0 &&
iview->base_layer == 0 &&
- radv_layout_can_expclear(iview->image, layout) &&
- memcmp(&iview->extent, &iview->image->extent, sizeof(iview->extent)) == 0)
+ radv_layout_is_htile_compressed(iview->image, layout, queue_mask) &&
+ !radv_image_extent_compare(iview->image, &iview->extent))
return true;
return false;
}
static struct radv_pipeline *
-pick_depthstencil_pipeline(struct radv_meta_state *meta_state,
+pick_depthstencil_pipeline(struct radv_cmd_buffer *cmd_buffer,
+ struct radv_meta_state *meta_state,
const struct radv_image_view *iview,
int samples_log2,
VkImageAspectFlags aspects,
const VkClearRect *clear_rect,
VkClearDepthStencilValue clear_value)
{
- bool fast = depth_view_can_fast_clear(iview, layout, clear_rect);
+ bool fast = depth_view_can_fast_clear(cmd_buffer, iview, layout, clear_rect);
int index = DEPTH_CLEAR_SLOW;
if (fast) {
VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
VkImageAspectFlags aspects = clear_att->aspectMask;
const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
- const uint32_t samples = iview->image->samples;
+ const uint32_t samples = iview->image->info.samples;
const uint32_t samples_log2 = ffs(samples) - 1;
VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
- uint32_t offset;
assert(aspects == VK_IMAGE_ASPECT_DEPTH_BIT ||
aspects == VK_IMAGE_ASPECT_STENCIL_BIT ||
VK_IMAGE_ASPECT_STENCIL_BIT));
assert(pass_att != VK_ATTACHMENT_UNUSED);
- const struct depthstencil_clear_vattrs vertex_data[3] = {
- {
- .position = {
- clear_rect->rect.offset.x,
- clear_rect->rect.offset.y,
- },
- .depth_clear = clear_value.depth,
- },
- {
- .position = {
- clear_rect->rect.offset.x,
- clear_rect->rect.offset.y + clear_rect->rect.extent.height,
- },
- .depth_clear = clear_value.depth,
- },
- {
- .position = {
- clear_rect->rect.offset.x + clear_rect->rect.extent.width,
- clear_rect->rect.offset.y,
- },
- .depth_clear = clear_value.depth,
- },
- };
+ if (!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
+ clear_value.depth = 1.0f;
- radv_cmd_buffer_upload_data(cmd_buffer, sizeof(vertex_data), 16, vertex_data, &offset);
- struct radv_buffer vertex_buffer = {
- .device = device,
- .size = sizeof(vertex_data),
- .bo = cmd_buffer->upload.upload_bo,
- .offset = offset,
- };
+ radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
+ device->meta_state.clear_depth_p_layout,
+ VK_SHADER_STAGE_VERTEX_BIT, 0, 4,
+ &clear_value.depth);
if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
radv_CmdSetStencilReference(cmd_buffer_h, VK_STENCIL_FACE_FRONT_BIT,
clear_value.stencil);
}
- radv_CmdBindVertexBuffers(cmd_buffer_h, 0, 1,
- (VkBuffer[]) { radv_buffer_to_handle(&vertex_buffer) },
- (VkDeviceSize[]) { 0 });
-
- struct radv_pipeline *pipeline = pick_depthstencil_pipeline(meta_state,
+ struct radv_pipeline *pipeline = pick_depthstencil_pipeline(cmd_buffer,
+ meta_state,
iview,
samples_log2,
aspects,
radv_pipeline_to_handle(pipeline));
}
- if (depth_view_can_fast_clear(iview, subpass->depth_stencil_attachment.layout, clear_rect))
+ if (depth_view_can_fast_clear(cmd_buffer, iview, subpass->depth_stencil_attachment.layout, clear_rect))
radv_set_depth_clear_regs(cmd_buffer, iview->image, clear_value, aspects);
- radv_CmdDraw(cmd_buffer_h, 3, 1, 0, 0);
+ radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
+ .x = clear_rect->rect.offset.x,
+ .y = clear_rect->rect.offset.y,
+ .width = clear_rect->rect.extent.width,
+ .height = clear_rect->rect.extent.height,
+ .minDepth = 0.0f,
+ .maxDepth = 1.0f
+ });
+
+ radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
+
+ radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, 0);
}
+static bool
+emit_fast_htile_clear(struct radv_cmd_buffer *cmd_buffer,
+ const VkClearAttachment *clear_att,
+ const VkClearRect *clear_rect,
+ enum radv_cmd_flush_bits *pre_flush,
+ enum radv_cmd_flush_bits *post_flush)
+{
+ const struct radv_subpass *subpass = cmd_buffer->state.subpass;
+ const uint32_t pass_att = subpass->depth_stencil_attachment.attachment;
+ VkImageLayout image_layout = subpass->depth_stencil_attachment.layout;
+ const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
+ const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
+ VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
+ VkImageAspectFlags aspects = clear_att->aspectMask;
+ uint32_t clear_word;
+
+ if (!iview->image->surface.htile_size)
+ return false;
+
+ if (cmd_buffer->device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
+ return false;
+
+ if (!radv_layout_is_htile_compressed(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
+ goto fail;
+
+ /* don't fast clear 3D */
+ if (iview->image->type == VK_IMAGE_TYPE_3D)
+ goto fail;
+
+ /* all layers are bound */
+ if (iview->base_layer > 0)
+ goto fail;
+ if (iview->image->info.array_size != iview->layer_count)
+ goto fail;
+
+ if (iview->image->info.levels > 1)
+ goto fail;
+
+ if (!radv_image_extent_compare(iview->image, &iview->extent))
+ goto fail;
+
+ if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
+ clear_rect->rect.extent.width != iview->image->info.width ||
+ clear_rect->rect.extent.height != iview->image->info.height)
+ goto fail;
+
+ if (clear_rect->baseArrayLayer != 0)
+ goto fail;
+ if (clear_rect->layerCount != iview->image->info.array_size)
+ goto fail;
+
+ /* Don't do stencil clears till we have figured out if the clear words are
+ * correct. */
+ if (vk_format_aspects(iview->image->vk_format) & VK_IMAGE_ASPECT_STENCIL_BIT)
+ goto fail;
+
+ if (clear_value.depth == 1.0)
+ clear_word = 0xfffffff0;
+ else if (clear_value.depth == 0.0)
+ clear_word = 0;
+ else
+ goto fail;
+
+ if (pre_flush) {
+ cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_DB |
+ RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) & ~ *pre_flush;
+ *pre_flush |= cmd_buffer->state.flush_bits;
+ } else
+ cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
+ RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
+
+ radv_fill_buffer(cmd_buffer, iview->image->bo,
+ iview->image->offset + iview->image->htile_offset,
+ iview->image->surface.htile_size, clear_word);
+
+
+ radv_set_depth_clear_regs(cmd_buffer, iview->image, clear_value, aspects);
+ if (post_flush)
+ *post_flush |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
+ RADV_CMD_FLAG_INV_VMEM_L1 |
+ RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
+ else
+ cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
+ RADV_CMD_FLAG_INV_VMEM_L1 |
+ RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
+ return true;
+fail:
+ return false;
+}
static VkFormat pipeline_formats[] = {
VK_FORMAT_R8G8B8A8_UNORM,
memset(&device->meta_state.clear, 0, sizeof(device->meta_state.clear));
+ VkPipelineLayoutCreateInfo pl_color_create_info = {
+ .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
+ .setLayoutCount = 0,
+ .pushConstantRangeCount = 1,
+ .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16},
+ };
+
+ res = radv_CreatePipelineLayout(radv_device_to_handle(device),
+ &pl_color_create_info,
+ &device->meta_state.alloc,
+ &device->meta_state.clear_color_p_layout);
+ if (res != VK_SUCCESS)
+ goto fail;
+
+ VkPipelineLayoutCreateInfo pl_depth_create_info = {
+ .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
+ .setLayoutCount = 0,
+ .pushConstantRangeCount = 1,
+ .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_VERTEX_BIT, 0, 4},
+ };
+
+ res = radv_CreatePipelineLayout(radv_device_to_handle(device),
+ &pl_depth_create_info,
+ &device->meta_state.alloc,
+ &device->meta_state.clear_depth_p_layout);
+ if (res != VK_SUCCESS)
+ goto fail;
+
for (uint32_t i = 0; i < ARRAY_SIZE(state->clear); ++i) {
uint32_t samples = 1 << i;
for (uint32_t j = 0; j < ARRAY_SIZE(pipeline_formats); ++j) {
VkFormat format = pipeline_formats[j];
unsigned fs_key = radv_format_meta_fs_key(format);
assert(!state->clear[i].color_pipelines[fs_key]);
- res = create_color_pipeline(device, format, samples, 0, &state->clear[i].color_pipelines[fs_key],
- &state->clear[i].render_pass[fs_key]);
+
+ res = create_color_renderpass(device, format, samples,
+ &state->clear[i].render_pass[fs_key]);
+ if (res != VK_SUCCESS)
+ goto fail;
+
+ res = create_color_pipeline(device, samples, 0, &state->clear[i].color_pipelines[fs_key],
+ state->clear[i].render_pass[fs_key]);
if (res != VK_SUCCESS)
goto fail;
}
+ res = create_depthstencil_renderpass(device,
+ samples,
+ &state->clear[i].depthstencil_rp);
+ if (res != VK_SUCCESS)
+ goto fail;
+
for (uint32_t j = 0; j < NUM_DEPTH_CLEAR_PIPELINES; j++) {
res = create_depthstencil_pipeline(device,
VK_IMAGE_ASPECT_DEPTH_BIT,
samples,
j,
&state->clear[i].depth_only_pipeline[j],
- &state->clear[i].depth_only_rp[j]);
+ state->clear[i].depthstencil_rp);
if (res != VK_SUCCESS)
goto fail;
samples,
j,
&state->clear[i].stencil_only_pipeline[j],
- &state->clear[i].stencil_only_rp[j]);
+ state->clear[i].depthstencil_rp);
if (res != VK_SUCCESS)
goto fail;
samples,
j,
&state->clear[i].depthstencil_pipeline[j],
- &state->clear[i].depthstencil_rp[j]);
+ state->clear[i].depthstencil_rp);
if (res != VK_SUCCESS)
goto fail;
}
static bool
emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
const VkClearAttachment *clear_att,
- const VkClearRect *clear_rect)
+ const VkClearRect *clear_rect,
+ enum radv_cmd_flush_bits *pre_flush,
+ enum radv_cmd_flush_bits *post_flush)
{
const struct radv_subpass *subpass = cmd_buffer->state.subpass;
const uint32_t subpass_att = clear_att->colorAttachment;
if (!iview->image->cmask.size && !iview->image->surface.dcc_size)
return false;
- if (!cmd_buffer->device->allow_fast_clears)
+ if (cmd_buffer->device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
return false;
- if (!radv_layout_has_cmask(iview->image, image_layout))
+ if (!radv_layout_can_fast_clear(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
goto fail;
if (vk_format_get_blocksizebits(iview->image->vk_format) > 64)
goto fail;
/* all layers are bound */
if (iview->base_layer > 0)
goto fail;
- if (iview->image->array_size != iview->layer_count)
+ if (iview->image->info.array_size != iview->layer_count)
goto fail;
- if (iview->image->levels > 1)
+ if (iview->image->info.levels > 1)
goto fail;
- if (iview->image->surface.level[0].mode < RADEON_SURF_MODE_1D)
+ if (iview->image->surface.u.legacy.level[0].mode < RADEON_SURF_MODE_1D)
goto fail;
-
- if (memcmp(&iview->extent, &iview->image->extent, sizeof(iview->extent)))
+ if (!radv_image_extent_compare(iview->image, &iview->extent))
goto fail;
if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
- clear_rect->rect.extent.width != iview->image->extent.width ||
- clear_rect->rect.extent.height != iview->image->extent.height)
+ clear_rect->rect.extent.width != iview->image->info.width ||
+ clear_rect->rect.extent.height != iview->image->info.height)
goto fail;
if (clear_rect->baseArrayLayer != 0)
goto fail;
- if (clear_rect->layerCount != iview->image->array_size)
+ if (clear_rect->layerCount != iview->image->info.array_size)
+ goto fail;
+
+ /* RB+ doesn't work with CMASK fast clear on Stoney. */
+ if (!iview->image->surface.dcc_size &&
+ cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY)
goto fail;
/* DCC */
if (ret == false)
goto fail;
- cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
- RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
- si_emit_cache_flush(cmd_buffer);
+ if (pre_flush) {
+ cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
+ RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) & ~ *pre_flush;
+ *pre_flush |= cmd_buffer->state.flush_bits;
+ } else
+ cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
+ RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
/* clear cmask buffer */
if (iview->image->surface.dcc_size) {
radv_fill_buffer(cmd_buffer, iview->image->bo,
iview->image->offset + iview->image->cmask.offset,
iview->image->cmask.size, 0);
}
- cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
- RADV_CMD_FLAG_INV_VMEM_L1 |
- RADV_CMD_FLAG_INV_GLOBAL_L2;
+
+ if (post_flush)
+ *post_flush |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
+ RADV_CMD_FLAG_INV_VMEM_L1 |
+ RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
+ else
+ cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
+ RADV_CMD_FLAG_INV_VMEM_L1 |
+ RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
radv_set_color_clear_regs(cmd_buffer, iview->image, subpass_att, clear_color);
static void
emit_clear(struct radv_cmd_buffer *cmd_buffer,
const VkClearAttachment *clear_att,
- const VkClearRect *clear_rect)
+ const VkClearRect *clear_rect,
+ enum radv_cmd_flush_bits *pre_flush,
+ enum radv_cmd_flush_bits *post_flush)
{
if (clear_att->aspectMask & VK_IMAGE_ASPECT_COLOR_BIT) {
- if (!emit_fast_color_clear(cmd_buffer, clear_att, clear_rect))
+ if (!emit_fast_color_clear(cmd_buffer, clear_att, clear_rect,
+ pre_flush, post_flush))
emit_color_clear(cmd_buffer, clear_att, clear_rect);
} else {
assert(clear_att->aspectMask & (VK_IMAGE_ASPECT_DEPTH_BIT |
VK_IMAGE_ASPECT_STENCIL_BIT));
- emit_depthstencil_clear(cmd_buffer, clear_att, clear_rect);
+ if (!emit_fast_htile_clear(cmd_buffer, clear_att, clear_rect,
+ pre_flush, post_flush))
+ emit_depthstencil_clear(cmd_buffer, clear_att, clear_rect);
}
}
{
struct radv_cmd_state *cmd_state = &cmd_buffer->state;
struct radv_meta_saved_state saved_state;
+ enum radv_cmd_flush_bits pre_flush = 0;
+ enum radv_cmd_flush_bits post_flush = 0;
if (!subpass_needs_clear(cmd_buffer))
return;
- radv_meta_save_graphics_reset_vport_scissor(&saved_state, cmd_buffer);
-
- if (cmd_state->framebuffer->layers > 1)
- radv_finishme("clearing multi-layer framebuffer");
+ radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state, cmd_buffer);
VkClearRect clear_rect = {
.rect = cmd_state->render_area,
.baseArrayLayer = 0,
- .layerCount = 1, /* FINISHME: clear multi-layer framebuffer */
+ .layerCount = cmd_state->framebuffer->layers,
};
for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
.clearValue = cmd_state->attachments[a].clear_value,
};
- emit_clear(cmd_buffer, &clear_att, &clear_rect);
+ emit_clear(cmd_buffer, &clear_att, &clear_rect, &pre_flush, &post_flush);
cmd_state->attachments[a].pending_clear_aspects = 0;
}
.clearValue = cmd_state->attachments[ds].clear_value,
};
- emit_clear(cmd_buffer, &clear_att, &clear_rect);
+ emit_clear(cmd_buffer, &clear_att, &clear_rect,
+ &pre_flush, &post_flush);
cmd_state->attachments[ds].pending_clear_aspects = 0;
}
}
radv_meta_restore(&saved_state, cmd_buffer);
+ cmd_buffer->state.flush_bits |= post_flush;
}
static void
.baseArrayLayer = range->baseArrayLayer + layer,
.layerCount = 1
},
- },
- cmd_buffer, VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT);
+ });
VkFramebuffer fb;
radv_CreateFramebuffer(device_h,
.layerCount = 1, /* FINISHME: clear multi-layer framebuffer */
};
- emit_clear(cmd_buffer, &clear_att, &clear_rect);
+ emit_clear(cmd_buffer, &clear_att, &clear_rect, NULL, NULL);
radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
radv_DestroyRenderPass(device_h, pass,
internal_clear_value.color.uint32[0] = value;
}
+ if (format == VK_FORMAT_R4G4_UNORM_PACK8) {
+ uint8_t r, g;
+ format = VK_FORMAT_R8_UINT;
+ r = float_to_ubyte(clear_value->color.float32[0]) >> 4;
+ g = float_to_ubyte(clear_value->color.float32[1]) >> 4;
+ internal_clear_value.color.uint32[0] = (r << 4) | (g & 0xf);
+ }
+
for (uint32_t r = 0; r < range_count; r++) {
const VkImageSubresourceRange *range = &ranges[r];
for (uint32_t l = 0; l < radv_get_levelCount(image, range); ++l) {
const uint32_t layer_count = image->type == VK_IMAGE_TYPE_3D ?
- radv_minify(image->extent.depth, range->baseMipLevel + l) :
+ radv_minify(image->info.depth, range->baseMipLevel + l) :
radv_get_layerCount(image, range);
for (uint32_t s = 0; s < layer_count; ++s) {
if (cs)
radv_meta_begin_cleari(cmd_buffer, &saved_state.compute);
else
- radv_meta_save_graphics_reset_vport_scissor(&saved_state.gfx, cmd_buffer);
+ radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state.gfx, cmd_buffer);
radv_cmd_clear_image(cmd_buffer, image, imageLayout,
(const VkClearValue *) pColor,
RADV_FROM_HANDLE(radv_image, image, image_h);
struct radv_meta_saved_state saved_state;
- radv_meta_save_graphics_reset_vport_scissor(&saved_state, cmd_buffer);
+ radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state, cmd_buffer);
radv_cmd_clear_image(cmd_buffer, image, imageLayout,
(const VkClearValue *) pDepthStencil,
{
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
struct radv_meta_saved_state saved_state;
+ enum radv_cmd_flush_bits pre_flush = 0;
+ enum radv_cmd_flush_bits post_flush = 0;
if (!cmd_buffer->state.subpass)
return;
- radv_meta_save_graphics_reset_vport_scissor(&saved_state, cmd_buffer);
+ radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state, cmd_buffer);
/* FINISHME: We can do better than this dumb loop. It thrashes too much
* state.
*/
for (uint32_t a = 0; a < attachmentCount; ++a) {
for (uint32_t r = 0; r < rectCount; ++r) {
- emit_clear(cmd_buffer, &pAttachments[a], &pRects[r]);
+ emit_clear(cmd_buffer, &pAttachments[a], &pRects[r], &pre_flush, &post_flush);
}
}
radv_meta_restore(&saved_state, cmd_buffer);
+ cmd_buffer->state.flush_bits |= post_flush;
}
projects / mesa.git / blobdiff