{
struct radv_device *device = cmd_buffer->device;
const struct radv_subpass *subpass = cmd_buffer->state.subpass;
- const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
const uint32_t subpass_att = clear_att->colorAttachment;
const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
- const struct radv_image_view *iview = fb ? fb->attachments[pass_att].attachment : NULL;
+ const struct radv_image_view *iview = cmd_buffer->state.attachments ?
+ cmd_buffer->state.attachments[pass_att].iview : NULL;
uint32_t samples, samples_log2;
VkFormat format;
unsigned fs_key;
struct radv_device *device = cmd_buffer->device;
struct radv_meta_state *meta_state = &device->meta_state;
const struct radv_subpass *subpass = cmd_buffer->state.subpass;
- const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
const uint32_t pass_att = ds_att->attachment;
VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
VkImageAspectFlags aspects = clear_att->aspectMask;
- const struct radv_image_view *iview = fb ? fb->attachments[pass_att].attachment : NULL;
+ const struct radv_image_view *iview = cmd_buffer->state.attachments ?
+ cmd_buffer->state.attachments[pass_att].iview : NULL;
uint32_t samples, samples_log2;
VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
radv_meta_restore(&saved_state, cmd_buffer);
return RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
- RADV_CMD_FLAG_INV_VMEM_L1 |
- RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
+ RADV_CMD_FLAG_INV_VCACHE |
+ RADV_CMD_FLAG_WB_L2;
}
static uint32_t
if (!view_mask && clear_rect->layerCount != iview->image->info.array_size)
return false;
- if (cmd_buffer->device->physical_device->rad_info.chip_class < GFX9 &&
+ if (cmd_buffer->device->physical_device->rad_info.chip_class != GFX9 &&
(!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT) ||
((vk_format_aspects(iview->image->vk_format) & VK_IMAGE_ASPECT_STENCIL_BIT) &&
!(aspects & VK_IMAGE_ASPECT_STENCIL_BIT))))
iview->image->planes[0].surface.htile_size, clear_word);
} else {
/* Only clear depth or stencil bytes in the HTILE buffer. */
- assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9);
+ /* TODO: Implement that path for GFX10. */
+ assert(cmd_buffer->device->physical_device->rad_info.chip_class == GFX9);
flush_bits = clear_htile_mask(cmd_buffer, iview->image->bo,
iview->image->offset + iview->image->htile_offset,
iview->image->planes[0].surface.htile_size, clear_word,
uint32_t
radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer,
- struct radv_image *image, uint32_t value)
+ struct radv_image *image,
+ const VkImageSubresourceRange *range, uint32_t value)
{
- return radv_fill_buffer(cmd_buffer, image->bo,
- image->offset + image->cmask.offset,
- image->cmask.size, value);
+ uint64_t offset = image->offset + image->cmask_offset;
+ uint64_t size;
+
+ if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
+ /* TODO: clear layers. */
+ size = image->planes[0].surface.cmask_size;
+ } else {
+ unsigned cmask_slice_size =
+ image->planes[0].surface.cmask_slice_size;
+
+ offset += cmask_slice_size * range->baseArrayLayer;
+ size = cmask_slice_size * radv_get_layerCount(image, range);
+ }
+
+ return radv_fill_buffer(cmd_buffer, image->bo, offset, size, value);
}
uint32_t
radv_clear_fmask(struct radv_cmd_buffer *cmd_buffer,
- struct radv_image *image, uint32_t value)
+ struct radv_image *image,
+ const VkImageSubresourceRange *range, uint32_t value)
{
- return radv_fill_buffer(cmd_buffer, image->bo,
- image->offset + image->fmask.offset,
- image->fmask.size, value);
-}
+ uint64_t offset = image->offset + image->fmask_offset;
+ uint64_t size;
-uint32_t
-radv_dcc_clear_level(struct radv_cmd_buffer *cmd_buffer,
- const struct radv_image *image,
- uint32_t level, uint32_t value)
-{
- uint64_t offset = image->offset + image->dcc_offset;
- uint32_t size;
+ /* MSAA images do not support mipmap levels. */
+ assert(range->baseMipLevel == 0 &&
+ radv_get_levelCount(image, range) == 1);
if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
- /* Mipmap levels aren't implemented. */
- assert(level == 0);
- size = image->planes[0].surface.dcc_size;
+ /* TODO: clear layers. */
+ size = image->planes[0].surface.fmask_size;
} else {
- const struct legacy_surf_level *surf_level =
- &image->planes[0].surface.u.legacy.level[level];
+ unsigned fmask_slice_size =
+ image->planes[0].surface.u.legacy.fmask.slice_size;
- /* If this is 0, fast clear isn't possible. */
- assert(surf_level->dcc_fast_clear_size);
- offset += surf_level->dcc_offset;
- size = surf_level->dcc_fast_clear_size;
+ offset += fmask_slice_size * range->baseArrayLayer;
+ size = fmask_slice_size * radv_get_layerCount(image, range);
}
return radv_fill_buffer(cmd_buffer, image->bo, offset, size, value);
radv_update_dcc_metadata(cmd_buffer, image, range, true);
for (uint32_t l = 0; l < level_count; l++) {
+ uint64_t offset = image->offset + image->dcc_offset;
uint32_t level = range->baseMipLevel + l;
+ uint64_t size;
+
+ if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
+ /* Mipmap levels aren't implemented. */
+ assert(level == 0);
+ size = image->planes[0].surface.dcc_size;
+ } else {
+ const struct legacy_surf_level *surf_level =
+ &image->planes[0].surface.u.legacy.level[level];
+
+ /* If dcc_fast_clear_size is 0 (which might happens for
+ * mipmaps) the fill buffer operation below is a no-op.
+ * This can only happen during initialization as the
+ * fast clear path fallbacks to slow clears if one
+ * level can't be fast cleared.
+ */
+ offset += surf_level->dcc_offset +
+ surf_level->dcc_slice_fast_clear_size * range->baseArrayLayer;
+ size = surf_level->dcc_slice_fast_clear_size * radv_get_layerCount(image, range);
+ }
- flush_bits |= radv_dcc_clear_level(cmd_buffer, image,
- level, value);
+ flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
+ size, value);
}
return flush_bits;
return radv_fill_buffer(cmd_buffer, image->bo, offset, size, value);
}
+enum {
+ RADV_DCC_CLEAR_REG = 0x20202020U,
+ RADV_DCC_CLEAR_MAIN_1 = 0x80808080U,
+ RADV_DCC_CLEAR_SECONDARY_1 = 0x40404040U
+};
+
static void vi_get_fast_clear_parameters(VkFormat format,
const VkClearColorValue *clear_value,
uint32_t* reset_value,
int i;
*can_avoid_fast_clear_elim = false;
- *reset_value = 0x20202020U;
+ *reset_value = RADV_DCC_CLEAR_REG;
const struct vk_format_description *desc = vk_format_description(format);
if (format == VK_FORMAT_B10G11R11_UFLOAT_PACK32 ||
return;
*can_avoid_fast_clear_elim = true;
+ *reset_value = 0;
if (main_value)
- *reset_value |= 0x80808080U;
+ *reset_value |= RADV_DCC_CLEAR_MAIN_1;
if (extra_value)
- *reset_value |= 0x40404040U;
+ *reset_value |= RADV_DCC_CLEAR_SECONDARY_1;
return;
}
VkClearColorValue clear_value = clear_att->clearValue.color;
uint32_t clear_color[2], flush_bits = 0;
uint32_t cmask_clear_value;
+ VkImageSubresourceRange range = {
+ .aspectMask = iview->aspect_mask,
+ .baseMipLevel = iview->base_mip,
+ .levelCount = iview->level_count,
+ .baseArrayLayer = iview->base_layer,
+ .layerCount = iview->layer_count,
+ };
if (pre_flush) {
cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
uint32_t reset_value;
bool can_avoid_fast_clear_elim;
bool need_decompress_pass = false;
- VkImageSubresourceRange range = {
- .aspectMask = iview->aspect_mask,
- .baseMipLevel = iview->base_mip,
- .levelCount = iview->level_count,
- .baseArrayLayer = iview->base_layer,
- .layerCount = iview->layer_count,
- };
vi_get_fast_clear_parameters(iview->vk_format,
&clear_value, &reset_value,
if (radv_image_has_cmask(iview->image)) {
flush_bits = radv_clear_cmask(cmd_buffer, iview->image,
- cmask_clear_value);
+ &range, cmask_clear_value);
need_decompress_pass = true;
}
need_decompress_pass);
} else {
flush_bits = radv_clear_cmask(cmd_buffer, iview->image,
- cmask_clear_value);
+ &range, cmask_clear_value);
}
if (post_flush) {
return;
VkImageLayout image_layout = subpass->color_attachments[subpass_att].layout;
- const struct radv_image_view *iview = fb ? fb->attachments[pass_att].attachment : NULL;
+ const struct radv_image_view *iview = fb ? cmd_buffer->state.attachments[pass_att].iview : NULL;
VkClearColorValue clear_value = clear_att->clearValue.color;
if (radv_can_fast_clear_color(cmd_buffer, iview, image_layout,
if (ds_resolve_clear)
ds_att = subpass->ds_resolve_attachment;
- if (ds_att->attachment == VK_ATTACHMENT_UNUSED)
+ if (!ds_att || ds_att->attachment == VK_ATTACHMENT_UNUSED)
return;
VkImageLayout image_layout = ds_att->layout;
- const struct radv_image_view *iview = fb ? fb->attachments[ds_att->attachment].attachment : NULL;
+ const struct radv_image_view *iview = fb ? cmd_buffer->state.attachments[ds_att->attachment].iview : NULL;
VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
assert(aspects & (VK_IMAGE_ASPECT_DEPTH_BIT |
projects / mesa.git / blobdiff