.attachment = VK_ATTACHMENT_UNUSED,
.layout = VK_IMAGE_LAYOUT_GENERAL,
},
- .preserveAttachmentCount = 1,
- .pPreserveAttachments = (uint32_t[]) { 0 },
+ .preserveAttachmentCount = 0,
+ .pPreserveAttachments = NULL,
},
.dependencyCount = 0,
}, &device->meta_state.alloc, pass);
{
struct radv_device *device = cmd_buffer->device;
const struct radv_subpass *subpass = cmd_buffer->state.subpass;
- const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
const uint32_t subpass_att = clear_att->colorAttachment;
const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
- const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
- const uint32_t samples = iview->image->info.samples;
- const uint32_t samples_log2 = ffs(samples) - 1;
- unsigned fs_key = radv_format_meta_fs_key(iview->vk_format);
+ const struct radv_image_view *iview = cmd_buffer->state.attachments ?
+ cmd_buffer->state.attachments[pass_att].iview : NULL;
+ uint32_t samples, samples_log2;
+ VkFormat format;
+ unsigned fs_key;
VkClearColorValue clear_value = clear_att->clearValue.color;
VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
VkPipeline pipeline;
+ /* When a framebuffer is bound to the current command buffer, get the
+ * number of samples from it. Otherwise, get the number of samples from
+ * the render pass because it's likely a secondary command buffer.
+ */
+ if (iview) {
+ samples = iview->image->info.samples;
+ format = iview->vk_format;
+ } else {
+ samples = cmd_buffer->state.pass->attachments[pass_att].samples;
+ format = cmd_buffer->state.pass->attachments[pass_att].format;
+ }
+
+ samples_log2 = ffs(samples) - 1;
+ fs_key = radv_format_meta_fs_key(format);
+
if (fs_key == -1) {
radv_finishme("color clears incomplete");
return;
.color_attachments = (struct radv_subpass_attachment[]) {
subpass->color_attachments[clear_att->colorAttachment]
},
- .depth_stencil_attachment = (struct radv_subpass_attachment) { VK_ATTACHMENT_UNUSED, VK_IMAGE_LAYOUT_UNDEFINED }
+ .depth_stencil_attachment = NULL,
};
- radv_cmd_buffer_set_subpass(cmd_buffer, &clear_subpass, false);
+ radv_cmd_buffer_set_subpass(cmd_buffer, &clear_subpass);
radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
pipeline);
radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, clear_rect->baseArrayLayer);
}
- radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
+ radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
}
.attachment = 0,
.layout = VK_IMAGE_LAYOUT_GENERAL,
},
- .preserveAttachmentCount = 1,
- .pPreserveAttachments = (uint32_t[]) { 0 },
+ .preserveAttachmentCount = 0,
+ .pPreserveAttachments = NULL,
},
.dependencyCount = 0,
}, &device->meta_state.alloc, render_pass);
const VkClearRect *clear_rect,
VkClearDepthStencilValue clear_value)
{
+ if (!iview)
+ return false;
+
uint32_t queue_mask = radv_image_queue_family_mask(iview->image,
cmd_buffer->queue_family_index,
cmd_buffer->queue_family_index);
if (radv_image_has_htile(iview->image) &&
iview->base_mip == 0 &&
iview->base_layer == 0 &&
+ iview->layer_count == iview->image->info.array_size &&
radv_layout_is_htile_compressed(iview->image, layout, queue_mask) &&
- !radv_image_extent_compare(iview->image, &iview->extent))
+ radv_image_extent_compare(iview->image, &iview->extent))
return true;
return false;
}
static void
emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer,
const VkClearAttachment *clear_att,
- const VkClearRect *clear_rect)
+ const VkClearRect *clear_rect,
+ struct radv_subpass_attachment *ds_att,
+ uint32_t view_mask)
{
struct radv_device *device = cmd_buffer->device;
struct radv_meta_state *meta_state = &device->meta_state;
const struct radv_subpass *subpass = cmd_buffer->state.subpass;
- const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
- const uint32_t pass_att = subpass->depth_stencil_attachment.attachment;
+ const uint32_t pass_att = ds_att->attachment;
VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
VkImageAspectFlags aspects = clear_att->aspectMask;
- const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
- const uint32_t samples = iview->image->info.samples;
- const uint32_t samples_log2 = ffs(samples) - 1;
+ const struct radv_image_view *iview = cmd_buffer->state.attachments ?
+ cmd_buffer->state.attachments[pass_att].iview : NULL;
+ uint32_t samples, samples_log2;
VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
+ /* When a framebuffer is bound to the current command buffer, get the
+ * number of samples from it. Otherwise, get the number of samples from
+ * the render pass because it's likely a secondary command buffer.
+ */
+ if (iview) {
+ samples = iview->image->info.samples;
+ } else {
+ samples = cmd_buffer->state.pass->attachments[pass_att].samples;
+ }
+
+ samples_log2 = ffs(samples) - 1;
+
assert(pass_att != VK_ATTACHMENT_UNUSED);
if (!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
iview,
samples_log2,
aspects,
- subpass->depth_stencil_attachment.layout,
+ ds_att->layout,
clear_rect,
clear_value);
if (!pipeline)
return;
+ struct radv_subpass clear_subpass = {
+ .color_count = 0,
+ .color_attachments = NULL,
+ .depth_stencil_attachment = ds_att,
+ };
+
+ radv_cmd_buffer_set_subpass(cmd_buffer, &clear_subpass);
+
radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
pipeline);
if (depth_view_can_fast_clear(cmd_buffer, iview, aspects,
- subpass->depth_stencil_attachment.layout,
- clear_rect, clear_value))
+ ds_att->layout, clear_rect, clear_value))
radv_update_ds_clear_metadata(cmd_buffer, iview->image,
clear_value, aspects);
radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
- radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, clear_rect->baseArrayLayer);
+ if (view_mask) {
+ unsigned i;
+ for_each_bit(i, view_mask)
+ radv_CmdDraw(cmd_buffer_h, 3, 1, 0, i);
+ } else {
+ radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, clear_rect->baseArrayLayer);
+ }
if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
radv_CmdSetStencilReference(cmd_buffer_h, VK_STENCIL_FACE_FRONT_BIT,
prev_reference);
}
+
+ radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
}
static uint32_t
radv_meta_restore(&saved_state, cmd_buffer);
return RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
- RADV_CMD_FLAG_INV_VMEM_L1 |
- RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
+ RADV_CMD_FLAG_INV_VCACHE |
+ RADV_CMD_FLAG_WB_L2;
}
static uint32_t
{
uint32_t clear_value;
- if (!image->surface.has_stencil) {
+ if (!image->planes[0].surface.has_stencil) {
clear_value = value.depth ? 0xfffffff0 : 0;
} else {
clear_value = value.depth ? 0xfffc0000 : 0;
{
uint32_t mask = 0;
- if (!image->surface.has_stencil) {
+ if (!image->planes[0].surface.has_stencil) {
/* All the HTILE buffer is used when there is no stencil. */
mask = UINT32_MAX;
} else {
} else {
if (!radv_image_has_htile(image))
return false;
-
- /* GFX8 only supports 32-bit depth surfaces but we can enable
- * TC-compat HTILE for 16-bit surfaces if no Z planes are
- * compressed. Though, fast HTILE clears don't seem to work.
- */
- if (device->physical_device->rad_info.chip_class == VI &&
- image->vk_format == VK_FORMAT_D16_UNORM)
- return false;
}
/* Do not fast clears 3D images. */
radv_image_view_can_fast_clear(struct radv_device *device,
const struct radv_image_view *iview)
{
- struct radv_image *image = iview->image;
+ struct radv_image *image;
+
+ if (!iview)
+ return false;
+ image = iview->image;
/* Only fast clear if the image itself can be fast cleared. */
if (!radv_image_can_fast_clear(device, image))
VkImageLayout image_layout,
VkImageAspectFlags aspects,
const VkClearRect *clear_rect,
- const VkClearDepthStencilValue clear_value)
+ const VkClearDepthStencilValue clear_value,
+ uint32_t view_mask)
{
if (!radv_image_view_can_fast_clear(cmd_buffer->device, iview))
return false;
clear_rect->rect.extent.height != iview->image->info.height)
return false;
- if (clear_rect->baseArrayLayer != 0)
+ if (view_mask && (iview->image->info.array_size >= 32 ||
+ (1u << iview->image->info.array_size) - 1u != view_mask))
return false;
- if (clear_rect->layerCount != iview->image->info.array_size)
+ if (!view_mask && clear_rect->baseArrayLayer != 0)
+ return false;
+ if (!view_mask && clear_rect->layerCount != iview->image->info.array_size)
return false;
- if (cmd_buffer->device->physical_device->rad_info.chip_class < GFX9 &&
+ if (cmd_buffer->device->physical_device->rad_info.chip_class != GFX9 &&
(!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT) ||
((vk_format_aspects(iview->image->vk_format) & VK_IMAGE_ASPECT_STENCIL_BIT) &&
!(aspects & VK_IMAGE_ASPECT_STENCIL_BIT))))
/* Clear the whole HTILE buffer. */
flush_bits = radv_fill_buffer(cmd_buffer, iview->image->bo,
iview->image->offset + iview->image->htile_offset,
- iview->image->surface.htile_size, clear_word);
+ iview->image->planes[0].surface.htile_size, clear_word);
} else {
/* Only clear depth or stencil bytes in the HTILE buffer. */
- assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9);
+ /* TODO: Implement that path for GFX10. */
+ assert(cmd_buffer->device->physical_device->rad_info.chip_class == GFX9);
flush_bits = clear_htile_mask(cmd_buffer, iview->image->bo,
iview->image->offset + iview->image->htile_offset,
- iview->image->surface.htile_size, clear_word,
+ iview->image->planes[0].surface.htile_size, clear_word,
htile_mask);
}
b.shader->info.cs.local_size[1] = 1;
b.shader->info.cs.local_size[2] = 1;
- nir_ssa_def *invoc_id = nir_load_system_value(&b, nir_intrinsic_load_local_invocation_id, 0);
- nir_ssa_def *wg_id = nir_load_system_value(&b, nir_intrinsic_load_work_group_id, 0);
+ nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b);
+ nir_ssa_def *wg_id = nir_load_work_group_id(&b);
nir_ssa_def *block_size = nir_imm_ivec4(&b,
b.shader->info.cs.local_size[0],
b.shader->info.cs.local_size[1],
nir_intrinsic_vulkan_resource_index);
buf->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
+ buf->num_components = 1;
nir_intrinsic_set_desc_set(buf, 0);
nir_intrinsic_set_binding(buf, 0);
- nir_ssa_dest_init(&buf->instr, &buf->dest, 1, 32, NULL);
+ nir_ssa_dest_init(&buf->instr, &buf->dest, buf->num_components, 32, NULL);
nir_builder_instr_insert(&b, &buf->instr);
nir_intrinsic_instr *constants =
store->src[1] = nir_src_for_ssa(&buf->dest.ssa);
store->src[2] = nir_src_for_ssa(offset);
nir_intrinsic_set_write_mask(store, 0xf);
+ nir_intrinsic_set_access(store, ACCESS_NON_READABLE);
store->num_components = 4;
nir_builder_instr_insert(&b, &store->instr);
uint32_t
radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer,
- struct radv_image *image, uint32_t value)
+ struct radv_image *image,
+ const VkImageSubresourceRange *range, uint32_t value)
{
- return radv_fill_buffer(cmd_buffer, image->bo,
- image->offset + image->cmask.offset,
- image->cmask.size, value);
+ uint64_t offset = image->offset + image->cmask_offset;
+ uint64_t size;
+
+ if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
+ /* TODO: clear layers. */
+ size = image->planes[0].surface.cmask_size;
+ } else {
+ unsigned cmask_slice_size =
+ image->planes[0].surface.cmask_slice_size;
+
+ offset += cmask_slice_size * range->baseArrayLayer;
+ size = cmask_slice_size * radv_get_layerCount(image, range);
+ }
+
+ return radv_fill_buffer(cmd_buffer, image->bo, offset, size, value);
+}
+
+
+uint32_t
+radv_clear_fmask(struct radv_cmd_buffer *cmd_buffer,
+ struct radv_image *image,
+ const VkImageSubresourceRange *range, uint32_t value)
+{
+ uint64_t offset = image->offset + image->fmask_offset;
+ uint64_t size;
+
+ /* MSAA images do not support mipmap levels. */
+ assert(range->baseMipLevel == 0 &&
+ radv_get_levelCount(image, range) == 1);
+
+ if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
+ /* TODO: clear layers. */
+ size = image->planes[0].surface.fmask_size;
+ } else {
+ unsigned fmask_slice_size =
+ image->planes[0].surface.u.legacy.fmask.slice_size;
+
+
+ offset += fmask_slice_size * range->baseArrayLayer;
+ size = fmask_slice_size * radv_get_layerCount(image, range);
+ }
+
+ return radv_fill_buffer(cmd_buffer, image->bo, offset, size, value);
}
uint32_t
radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer,
- struct radv_image *image, uint32_t value)
+ struct radv_image *image,
+ const VkImageSubresourceRange *range, uint32_t value)
{
- return radv_fill_buffer(cmd_buffer, image->bo,
- image->offset + image->dcc_offset,
- image->surface.dcc_size, value);
+ uint32_t level_count = radv_get_levelCount(image, range);
+ uint32_t flush_bits = 0;
+
+ /* Mark the image as being compressed. */
+ radv_update_dcc_metadata(cmd_buffer, image, range, true);
+
+ for (uint32_t l = 0; l < level_count; l++) {
+ uint64_t offset = image->offset + image->dcc_offset;
+ uint32_t level = range->baseMipLevel + l;
+ uint64_t size;
+
+ if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
+ /* Mipmap levels aren't implemented. */
+ assert(level == 0);
+ size = image->planes[0].surface.dcc_size;
+ } else {
+ const struct legacy_surf_level *surf_level =
+ &image->planes[0].surface.u.legacy.level[level];
+
+ /* If dcc_fast_clear_size is 0 (which might happens for
+ * mipmaps) the fill buffer operation below is a no-op.
+ * This can only happen during initialization as the
+ * fast clear path fallbacks to slow clears if one
+ * level can't be fast cleared.
+ */
+ offset += surf_level->dcc_offset +
+ surf_level->dcc_slice_fast_clear_size * range->baseArrayLayer;
+ size = surf_level->dcc_slice_fast_clear_size * radv_get_layerCount(image, range);
+ }
+
+ flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
+ size, value);
+ }
+
+ return flush_bits;
+}
+
+uint32_t
+radv_clear_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
+ const VkImageSubresourceRange *range, uint32_t value)
+{
+ unsigned layer_count = radv_get_layerCount(image, range);
+ uint64_t size = image->planes[0].surface.htile_slice_size * layer_count;
+ uint64_t offset = image->offset + image->htile_offset +
+ image->planes[0].surface.htile_slice_size * range->baseArrayLayer;
+
+ return radv_fill_buffer(cmd_buffer, image->bo, offset, size, value);
}
+enum {
+ RADV_DCC_CLEAR_REG = 0x20202020U,
+ RADV_DCC_CLEAR_MAIN_1 = 0x80808080U,
+ RADV_DCC_CLEAR_SECONDARY_1 = 0x40404040U
+};
+
static void vi_get_fast_clear_parameters(VkFormat format,
const VkClearColorValue *clear_value,
uint32_t* reset_value,
int i;
*can_avoid_fast_clear_elim = false;
- *reset_value = 0x20202020U;
+ *reset_value = RADV_DCC_CLEAR_REG;
const struct vk_format_description *desc = vk_format_description(format);
if (format == VK_FORMAT_B10G11R11_UFLOAT_PACK32 ||
return;
*can_avoid_fast_clear_elim = true;
+ *reset_value = 0;
if (main_value)
- *reset_value |= 0x80808080U;
+ *reset_value |= RADV_DCC_CLEAR_MAIN_1;
if (extra_value)
- *reset_value |= 0x40404040U;
+ *reset_value |= RADV_DCC_CLEAR_SECONDARY_1;
return;
}
clear_color, &clear_value))
return false;
- if (radv_image_has_dcc(iview->image)) {
+ if (radv_dcc_enabled(iview->image, iview->base_mip)) {
bool can_avoid_fast_clear_elim;
uint32_t reset_value;
if (!can_avoid_fast_clear_elim)
return false;
}
+
+ if (iview->image->info.levels > 1 &&
+ cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) {
+ for (uint32_t l = 0; l < iview->level_count; l++) {
+ uint32_t level = iview->base_mip + l;
+ struct legacy_surf_level *surf_level =
+ &iview->image->planes[0].surface.u.legacy.level[level];
+
+ /* Do not fast clears if one level can't be
+ * fast cleared.
+ */
+ if (!surf_level->dcc_fast_clear_size)
+ return false;
+ }
+ }
}
return true;
VkClearColorValue clear_value = clear_att->clearValue.color;
uint32_t clear_color[2], flush_bits = 0;
uint32_t cmask_clear_value;
+ VkImageSubresourceRange range = {
+ .aspectMask = iview->aspect_mask,
+ .baseMipLevel = iview->base_mip,
+ .levelCount = iview->level_count,
+ .baseArrayLayer = iview->base_layer,
+ .layerCount = iview->layer_count,
+ };
if (pre_flush) {
cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
cmask_clear_value = radv_get_cmask_fast_clear_value(iview->image);
/* clear cmask buffer */
- if (radv_image_has_dcc(iview->image)) {
+ if (radv_dcc_enabled(iview->image, iview->base_mip)) {
uint32_t reset_value;
bool can_avoid_fast_clear_elim;
bool need_decompress_pass = false;
if (radv_image_has_cmask(iview->image)) {
flush_bits = radv_clear_cmask(cmd_buffer, iview->image,
- cmask_clear_value);
+ &range, cmask_clear_value);
need_decompress_pass = true;
}
if (!can_avoid_fast_clear_elim)
need_decompress_pass = true;
- flush_bits |= radv_clear_dcc(cmd_buffer, iview->image, reset_value);
+ flush_bits |= radv_clear_dcc(cmd_buffer, iview->image, &range,
+ reset_value);
- radv_update_fce_metadata(cmd_buffer, iview->image,
+ radv_update_fce_metadata(cmd_buffer, iview->image, &range,
need_decompress_pass);
} else {
flush_bits = radv_clear_cmask(cmd_buffer, iview->image,
- cmask_clear_value);
+ &range, cmask_clear_value);
}
if (post_flush) {
*post_flush |= flush_bits;
}
- radv_update_color_clear_metadata(cmd_buffer, iview->image, subpass_att,
+ radv_update_color_clear_metadata(cmd_buffer, iview, subpass_att,
clear_color);
}
const VkClearRect *clear_rect,
enum radv_cmd_flush_bits *pre_flush,
enum radv_cmd_flush_bits *post_flush,
- uint32_t view_mask)
+ uint32_t view_mask,
+ bool ds_resolve_clear)
{
const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
const struct radv_subpass *subpass = cmd_buffer->state.subpass;
if (aspects & VK_IMAGE_ASPECT_COLOR_BIT) {
const uint32_t subpass_att = clear_att->colorAttachment;
+ assert(subpass_att < subpass->color_count);
const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
+ if (pass_att == VK_ATTACHMENT_UNUSED)
+ return;
+
VkImageLayout image_layout = subpass->color_attachments[subpass_att].layout;
- const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
+ const struct radv_image_view *iview = fb ? cmd_buffer->state.attachments[pass_att].iview : NULL;
VkClearColorValue clear_value = clear_att->clearValue.color;
if (radv_can_fast_clear_color(cmd_buffer, iview, image_layout,
emit_color_clear(cmd_buffer, clear_att, clear_rect, view_mask);
}
} else {
- const uint32_t pass_att = subpass->depth_stencil_attachment.attachment;
- VkImageLayout image_layout = subpass->depth_stencil_attachment.layout;
- const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
+ struct radv_subpass_attachment *ds_att = subpass->depth_stencil_attachment;
+
+ if (ds_resolve_clear)
+ ds_att = subpass->ds_resolve_attachment;
+
+ if (!ds_att || ds_att->attachment == VK_ATTACHMENT_UNUSED)
+ return;
+
+ VkImageLayout image_layout = ds_att->layout;
+ const struct radv_image_view *iview = fb ? cmd_buffer->state.attachments[ds_att->attachment].iview : NULL;
VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
assert(aspects & (VK_IMAGE_ASPECT_DEPTH_BIT |
VK_IMAGE_ASPECT_STENCIL_BIT));
if (radv_can_fast_clear_depth(cmd_buffer, iview, image_layout,
- aspects, clear_rect, clear_value)) {
+ aspects, clear_rect, clear_value,
+ view_mask)) {
radv_fast_clear_depth(cmd_buffer, iview, clear_att,
pre_flush, post_flush);
} else {
- emit_depthstencil_clear(cmd_buffer, clear_att, clear_rect);
+ emit_depthstencil_clear(cmd_buffer, clear_att, clear_rect,
+ ds_att, view_mask);
}
}
}
return true;
}
- a = cmd_state->subpass->depth_stencil_attachment.attachment;
+ if (cmd_state->subpass->depth_stencil_attachment) {
+ a = cmd_state->subpass->depth_stencil_attachment->attachment;
+ if (radv_attachment_needs_clear(cmd_state, a))
+ return true;
+ }
+
+ if (!cmd_state->subpass->ds_resolve_attachment)
+ return false;
+
+ a = cmd_state->subpass->ds_resolve_attachment->attachment;
return radv_attachment_needs_clear(cmd_state, a);
}
struct radv_attachment_state *attachment,
const VkClearAttachment *clear_att,
enum radv_cmd_flush_bits *pre_flush,
- enum radv_cmd_flush_bits *post_flush)
+ enum radv_cmd_flush_bits *post_flush,
+ bool ds_resolve_clear)
{
struct radv_cmd_state *cmd_state = &cmd_buffer->state;
uint32_t view_mask = cmd_state->subpass->view_mask;
};
emit_clear(cmd_buffer, clear_att, &clear_rect, pre_flush, post_flush,
- view_mask & ~attachment->cleared_views);
+ view_mask & ~attachment->cleared_views, ds_resolve_clear);
if (view_mask)
attachment->cleared_views |= view_mask;
else
radv_subpass_clear_attachment(cmd_buffer,
&cmd_state->attachments[a],
&clear_att, &pre_flush,
- &post_flush);
+ &post_flush, false);
}
- uint32_t ds = cmd_state->subpass->depth_stencil_attachment.attachment;
- if (radv_attachment_needs_clear(cmd_state, ds)) {
- VkClearAttachment clear_att = {
- .aspectMask = cmd_state->attachments[ds].pending_clear_aspects,
- .clearValue = cmd_state->attachments[ds].clear_value,
- };
+ if (cmd_state->subpass->depth_stencil_attachment) {
+ uint32_t ds = cmd_state->subpass->depth_stencil_attachment->attachment;
+ if (radv_attachment_needs_clear(cmd_state, ds)) {
+ VkClearAttachment clear_att = {
+ .aspectMask = cmd_state->attachments[ds].pending_clear_aspects,
+ .clearValue = cmd_state->attachments[ds].clear_value,
+ };
+
+ radv_subpass_clear_attachment(cmd_buffer,
+ &cmd_state->attachments[ds],
+ &clear_att, &pre_flush,
+ &post_flush, false);
+ }
+ }
- radv_subpass_clear_attachment(cmd_buffer,
- &cmd_state->attachments[ds],
- &clear_att, &pre_flush,
- &post_flush);
+ if (cmd_state->subpass->ds_resolve_attachment) {
+ uint32_t ds_resolve = cmd_state->subpass->ds_resolve_attachment->attachment;
+ if (radv_attachment_needs_clear(cmd_state, ds_resolve)) {
+ VkClearAttachment clear_att = {
+ .aspectMask = cmd_state->attachments[ds_resolve].pending_clear_aspects,
+ .clearValue = cmd_state->attachments[ds_resolve].clear_value,
+ };
+
+ radv_subpass_clear_attachment(cmd_buffer,
+ &cmd_state->attachments[ds_resolve],
+ &clear_att, &pre_flush,
+ &post_flush, true);
+ }
}
radv_meta_restore(&saved_state, cmd_buffer);
.layerCount = 1, /* FINISHME: clear multi-layer framebuffer */
};
- emit_clear(cmd_buffer, &clear_att, &clear_rect, NULL, NULL, 0);
+ emit_clear(cmd_buffer, &clear_att, &clear_rect, NULL, NULL, 0, false);
radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
radv_DestroyRenderPass(device_h, pass,
radv_DestroyFramebuffer(device_h, fb,
&cmd_buffer->pool->alloc);
}
+
+/**
+ * Return TRUE if a fast color or depth clear has been performed.
+ */
+static bool
+radv_fast_clear_range(struct radv_cmd_buffer *cmd_buffer,
+ struct radv_image *image,
+ VkFormat format,
+ VkImageLayout image_layout,
+ const VkImageSubresourceRange *range,
+ const VkClearValue *clear_val)
+{
+ struct radv_image_view iview;
+
+ radv_image_view_init(&iview, cmd_buffer->device,
+ &(VkImageViewCreateInfo) {
+ .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
+ .image = radv_image_to_handle(image),
+ .viewType = radv_meta_get_view_type(image),
+ .format = image->vk_format,
+ .subresourceRange = {
+ .aspectMask = range->aspectMask,
+ .baseMipLevel = range->baseMipLevel,
+ .levelCount = range->levelCount,
+ .baseArrayLayer = range->baseArrayLayer,
+ .layerCount = range->layerCount,
+ },
+ });
+
+ VkClearRect clear_rect = {
+ .rect = {
+ .offset = { 0, 0 },
+ .extent = {
+ radv_minify(image->info.width, range->baseMipLevel),
+ radv_minify(image->info.height, range->baseMipLevel),
+ },
+ },
+ .baseArrayLayer = range->baseArrayLayer,
+ .layerCount = range->layerCount,
+ };
+
+ VkClearAttachment clear_att = {
+ .aspectMask = range->aspectMask,
+ .colorAttachment = 0,
+ .clearValue = *clear_val,
+ };
+
+ if (vk_format_is_color(format)) {
+ if (radv_can_fast_clear_color(cmd_buffer, &iview,
+ image_layout, &clear_rect,
+ clear_att.clearValue.color, 0)) {
+ radv_fast_clear_color(cmd_buffer, &iview, &clear_att,
+ clear_att.colorAttachment,
+ NULL, NULL);
+ return true;
+ }
+ } else {
+ if (radv_can_fast_clear_depth(cmd_buffer, &iview, image_layout,
+ range->aspectMask, &clear_rect,
+ clear_att.clearValue.depthStencil, 0)) {
+ radv_fast_clear_depth(cmd_buffer, &iview, &clear_att,
+ NULL, NULL);
+ return true;
+ }
+ }
+
+ return false;
+}
+
static void
radv_cmd_clear_image(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *image,
internal_clear_value.color.uint32[0] = (r << 4) | (g & 0xf);
}
+ if (format == VK_FORMAT_R32G32B32_UINT ||
+ format == VK_FORMAT_R32G32B32_SINT ||
+ format == VK_FORMAT_R32G32B32_SFLOAT)
+ cs = true;
+
for (uint32_t r = 0; r < range_count; r++) {
const VkImageSubresourceRange *range = &ranges[r];
+
+ /* Try to perform a fast clear first, otherwise fallback to
+ * the legacy path.
+ */
+ if (!cs &&
+ radv_fast_clear_range(cmd_buffer, image, format,
+ image_layout, range,
+ &internal_clear_value)) {
+ continue;
+ }
+
for (uint32_t l = 0; l < radv_get_levelCount(image, range); ++l) {
const uint32_t layer_count = image->type == VK_IMAGE_TYPE_3D ?
radv_minify(image->info.depth, range->baseMipLevel + l) :
radv_get_layerCount(image, range);
for (uint32_t s = 0; s < layer_count; ++s) {
- if (cs ||
- (format == VK_FORMAT_R32G32B32_UINT ||
- format == VK_FORMAT_R32G32B32_SINT ||
- format == VK_FORMAT_R32G32B32_SFLOAT)) {
+ if (cs) {
struct radv_meta_blit2d_surf surf;
surf.format = format;
surf.image = image;
for (uint32_t a = 0; a < attachmentCount; ++a) {
for (uint32_t r = 0; r < rectCount; ++r) {
emit_clear(cmd_buffer, &pAttachments[a], &pRects[r], &pre_flush, &post_flush,
- cmd_buffer->state.subpass->view_mask);
+ cmd_buffer->state.subpass->view_mask, false);
}
}
projects / mesa.git / blobdiff