radv: set depth/stencil enable values correctly for the meta clear path

[mesa.git] / src / amd / vulkan / radv_meta_clear.c

diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index 62c17af7fe9aff62f513f41e6b3a287c12f66e56..4d4dd1091655852b1331cde7a68b27797cb57730 100644 (file)
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -664,11 +664,11 @@ create_depthstencil_pipeline(struct radv_device *device,
 
        const VkPipelineDepthStencilStateCreateInfo ds_state = {
                .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
-               .depthTestEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
+               .depthTestEnable = !!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
                .depthCompareOp = VK_COMPARE_OP_ALWAYS,
-               .depthWriteEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
+               .depthWriteEnable = !!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
                .depthBoundsTestEnable = false,
-               .stencilTestEnable = (aspects & VK_IMAGE_ASPECT_STENCIL_BIT),
+               .stencilTestEnable = !!(aspects & VK_IMAGE_ASPECT_STENCIL_BIT),
                .front = {
                        .passOp = VK_STENCIL_OP_REPLACE,
                        .compareOp = VK_COMPARE_OP_ALWAYS,
@@ -1481,7 +1481,7 @@ radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer,
                 struct radv_image *image,
                 const VkImageSubresourceRange *range, uint32_t value)
 {
-       uint64_t offset = image->offset + image->cmask_offset;
+       uint64_t offset = image->offset + image->planes[0].surface.cmask_offset;
        uint64_t size;
 
        if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
@@ -1504,7 +1504,7 @@ radv_clear_fmask(struct radv_cmd_buffer *cmd_buffer,
                 struct radv_image *image,
                 const VkImageSubresourceRange *range, uint32_t value)
 {
-       uint64_t offset = image->offset + image->fmask_offset;
+       uint64_t offset = image->offset + image->planes[0].surface.fmask_offset;
        uint64_t size;
 
        /* MSAA images do not support mipmap levels. */
@@ -1538,7 +1538,7 @@ radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer,
        radv_update_dcc_metadata(cmd_buffer, image, range, true);
 
        for (uint32_t l = 0; l < level_count; l++) {
-               uint64_t offset = image->offset + image->dcc_offset;
+               uint64_t offset = image->offset + image->planes[0].surface.dcc_offset;
                uint32_t level = range->baseMipLevel + l;
                uint64_t size;
 
@@ -1576,7 +1576,7 @@ radv_clear_htile(struct radv_cmd_buffer *cmd_buffer,
 {
        unsigned layer_count = radv_get_layerCount(image, range);
        uint64_t size = image->planes[0].surface.htile_slice_size * layer_count;
-       uint64_t offset = image->offset + image->htile_offset +
+       uint64_t offset = image->offset + image->planes[0].surface.htile_offset +
                          image->planes[0].surface.htile_slice_size * range->baseArrayLayer;
        uint32_t htile_mask, flush_bits;