radv: ignore BB labels when splitting the disassembly string

[mesa.git] / src / amd / vulkan / radv_meta_clear.c

diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index 6d6f11b0662bc2b79ce72e8ac804b1116fa5f372..4d4dd1091655852b1331cde7a68b27797cb57730 100644 (file)
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -512,8 +512,12 @@ build_depthstencil_shader(struct nir_shader **out_vs,
        nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL);
        nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
 
-       vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_depthstencil_vs");
-       fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_depthstencil_fs");
+       vs_b.shader->info.name = ralloc_strdup(vs_b.shader,
+                                              unrestricted ? "meta_clear_depthstencil_unrestricted_vs"
+                                                           : "meta_clear_depthstencil_vs");
+       fs_b.shader->info.name = ralloc_strdup(fs_b.shader,
+                                              unrestricted ? "meta_clear_depthstencil_unrestricted_fs"
+                                                           : "meta_clear_depthstencil_fs");
        const struct glsl_type *position_out_type = glsl_vec4_type();
 
        nir_variable *vs_out_pos =
@@ -660,11 +664,11 @@ create_depthstencil_pipeline(struct radv_device *device,
 
        const VkPipelineDepthStencilStateCreateInfo ds_state = {
                .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
-               .depthTestEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
+               .depthTestEnable = !!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
                .depthCompareOp = VK_COMPARE_OP_ALWAYS,
-               .depthWriteEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
+               .depthWriteEnable = !!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
                .depthBoundsTestEnable = false,
-               .stencilTestEnable = (aspects & VK_IMAGE_ASPECT_STENCIL_BIT),
+               .stencilTestEnable = !!(aspects & VK_IMAGE_ASPECT_STENCIL_BIT),
                .front = {
                        .passOp = VK_STENCIL_OP_REPLACE,
                        .compareOp = VK_COMPARE_OP_ALWAYS,
@@ -1477,7 +1481,7 @@ radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer,
                 struct radv_image *image,
                 const VkImageSubresourceRange *range, uint32_t value)
 {
-       uint64_t offset = image->offset + image->cmask_offset;
+       uint64_t offset = image->offset + image->planes[0].surface.cmask_offset;
        uint64_t size;
 
        if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
@@ -1500,7 +1504,7 @@ radv_clear_fmask(struct radv_cmd_buffer *cmd_buffer,
                 struct radv_image *image,
                 const VkImageSubresourceRange *range, uint32_t value)
 {
-       uint64_t offset = image->offset + image->fmask_offset;
+       uint64_t offset = image->offset + image->planes[0].surface.fmask_offset;
        uint64_t size;
 
        /* MSAA images do not support mipmap levels. */
@@ -1534,7 +1538,7 @@ radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer,
        radv_update_dcc_metadata(cmd_buffer, image, range, true);
 
        for (uint32_t l = 0; l < level_count; l++) {
-               uint64_t offset = image->offset + image->dcc_offset;
+               uint64_t offset = image->offset + image->planes[0].surface.dcc_offset;
                uint32_t level = range->baseMipLevel + l;
                uint64_t size;
 
@@ -1572,7 +1576,7 @@ radv_clear_htile(struct radv_cmd_buffer *cmd_buffer,
 {
        unsigned layer_count = radv_get_layerCount(image, range);
        uint64_t size = image->planes[0].surface.htile_slice_size * layer_count;
-       uint64_t offset = image->offset + image->htile_offset +
+       uint64_t offset = image->offset + image->planes[0].surface.htile_offset +
                          image->planes[0].surface.htile_slice_size * range->baseArrayLayer;
        uint32_t htile_mask, flush_bits;
 
@@ -2153,22 +2157,24 @@ radv_clear_image_layer(struct radv_cmd_buffer *cmd_buffer,
                              &cmd_buffer->pool->alloc,
                              &pass);
 
-       radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
-                               &(VkRenderPassBeginInfo) {
-                                       .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
+       radv_cmd_buffer_begin_render_pass(cmd_buffer,
+                                         &(VkRenderPassBeginInfo) {
+                                               .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
                                                .renderArea = {
                                                .offset = { 0, 0, },
                                                .extent = {
                                                        .width = width,
                                                        .height = height,
+                                                       },
                                                },
-                                       },
                                                .renderPass = pass,
                                                .framebuffer = fb,
                                                .clearValueCount = 0,
                                                .pClearValues = NULL,
-                                               },
-                               VK_SUBPASS_CONTENTS_INLINE);
+                                        });
+
+       radv_cmd_buffer_set_subpass(cmd_buffer,
+                                   &cmd_buffer->state.pass->subpasses[0]);
 
        VkClearAttachment clear_att = {
                .aspectMask = range->aspectMask,
@@ -2187,7 +2193,7 @@ radv_clear_image_layer(struct radv_cmd_buffer *cmd_buffer,
 
        emit_clear(cmd_buffer, &clear_att, &clear_rect, NULL, NULL, 0, false);
 
-       radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
+       radv_cmd_buffer_end_render_pass(cmd_buffer);
        radv_DestroyRenderPass(device_h, pass,
                               &cmd_buffer->pool->alloc);
        radv_DestroyFramebuffer(device_h, fb,