radv: Fix the autotools build take 2.
[mesa.git] / src / amd / vulkan / radv_meta_clear.c
index fd2caf3d0ce95781774aae7015ed1563983e0012..98fb8fa6a7ca52b397e254fd7cace8d1ea09ee58 100644 (file)
@@ -374,10 +374,8 @@ emit_color_clear(struct radv_cmd_buffer *cmd_buffer,
 
        radv_cmd_buffer_set_subpass(cmd_buffer, &clear_subpass, false);
 
-       if (cmd_buffer->state.pipeline != radv_pipeline_from_handle(pipeline)) {
-               radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
-                                          pipeline);
-       }
+       radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
+                            pipeline);
 
        radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
                        .x = clear_rect->rect.offset.x,
@@ -616,10 +614,6 @@ emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer,
        const uint32_t samples_log2 = ffs(samples) - 1;
        VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
 
-       assert(aspects == VK_IMAGE_ASPECT_DEPTH_BIT ||
-              aspects == VK_IMAGE_ASPECT_STENCIL_BIT ||
-              aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
-                          VK_IMAGE_ASPECT_STENCIL_BIT));
        assert(pass_att != VK_ATTACHMENT_UNUSED);
 
        if (!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
@@ -630,6 +624,7 @@ emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer,
                              VK_SHADER_STAGE_VERTEX_BIT, 0, 4,
                              &clear_value.depth);
 
+       uint32_t prev_reference = cmd_buffer->state.dynamic.stencil_reference.front;
        if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
                radv_CmdSetStencilReference(cmd_buffer_h, VK_STENCIL_FACE_FRONT_BIT,
                                                  clear_value.stencil);
@@ -644,10 +639,8 @@ emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer,
                                                         clear_rect,
                                                         clear_value);
 
-       if (cmd_buffer->state.pipeline != radv_pipeline_from_handle(pipeline)) {
-               radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
-                                    pipeline);
-       }
+       radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
+                            pipeline);
 
        if (depth_view_can_fast_clear(cmd_buffer, iview, aspects,
                                      subpass->depth_stencil_attachment.layout,
@@ -666,6 +659,11 @@ emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer,
        radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
 
        radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, clear_rect->baseArrayLayer);
+
+       if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
+               radv_CmdSetStencilReference(cmd_buffer_h, VK_STENCIL_FACE_FRONT_BIT,
+                                                 prev_reference);
+       }
 }
 
 static bool
@@ -682,12 +680,12 @@ emit_fast_htile_clear(struct radv_cmd_buffer *cmd_buffer,
        const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
        VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
        VkImageAspectFlags aspects = clear_att->aspectMask;
-       uint32_t clear_word;
+       uint32_t clear_word, flush_bits;
 
        if (!iview->image->surface.htile_size)
                return false;
 
-       if (cmd_buffer->device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
+       if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
                return false;
 
        if (!radv_layout_is_htile_compressed(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
@@ -734,20 +732,17 @@ emit_fast_htile_clear(struct radv_cmd_buffer *cmd_buffer,
                cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
                                                RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
 
-       radv_fill_buffer(cmd_buffer, iview->image->bo,
-                        iview->image->offset + iview->image->htile_offset,
-                        iview->image->surface.htile_size, clear_word);
-
+       flush_bits = radv_fill_buffer(cmd_buffer, iview->image->bo,
+                                     iview->image->offset + iview->image->htile_offset,
+                                     iview->image->surface.htile_size, clear_word);
 
        radv_set_depth_clear_regs(cmd_buffer, iview->image, clear_value, aspects);
-       if (post_flush)
-               *post_flush |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
-                              RADV_CMD_FLAG_INV_VMEM_L1 |
-                              RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
-       else
-               cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
-                                               RADV_CMD_FLAG_INV_VMEM_L1 |
-                                               RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
+       if (post_flush) {
+               *post_flush |= flush_bits;
+       } else {
+               cmd_buffer->state.flush_bits |= flush_bits;
+       }
+
        return true;
 fail:
        return false;
@@ -956,13 +951,13 @@ emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
        const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
        const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
        VkClearColorValue clear_value = clear_att->clearValue.color;
-       uint32_t clear_color[2];
+       uint32_t clear_color[2], flush_bits;
        bool ret;
 
        if (!iview->image->cmask.size && !iview->image->surface.dcc_size)
                return false;
 
-       if (cmd_buffer->device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
+       if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
                return false;
 
        if (!radv_layout_can_fast_clear(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
@@ -1025,30 +1020,22 @@ emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
                                             &clear_value, &reset_value,
                                             &can_avoid_fast_clear_elim);
 
-               radv_fill_buffer(cmd_buffer, iview->image->bo,
-                                iview->image->offset + iview->image->dcc_offset,
-                                iview->image->surface.dcc_size, reset_value);
+               flush_bits = radv_fill_buffer(cmd_buffer, iview->image->bo,
+                                             iview->image->offset + iview->image->dcc_offset,
+                                             iview->image->surface.dcc_size, reset_value);
                radv_set_dcc_need_cmask_elim_pred(cmd_buffer, iview->image,
                                                  !can_avoid_fast_clear_elim);
        } else {
-
-               if (iview->image->surface.bpe > 8) {
-                       /* 128 bit formats not supported */
-                       return false;
-               }
-               radv_fill_buffer(cmd_buffer, iview->image->bo,
-                                iview->image->offset + iview->image->cmask.offset,
-                                iview->image->cmask.size, 0);
+               flush_bits = radv_fill_buffer(cmd_buffer, iview->image->bo,
+                                             iview->image->offset + iview->image->cmask.offset,
+                                             iview->image->cmask.size, 0);
        }
 
-       if (post_flush)
-               *post_flush |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
-                              RADV_CMD_FLAG_INV_VMEM_L1 |
-                              RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
-       else
-               cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
-                                               RADV_CMD_FLAG_INV_VMEM_L1 |
-                                               RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
+       if (post_flush) {
+               *post_flush |= flush_bits;
+       } else {
+               cmd_buffer->state.flush_bits |= flush_bits;
+       }
 
        radv_set_color_clear_regs(cmd_buffer, iview->image, subpass_att, clear_color);
 
@@ -1149,7 +1136,9 @@ radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer)
        if (!radv_subpass_needs_clear(cmd_buffer))
                return;
 
-       radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state, cmd_buffer);
+       radv_meta_save(&saved_state, cmd_buffer,
+                      RADV_META_SAVE_GRAPHICS_PIPELINE |
+                      RADV_META_SAVE_CONSTANTS);
 
        for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
                uint32_t a = cmd_state->subpass->color_attachments[i].attachment;
@@ -1370,11 +1359,6 @@ radv_cmd_clear_image(struct radv_cmd_buffer *cmd_buffer,
        }
 }
 
-union meta_saved_state {
-       struct radv_meta_saved_state gfx;
-       struct radv_meta_saved_compute_state compute;
-};
-
 void radv_CmdClearColorImage(
        VkCommandBuffer                             commandBuffer,
        VkImage                                     image_h,
@@ -1385,22 +1369,25 @@ void radv_CmdClearColorImage(
 {
        RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
        RADV_FROM_HANDLE(radv_image, image, image_h);
-       union meta_saved_state saved_state;
+       struct radv_meta_saved_state saved_state;
        bool cs = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
 
-       if (cs)
-               radv_meta_save_compute(&saved_state.compute, cmd_buffer, 16);
-       else
-               radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state.gfx, cmd_buffer);
+       if (cs) {
+               radv_meta_save(&saved_state, cmd_buffer,
+                              RADV_META_SAVE_COMPUTE_PIPELINE |
+                              RADV_META_SAVE_CONSTANTS |
+                              RADV_META_SAVE_DESCRIPTORS);
+       } else {
+               radv_meta_save(&saved_state, cmd_buffer,
+                              RADV_META_SAVE_GRAPHICS_PIPELINE |
+                              RADV_META_SAVE_CONSTANTS);
+       }
 
        radv_cmd_clear_image(cmd_buffer, image, imageLayout,
                             (const VkClearValue *) pColor,
                             rangeCount, pRanges, cs);
 
-       if (cs)
-               radv_meta_restore_compute(&saved_state.compute, cmd_buffer);
-       else
-               radv_meta_restore(&saved_state.gfx, cmd_buffer);
+       radv_meta_restore(&saved_state, cmd_buffer);
 }
 
 void radv_CmdClearDepthStencilImage(
@@ -1415,7 +1402,9 @@ void radv_CmdClearDepthStencilImage(
        RADV_FROM_HANDLE(radv_image, image, image_h);
        struct radv_meta_saved_state saved_state;
 
-       radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state, cmd_buffer);
+       radv_meta_save(&saved_state, cmd_buffer,
+                      RADV_META_SAVE_GRAPHICS_PIPELINE |
+                      RADV_META_SAVE_CONSTANTS);
 
        radv_cmd_clear_image(cmd_buffer, image, imageLayout,
                             (const VkClearValue *) pDepthStencil,
@@ -1439,7 +1428,9 @@ void radv_CmdClearAttachments(
        if (!cmd_buffer->state.subpass)
                return;
 
-       radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state, cmd_buffer);
+       radv_meta_save(&saved_state, cmd_buffer,
+                      RADV_META_SAVE_GRAPHICS_PIPELINE |
+                      RADV_META_SAVE_CONSTANTS);
 
        /* FINISHME: We can do better than this dumb loop. It thrashes too much
         * state.