radv: fix non-0 based layer clears.
[mesa.git] / src / amd / vulkan / radv_meta_clear.c
index 18b4ca9ba2b4af555558fe0f98f63b39626264b3..d007f97b30e3ba516c3531ad3c1526e4075a73cd 100644 (file)
@@ -81,8 +81,10 @@ build_color_shaders(struct nir_shader **out_vs,
        vs_out_layer->data.location = VARYING_SLOT_LAYER;
        vs_out_layer->data.interpolation = INTERP_MODE_FLAT;
        nir_ssa_def *inst_id = nir_load_system_value(&vs_b, nir_intrinsic_load_instance_id, 0);
+       nir_ssa_def *base_instance = nir_load_system_value(&vs_b, nir_intrinsic_load_base_instance, 0);
 
-       nir_store_var(&vs_b, vs_out_layer, inst_id, 0x1);
+       nir_ssa_def *layer_id = nir_iadd(&vs_b, inst_id, base_instance);
+       nir_store_var(&vs_b, vs_out_layer, layer_id, 0x1);
 
        *out_vs = vs_b.shader;
        *out_fs = fs_b.shader;
@@ -398,7 +400,7 @@ emit_color_clear(struct radv_cmd_buffer *cmd_buffer,
 
        radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
 
-       radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, 0);
+       radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, clear_rect->baseArrayLayer);
 
        radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
 }
@@ -439,7 +441,10 @@ build_depthstencil_shader(struct nir_shader **out_vs, struct nir_shader **out_fs
        vs_out_layer->data.location = VARYING_SLOT_LAYER;
        vs_out_layer->data.interpolation = INTERP_MODE_FLAT;
        nir_ssa_def *inst_id = nir_load_system_value(&vs_b, nir_intrinsic_load_instance_id, 0);
-       nir_store_var(&vs_b, vs_out_layer, inst_id, 0x1);
+       nir_ssa_def *base_instance = nir_load_system_value(&vs_b, nir_intrinsic_load_base_instance, 0);
+
+       nir_ssa_def *layer_id = nir_iadd(&vs_b, inst_id, base_instance);
+       nir_store_var(&vs_b, vs_out_layer, layer_id, 0x1);
 
        *out_vs = vs_b.shader;
        *out_fs = fs_b.shader;
@@ -455,7 +460,7 @@ create_depthstencil_renderpass(struct radv_device *device,
                                               .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
                                                       .attachmentCount = 1,
                                                       .pAttachments = &(VkAttachmentDescription) {
-                                                      .format = VK_FORMAT_UNDEFINED,
+                                                      .format = VK_FORMAT_D32_SFLOAT_S8_UINT,
                                                       .samples = samples,
                                                       .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
                                                       .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
@@ -540,10 +545,14 @@ create_depthstencil_pipeline(struct radv_device *device,
        return result;
 }
 
-static bool depth_view_can_fast_clear(const struct radv_image_view *iview,
+static bool depth_view_can_fast_clear(struct radv_cmd_buffer *cmd_buffer,
+                                     const struct radv_image_view *iview,
                                      VkImageLayout layout,
                                      const VkClearRect *clear_rect)
 {
+       uint32_t queue_mask = radv_image_queue_family_mask(iview->image,
+                                                          cmd_buffer->queue_family_index,
+                                                          cmd_buffer->queue_family_index);
        if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
            clear_rect->rect.extent.width != iview->extent.width ||
            clear_rect->rect.extent.height != iview->extent.height)
@@ -551,14 +560,15 @@ static bool depth_view_can_fast_clear(const struct radv_image_view *iview,
        if (iview->image->surface.htile_size &&
            iview->base_mip == 0 &&
            iview->base_layer == 0 &&
-           radv_layout_is_htile_compressed(iview->image, layout) &&
+           radv_layout_is_htile_compressed(iview->image, layout, queue_mask) &&
            !radv_image_extent_compare(iview->image, &iview->extent))
                return true;
        return false;
 }
 
 static struct radv_pipeline *
-pick_depthstencil_pipeline(struct radv_meta_state *meta_state,
+pick_depthstencil_pipeline(struct radv_cmd_buffer *cmd_buffer,
+                          struct radv_meta_state *meta_state,
                           const struct radv_image_view *iview,
                           int samples_log2,
                           VkImageAspectFlags aspects,
@@ -566,7 +576,7 @@ pick_depthstencil_pipeline(struct radv_meta_state *meta_state,
                           const VkClearRect *clear_rect,
                           VkClearDepthStencilValue clear_value)
 {
-       bool fast = depth_view_can_fast_clear(iview, layout, clear_rect);
+       bool fast = depth_view_can_fast_clear(cmd_buffer, iview, layout, clear_rect);
        int index = DEPTH_CLEAR_SLOW;
 
        if (fast) {
@@ -622,7 +632,8 @@ emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer,
                                                  clear_value.stencil);
        }
 
-       struct radv_pipeline *pipeline = pick_depthstencil_pipeline(meta_state,
+       struct radv_pipeline *pipeline = pick_depthstencil_pipeline(cmd_buffer,
+                                                                   meta_state,
                                                                    iview,
                                                                    samples_log2,
                                                                    aspects,
@@ -634,7 +645,7 @@ emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer,
                                           radv_pipeline_to_handle(pipeline));
        }
 
-       if (depth_view_can_fast_clear(iview, subpass->depth_stencil_attachment.layout, clear_rect))
+       if (depth_view_can_fast_clear(cmd_buffer, iview, subpass->depth_stencil_attachment.layout, clear_rect))
                radv_set_depth_clear_regs(cmd_buffer, iview->image, clear_value, aspects);
 
        radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
@@ -648,9 +659,96 @@ emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer,
 
        radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
 
-       radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, 0);
+       radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, clear_rect->baseArrayLayer);
 }
 
+static bool
+emit_fast_htile_clear(struct radv_cmd_buffer *cmd_buffer,
+                     const VkClearAttachment *clear_att,
+                     const VkClearRect *clear_rect,
+                     enum radv_cmd_flush_bits *pre_flush,
+                     enum radv_cmd_flush_bits *post_flush)
+{
+       const struct radv_subpass *subpass = cmd_buffer->state.subpass;
+       const uint32_t pass_att = subpass->depth_stencil_attachment.attachment;
+       VkImageLayout image_layout = subpass->depth_stencil_attachment.layout;
+       const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
+       const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
+       VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
+       VkImageAspectFlags aspects = clear_att->aspectMask;
+       uint32_t clear_word;
+
+       if (!iview->image->surface.htile_size)
+               return false;
+
+       if (cmd_buffer->device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
+               return false;
+
+       if (!radv_layout_is_htile_compressed(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
+               goto fail;
+
+       /* don't fast clear 3D */
+       if (iview->image->type == VK_IMAGE_TYPE_3D)
+               goto fail;
+
+       /* all layers are bound */
+       if (iview->base_layer > 0)
+               goto fail;
+       if (iview->image->info.array_size != iview->layer_count)
+               goto fail;
+
+       if (iview->image->info.levels > 1)
+               goto fail;
+
+       if (!radv_image_extent_compare(iview->image, &iview->extent))
+               goto fail;
+
+       if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
+           clear_rect->rect.extent.width != iview->image->info.width ||
+           clear_rect->rect.extent.height != iview->image->info.height)
+               goto fail;
+
+       if (clear_rect->baseArrayLayer != 0)
+               goto fail;
+       if (clear_rect->layerCount != iview->image->info.array_size)
+               goto fail;
+
+       if ((clear_value.depth != 0.0 && clear_value.depth != 1.0) || !(aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
+               goto fail;
+
+       if (vk_format_aspects(iview->image->vk_format) & VK_IMAGE_ASPECT_STENCIL_BIT) {
+               if (clear_value.stencil != 0 || !(aspects & VK_IMAGE_ASPECT_STENCIL_BIT))
+                       goto fail;
+               clear_word = clear_value.depth ? 0xfffc0000 : 0;
+       } else
+               clear_word = clear_value.depth ? 0xfffffff0 : 0;
+
+       if (pre_flush) {
+               cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_DB |
+                                                RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) & ~ *pre_flush;
+               *pre_flush |= cmd_buffer->state.flush_bits;
+       } else
+               cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
+                                               RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
+
+       radv_fill_buffer(cmd_buffer, iview->image->bo,
+                        iview->image->offset + iview->image->htile_offset,
+                        iview->image->surface.htile_size, clear_word);
+
+
+       radv_set_depth_clear_regs(cmd_buffer, iview->image, clear_value, aspects);
+       if (post_flush)
+               *post_flush |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
+                              RADV_CMD_FLAG_INV_VMEM_L1 |
+                              RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
+       else
+               cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
+                                               RADV_CMD_FLAG_INV_VMEM_L1 |
+                                               RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
+       return true;
+fail:
+       return false;
+}
 
 static VkFormat pipeline_formats[] = {
        VK_FORMAT_R8G8B8A8_UNORM,
@@ -763,6 +861,83 @@ fail:
        return res;
 }
 
+static void vi_get_fast_clear_parameters(VkFormat format,
+                                        const VkClearColorValue *clear_value,
+                                        uint32_t* reset_value,
+                                        bool *can_avoid_fast_clear_elim)
+{
+       bool values[4] = {};
+       int extra_channel;
+       bool main_value = false;
+       bool extra_value = false;
+       int i;
+       *can_avoid_fast_clear_elim = false;
+
+       *reset_value = 0x20202020U;
+
+       const struct vk_format_description *desc = vk_format_description(format);
+       if (format == VK_FORMAT_B10G11R11_UFLOAT_PACK32 ||
+           format == VK_FORMAT_R5G6B5_UNORM_PACK16 ||
+           format == VK_FORMAT_B5G6R5_UNORM_PACK16)
+               extra_channel = -1;
+       else if (desc->layout == VK_FORMAT_LAYOUT_PLAIN) {
+               if (radv_translate_colorswap(format, false) <= 1)
+                       extra_channel = desc->nr_channels - 1;
+               else
+                       extra_channel = 0;
+       } else
+               return;
+
+       for (i = 0; i < 4; i++) {
+               int index = desc->swizzle[i] - VK_SWIZZLE_X;
+               if (desc->swizzle[i] < VK_SWIZZLE_X ||
+                   desc->swizzle[i] > VK_SWIZZLE_W)
+                       continue;
+
+               if (desc->channel[i].pure_integer &&
+                   desc->channel[i].type == VK_FORMAT_TYPE_SIGNED) {
+                       /* Use the maximum value for clamping the clear color. */
+                       int max = u_bit_consecutive(0, desc->channel[i].size - 1);
+
+                       values[i] = clear_value->int32[i] != 0;
+                       if (clear_value->int32[i] != 0 && MIN2(clear_value->int32[i], max) != max)
+                               return;
+               } else if (desc->channel[i].pure_integer &&
+                          desc->channel[i].type == VK_FORMAT_TYPE_UNSIGNED) {
+                       /* Use the maximum value for clamping the clear color. */
+                       unsigned max = u_bit_consecutive(0, desc->channel[i].size);
+
+                       values[i] = clear_value->uint32[i] != 0U;
+                       if (clear_value->uint32[i] != 0U && MIN2(clear_value->uint32[i], max) != max)
+                               return;
+               } else {
+                       values[i] = clear_value->float32[i] != 0.0F;
+                       if (clear_value->float32[i] != 0.0F && clear_value->float32[i] != 1.0F)
+                               return;
+               }
+
+               if (index == extra_channel)
+                       extra_value = values[i];
+               else
+                       main_value = values[i];
+       }
+
+       for (int i = 0; i < 4; ++i)
+               if (values[i] != main_value &&
+                   desc->swizzle[i] - VK_SWIZZLE_X != extra_channel &&
+                   desc->swizzle[i] >= VK_SWIZZLE_X &&
+                   desc->swizzle[i] <= VK_SWIZZLE_W)
+                       return;
+
+       *can_avoid_fast_clear_elim = true;
+       if (main_value)
+               *reset_value |= 0x80808080U;
+
+       if (extra_value)
+               *reset_value |= 0x40404040U;
+       return;
+}
+
 static bool
 emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
                      const VkClearAttachment *clear_att,
@@ -788,8 +963,6 @@ emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
 
        if (!radv_layout_can_fast_clear(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
                goto fail;
-       if (vk_format_get_blocksizebits(iview->image->vk_format) > 64)
-               goto fail;
 
        /* don't fast clear 3D */
        if (iview->image->type == VK_IMAGE_TYPE_3D)
@@ -804,7 +977,7 @@ emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
        if (iview->image->info.levels > 1)
                goto fail;
 
-       if (iview->image->surface.level[0].mode < RADEON_SURF_MODE_1D)
+       if (iview->image->surface.u.legacy.level[0].mode < RADEON_SURF_MODE_1D)
                goto fail;
        if (!radv_image_extent_compare(iview->image, &iview->extent))
                goto fail;
@@ -819,6 +992,11 @@ emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
        if (clear_rect->layerCount != iview->image->info.array_size)
                goto fail;
 
+       /* RB+ doesn't work with CMASK fast clear on Stoney. */
+       if (!iview->image->surface.dcc_size &&
+           cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY)
+               goto fail;
+
        /* DCC */
        ret = radv_format_pack_clear_color(iview->image->vk_format,
                                           clear_color, &clear_value);
@@ -834,10 +1012,23 @@ emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
                                                RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
        /* clear cmask buffer */
        if (iview->image->surface.dcc_size) {
+               uint32_t reset_value;
+               bool can_avoid_fast_clear_elim;
+               vi_get_fast_clear_parameters(iview->image->vk_format,
+                                            &clear_value, &reset_value,
+                                            &can_avoid_fast_clear_elim);
+
                radv_fill_buffer(cmd_buffer, iview->image->bo,
                                 iview->image->offset + iview->image->dcc_offset,
-                                iview->image->surface.dcc_size, 0x20202020);
+                                iview->image->surface.dcc_size, reset_value);
+               radv_set_dcc_need_cmask_elim_pred(cmd_buffer, iview->image,
+                                                 !can_avoid_fast_clear_elim);
        } else {
+
+               if (iview->image->surface.bpe > 8) {
+                       /* 128 bit formats not supported */
+                       return false;
+               }
                radv_fill_buffer(cmd_buffer, iview->image->bo,
                                 iview->image->offset + iview->image->cmask.offset,
                                 iview->image->cmask.size, 0);
@@ -877,7 +1068,9 @@ emit_clear(struct radv_cmd_buffer *cmd_buffer,
        } else {
                assert(clear_att->aspectMask & (VK_IMAGE_ASPECT_DEPTH_BIT |
                                                VK_IMAGE_ASPECT_STENCIL_BIT));
-               emit_depthstencil_clear(cmd_buffer, clear_att, clear_rect);
+               if (!emit_fast_htile_clear(cmd_buffer, clear_att, clear_rect,
+                                          pre_flush, post_flush))
+                       emit_depthstencil_clear(cmd_buffer, clear_att, clear_rect);
        }
 }
 
@@ -892,7 +1085,8 @@ subpass_needs_clear(const struct radv_cmd_buffer *cmd_buffer)
        ds = cmd_state->subpass->depth_stencil_attachment.attachment;
        for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
                uint32_t a = cmd_state->subpass->color_attachments[i].attachment;
-               if (cmd_state->attachments[a].pending_clear_aspects) {
+               if (a != VK_ATTACHMENT_UNUSED &&
+                   cmd_state->attachments[a].pending_clear_aspects) {
                        return true;
                }
        }
@@ -932,7 +1126,8 @@ radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer)
        for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
                uint32_t a = cmd_state->subpass->color_attachments[i].attachment;
 
-               if (!cmd_state->attachments[a].pending_clear_aspects)
+               if (a == VK_ATTACHMENT_UNUSED ||
+                   !cmd_state->attachments[a].pending_clear_aspects)
                        continue;
 
                assert(cmd_state->attachments[a].pending_clear_aspects ==
@@ -992,8 +1187,7 @@ radv_clear_image_layer(struct radv_cmd_buffer *cmd_buffer,
                                             .baseArrayLayer = range->baseArrayLayer + layer,
                                             .layerCount = 1
                                     },
-                            },
-                            cmd_buffer, VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT);
+                            });
 
        VkFramebuffer fb;
        radv_CreateFramebuffer(device_h,