radv: do not decompress levels without DCC with the graphics path

[mesa.git] / src / amd / vulkan / radv_meta_fast_clear.c

diff --git a/src/amd/vulkan/radv_meta_fast_clear.c b/src/amd/vulkan/radv_meta_fast_clear.c
index feeb0a1b7edc502fca53fc3356db86763ebf853b..12fea8292c0e2157b8ee14d40c5485227182a000 100644 (file)
--- a/src/amd/vulkan/radv_meta_fast_clear.c
+++ b/src/amd/vulkan/radv_meta_fast_clear.c
@@ -639,9 +639,18 @@ static void
 radv_process_color_image(struct radv_cmd_buffer *cmd_buffer,
                         struct radv_image *image,
                         const VkImageSubresourceRange *subresourceRange,
-                        VkPipeline *pipeline)
+                        bool decompress_dcc)
 {
        struct radv_meta_saved_state saved_state;
+       VkPipeline *pipeline;
+
+       if (decompress_dcc && radv_dcc_enabled(image, subresourceRange->baseMipLevel)) {
+               pipeline = &cmd_buffer->device->meta_state.fast_clear_flush.dcc_decompress_pipeline;
+       } else if (radv_image_has_fmask(image)) {
+               pipeline = &cmd_buffer->device->meta_state.fast_clear_flush.fmask_decompress_pipeline;
+       } else {
+               pipeline = &cmd_buffer->device->meta_state.fast_clear_flush.cmask_eliminate_pipeline;
+       }
 
        if (!*pipeline) {
                VkResult ret;
@@ -661,11 +670,15 @@ radv_process_color_image(struct radv_cmd_buffer *cmd_buffer,
                             VK_PIPELINE_BIND_POINT_GRAPHICS, *pipeline);
 
        for (uint32_t l = 0; l < radv_get_levelCount(image, subresourceRange); ++l) {
-               uint32_t width =
-                       radv_minify(image->info.width,
+               uint32_t width, height;
+
+               /* Do not decompress levels without DCC. */
+               if (!radv_dcc_enabled(image, subresourceRange->baseMipLevel + l))
+                       continue;
+
+               width = radv_minify(image->info.width,
                                    subresourceRange->baseMipLevel + l);
-               uint32_t height =
-                       radv_minify(image->info.height,
+               height = radv_minify(image->info.height,
                                    subresourceRange->baseMipLevel + l);
 
                radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1,
@@ -700,19 +713,10 @@ radv_emit_color_decompress(struct radv_cmd_buffer *cmd_buffer,
                            bool decompress_dcc)
 {
        bool old_predicating = false;
-       VkPipeline *pipeline;
 
        assert(cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL);
 
-       if (decompress_dcc && radv_image_has_dcc(image)) {
-               pipeline = &cmd_buffer->device->meta_state.fast_clear_flush.dcc_decompress_pipeline;
-       } else if (radv_image_has_fmask(image)) {
-               pipeline = &cmd_buffer->device->meta_state.fast_clear_flush.fmask_decompress_pipeline;
-       } else {
-               pipeline = &cmd_buffer->device->meta_state.fast_clear_flush.cmask_eliminate_pipeline;
-       }
-
-       if (radv_image_has_dcc(image)) {
+       if (radv_dcc_enabled(image, subresourceRange->baseMipLevel)) {
                uint64_t pred_offset = decompress_dcc ? image->dcc_pred_offset :
                                                        image->fce_pred_offset;
                pred_offset += 8 * subresourceRange->baseMipLevel;
@@ -723,9 +727,10 @@ radv_emit_color_decompress(struct radv_cmd_buffer *cmd_buffer,
                cmd_buffer->state.predicating = true;
        }
 
-       radv_process_color_image(cmd_buffer, image, subresourceRange, pipeline);
+       radv_process_color_image(cmd_buffer, image, subresourceRange,
+                                decompress_dcc);
 
-       if (radv_image_has_dcc(image)) {
+       if (radv_dcc_enabled(image, subresourceRange->baseMipLevel)) {
                uint64_t pred_offset = decompress_dcc ? image->dcc_pred_offset :
                                                        image->fce_pred_offset;
                pred_offset += 8 * subresourceRange->baseMipLevel;
@@ -742,7 +747,7 @@ radv_emit_color_decompress(struct radv_cmd_buffer *cmd_buffer,
                }
        }
 
-       if (radv_image_has_dcc(image)) {
+       if (radv_dcc_enabled(image, subresourceRange->baseMipLevel)) {
                /* Clear the image's fast-clear eliminate predicate because
                 * FMASK and DCC also imply a fast-clear eliminate.
                 */
@@ -801,6 +806,11 @@ radv_decompress_dcc_compute(struct radv_cmd_buffer *cmd_buffer,
                             device->meta_state.fast_clear_flush.dcc_decompress_compute_pipeline);
 
        for (uint32_t l = 0; l < radv_get_levelCount(image, subresourceRange); l++) {
+
+               /* Do not decompress levels without DCC. */
+               if (!radv_dcc_enabled(image, subresourceRange->baseMipLevel + l))
+                       continue;
+
                radv_image_view_init(&iview, cmd_buffer->device,
                                     &(VkImageViewCreateInfo) {
                                             .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,