radv: add radv_clear_{cmask,dcc} helpers

[mesa.git] / src / amd / vulkan / radv_meta_fast_clear.c

diff --git a/src/amd/vulkan/radv_meta_fast_clear.c b/src/amd/vulkan/radv_meta_fast_clear.c
index 98e8f6ac18a2e558e872207d6c076f6b2a713cb3..928062b5abc965faa1026851ddb1a3e8e8b10fcf 100644 (file)
--- a/src/amd/vulkan/radv_meta_fast_clear.c
+++ b/src/amd/vulkan/radv_meta_fast_clear.c
@@ -90,7 +90,7 @@ build_dcc_decompress_compute_shader(struct radv_device *dev)
        nir_builder_instr_insert(&b, &bar->instr);
 
        nir_ssa_def *outval = &tex->dest.ssa;
-       nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_store);
+       nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_var_store);
        store->src[0] = nir_src_for_ssa(global_id);
        store->src[1] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32));
        store->src[2] = nir_src_for_ssa(outval);
@@ -194,8 +194,8 @@ create_pass(struct radv_device *device)
        attachment.samples = 1;
        attachment.loadOp = VK_ATTACHMENT_LOAD_OP_LOAD;
        attachment.storeOp = VK_ATTACHMENT_STORE_OP_STORE;
-       attachment.initialLayout = VK_IMAGE_LAYOUT_GENERAL;
-       attachment.finalLayout = VK_IMAGE_LAYOUT_GENERAL;
+       attachment.initialLayout = VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL;
+       attachment.finalLayout = VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL;
 
        result = radv_CreateRenderPass(device_h,
                                       &(VkRenderPassCreateInfo) {
@@ -210,7 +210,7 @@ create_pass(struct radv_device *device)
                                                       .pColorAttachments = (VkAttachmentReference[]) {
                                                               {
                                                                       .attachment = 0,
-                                                                      .layout = VK_IMAGE_LAYOUT_GENERAL,
+                                                                      .layout = VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL,
                                                               },
                                                       },
                                                       .pResolveAttachments = NULL,
@@ -771,9 +771,7 @@ radv_decompress_dcc_compute(struct radv_cmd_buffer *cmd_buffer,
        state->flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
                             RADV_CMD_FLAG_INV_VMEM_L1;
 
-       state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
-                                             image->offset + image->dcc_offset,
-                                             image->surface.dcc_size, 0xffffffff);
+       state->flush_bits |= radv_clear_dcc(cmd_buffer, image, 0xffffffff);
 
        state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
                             RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;