radv: Fix memory allocation failure path in compute resolve init.
[mesa.git] / src / amd / vulkan / radv_meta_resolve_cs.c
index 7a38b876b2f886c13cc23659d95e23ea3d8b6b00..519e2a5f4283c5faf398d9f357550abf85a7508a 100644 (file)
 #include "sid.h"
 #include "vk_format.h"
 
+static nir_ssa_def *radv_meta_build_resolve_srgb_conversion(nir_builder *b,
+                                                           nir_ssa_def *input)
+{
+       nir_const_value v;
+       unsigned i;
+       v.u32[0] = 0x3b4d2e1c; // 0.00313080009
+
+       nir_ssa_def *cmp[3];
+       for (i = 0; i < 3; i++)
+               cmp[i] = nir_flt(b, nir_channel(b, input, i),
+                                nir_build_imm(b, 1, 32, v));
+
+       nir_ssa_def *ltvals[3];
+       v.f32[0] = 12.92;
+       for (i = 0; i < 3; i++)
+               ltvals[i] = nir_fmul(b, nir_channel(b, input, i),
+                                    nir_build_imm(b, 1, 32, v));
+
+       nir_ssa_def *gtvals[3];
+
+       for (i = 0; i < 3; i++) {
+               v.f32[0] = 1.0/2.4;
+               gtvals[i] = nir_fpow(b, nir_channel(b, input, i),
+                                    nir_build_imm(b, 1, 32, v));
+               v.f32[0] = 1.055;
+               gtvals[i] = nir_fmul(b, gtvals[i],
+                                    nir_build_imm(b, 1, 32, v));
+               v.f32[0] = 0.055;
+               gtvals[i] = nir_fsub(b, gtvals[i],
+                                    nir_build_imm(b, 1, 32, v));
+       }
+
+       nir_ssa_def *comp[4];
+       for (i = 0; i < 3; i++)
+               comp[i] = nir_bcsel(b, cmp[i], ltvals[i], gtvals[i]);
+       comp[3] = nir_channels(b, input, 1 << 3);
+       return nir_vec(b, comp, 4);
+}
+
 static nir_shader *
 build_resolve_compute_shader(struct radv_device *dev, bool is_integer, bool is_srgb, int samples)
 {
@@ -46,10 +85,10 @@ build_resolve_compute_shader(struct radv_device *dev, bool is_integer, bool is_s
                                                             GLSL_TYPE_FLOAT);
        snprintf(name, 64, "meta_resolve_cs-%d-%s", samples, is_integer ? "int" : (is_srgb ? "srgb" : "float"));
        nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL);
-       b.shader->info->name = ralloc_strdup(b.shader, name);
-       b.shader->info->cs.local_size[0] = 16;
-       b.shader->info->cs.local_size[1] = 16;
-       b.shader->info->cs.local_size[2] = 1;
+       b.shader->info.name = ralloc_strdup(b.shader, name);
+       b.shader->info.cs.local_size[0] = 16;
+       b.shader->info.cs.local_size[1] = 16;
+       b.shader->info.cs.local_size[2] = 1;
 
        nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform,
                                                      sampler_type, "s_tex");
@@ -63,19 +102,23 @@ build_resolve_compute_shader(struct radv_device *dev, bool is_integer, bool is_s
        nir_ssa_def *invoc_id = nir_load_system_value(&b, nir_intrinsic_load_local_invocation_id, 0);
        nir_ssa_def *wg_id = nir_load_system_value(&b, nir_intrinsic_load_work_group_id, 0);
        nir_ssa_def *block_size = nir_imm_ivec4(&b,
-                                               b.shader->info->cs.local_size[0],
-                                               b.shader->info->cs.local_size[1],
-                                               b.shader->info->cs.local_size[2], 0);
+                                               b.shader->info.cs.local_size[0],
+                                               b.shader->info.cs.local_size[1],
+                                               b.shader->info.cs.local_size[2], 0);
 
        nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
 
        nir_intrinsic_instr *src_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
+       nir_intrinsic_set_base(src_offset, 0);
+       nir_intrinsic_set_range(src_offset, 16);
        src_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
        src_offset->num_components = 2;
        nir_ssa_dest_init(&src_offset->instr, &src_offset->dest, 2, 32, "src_offset");
        nir_builder_instr_insert(&b, &src_offset->instr);
 
        nir_intrinsic_instr *dst_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
+       nir_intrinsic_set_base(dst_offset, 0);
+       nir_intrinsic_set_range(dst_offset, 16);
        dst_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 8));
        dst_offset->num_components = 2;
        nir_ssa_dest_init(&dst_offset->instr, &dst_offset->dest, 2, 32, "dst_offset");
@@ -84,10 +127,13 @@ build_resolve_compute_shader(struct radv_device *dev, bool is_integer, bool is_s
        nir_ssa_def *img_coord = nir_channels(&b, nir_iadd(&b, global_id, &src_offset->dest.ssa), 0x3);
        nir_variable *color = nir_local_variable_create(b.impl, glsl_vec4_type(), "color");
 
-       radv_meta_build_resolve_shader_core(&b, is_integer, is_srgb, samples,
-                                           input_img, color, img_coord);
+       radv_meta_build_resolve_shader_core(&b, is_integer, samples, input_img,
+                                           color, img_coord);
 
        nir_ssa_def *outval = nir_load_var(&b, color);
+       if (is_srgb)
+               outval = radv_meta_build_resolve_srgb_conversion(&b, outval);
+
        nir_ssa_def *coord = nir_iadd(&b, global_id, &dst_offset->dest.ssa);
        nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_store);
        store->src[0] = nir_src_for_ssa(coord);
@@ -204,26 +250,34 @@ radv_device_init_meta_resolve_compute_state(struct radv_device *device)
 {
        struct radv_meta_state *state = &device->meta_state;
        VkResult res;
-       memset(&device->meta_state.resolve_compute, 0, sizeof(device->meta_state.resolve_compute));
 
        res = create_layout(device);
        if (res != VK_SUCCESS)
-               return res;
+               goto fail;
 
        for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; ++i) {
                uint32_t samples = 1 << i;
 
                res = create_resolve_pipeline(device, samples, false, false,
                                              &state->resolve_compute.rc[i].pipeline);
+               if (res != VK_SUCCESS)
+                       goto fail;
 
                res = create_resolve_pipeline(device, samples, true, false,
                                              &state->resolve_compute.rc[i].i_pipeline);
+               if (res != VK_SUCCESS)
+                       goto fail;
 
                res = create_resolve_pipeline(device, samples, false, true,
                                              &state->resolve_compute.rc[i].srgb_pipeline);
+               if (res != VK_SUCCESS)
+                       goto fail;
 
        }
 
+       return VK_SUCCESS;
+fail:
+       radv_device_finish_meta_resolve_compute_state(device);
        return res;
 }
 
@@ -306,10 +360,9 @@ emit_resolve(struct radv_cmd_buffer *cmd_buffer,
                pipeline = device->meta_state.resolve_compute.rc[samples_log2].srgb_pipeline;
        else
                pipeline = device->meta_state.resolve_compute.rc[samples_log2].pipeline;
-       if (cmd_buffer->state.compute_pipeline != radv_pipeline_from_handle(pipeline)) {
-               radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
-                                    VK_PIPELINE_BIND_POINT_COMPUTE, pipeline);
-       }
+
+       radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
+                            VK_PIPELINE_BIND_POINT_COMPUTE, pipeline);
 
        unsigned push_constants[4] = {
                src_offset->x,
@@ -333,7 +386,7 @@ void radv_meta_resolve_compute_image(struct radv_cmd_buffer *cmd_buffer,
                                     uint32_t region_count,
                                     const VkImageResolve *regions)
 {
-       struct radv_meta_saved_compute_state saved_state;
+       struct radv_meta_saved_state saved_state;
 
        for (uint32_t r = 0; r < region_count; ++r) {
                const VkImageResolve *region = &regions[r];
@@ -349,7 +402,10 @@ void radv_meta_resolve_compute_image(struct radv_cmd_buffer *cmd_buffer,
                radv_fast_clear_flush_image_inplace(cmd_buffer, src_image, &range);
        }
 
-       radv_meta_save_compute(&saved_state, cmd_buffer, 16);
+       radv_meta_save(&saved_state, cmd_buffer,
+                      RADV_META_SAVE_COMPUTE_PIPELINE |
+                      RADV_META_SAVE_CONSTANTS |
+                      RADV_META_SAVE_DESCRIPTORS);
 
        for (uint32_t r = 0; r < region_count; ++r) {
                const VkImageResolve *region = &regions[r];
@@ -390,8 +446,7 @@ void radv_meta_resolve_compute_image(struct radv_cmd_buffer *cmd_buffer,
                                                             .baseArrayLayer = src_base_layer + layer,
                                                             .layerCount = 1,
                                                     },
-                                            },
-                                            cmd_buffer, VK_IMAGE_USAGE_SAMPLED_BIT);
+                                            });
 
                        struct radv_image_view dest_iview;
                        radv_image_view_init(&dest_iview, cmd_buffer->device,
@@ -399,7 +454,7 @@ void radv_meta_resolve_compute_image(struct radv_cmd_buffer *cmd_buffer,
                                                     .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
                                                             .image = radv_image_to_handle(dest_image),
                                                             .viewType = radv_meta_get_view_type(dest_image),
-                                                            .format = dest_image->vk_format,
+                                                            .format = vk_to_non_srgb_format(dest_image->vk_format),
                                                             .subresourceRange = {
                                                             .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
                                                             .baseMipLevel = region->dstSubresource.mipLevel,
@@ -407,8 +462,7 @@ void radv_meta_resolve_compute_image(struct radv_cmd_buffer *cmd_buffer,
                                                             .baseArrayLayer = dest_base_layer + layer,
                                                             .layerCount = 1,
                                                     },
-                                                            },
-                                            cmd_buffer, VK_IMAGE_USAGE_STORAGE_BIT);
+                                            });
 
                        emit_resolve(cmd_buffer,
                                     &src_iview,
@@ -418,5 +472,91 @@ void radv_meta_resolve_compute_image(struct radv_cmd_buffer *cmd_buffer,
                                     &(VkExtent2D) {extent.width, extent.height });
                }
        }
-       radv_meta_restore_compute(&saved_state, cmd_buffer, 16);
+       radv_meta_restore(&saved_state, cmd_buffer);
+}
+
+/**
+ * Emit any needed resolves for the current subpass.
+ */
+void
+radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer)
+{
+       struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
+       const struct radv_subpass *subpass = cmd_buffer->state.subpass;
+       struct radv_meta_saved_state saved_state;
+       /* FINISHME(perf): Skip clears for resolve attachments.
+        *
+        * From the Vulkan 1.0 spec:
+        *
+        *    If the first use of an attachment in a render pass is as a resolve
+        *    attachment, then the loadOp is effectively ignored as the resolve is
+        *    guaranteed to overwrite all pixels in the render area.
+        */
+
+       if (!subpass->has_resolve)
+               return;
+
+       /* Resolves happen before the end-of-subpass barriers get executed,
+        * so we have to make the attachment shader-readable */
+       cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
+                                       RADV_CMD_FLAG_FLUSH_AND_INV_CB |
+                                       RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
+                                       RADV_CMD_FLAG_INV_GLOBAL_L2 |
+                                       RADV_CMD_FLAG_INV_VMEM_L1;
+
+       for (uint32_t i = 0; i < subpass->color_count; ++i) {
+               VkAttachmentReference src_att = subpass->color_attachments[i];
+               VkAttachmentReference dest_att = subpass->resolve_attachments[i];
+
+               if (src_att.attachment == VK_ATTACHMENT_UNUSED ||
+                   dest_att.attachment == VK_ATTACHMENT_UNUSED)
+                       continue;
+
+               struct radv_image_view *src_iview = cmd_buffer->state.framebuffer->attachments[src_att.attachment].attachment;
+
+               VkImageSubresourceRange range;
+               range.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT;
+               range.baseMipLevel = 0;
+               range.levelCount = 1;
+               range.baseArrayLayer = 0;
+               range.layerCount = 1;
+               radv_fast_clear_flush_image_inplace(cmd_buffer, src_iview->image, &range);
+       }
+
+       radv_meta_save(&saved_state, cmd_buffer,
+                      RADV_META_SAVE_COMPUTE_PIPELINE |
+                      RADV_META_SAVE_CONSTANTS |
+                      RADV_META_SAVE_DESCRIPTORS);
+
+       for (uint32_t i = 0; i < subpass->color_count; ++i) {
+               VkAttachmentReference src_att = subpass->color_attachments[i];
+               VkAttachmentReference dest_att = subpass->resolve_attachments[i];
+               struct radv_image_view *src_iview = cmd_buffer->state.framebuffer->attachments[src_att.attachment].attachment;
+               struct radv_image_view *dst_iview = cmd_buffer->state.framebuffer->attachments[dest_att.attachment].attachment;
+               if (dest_att.attachment == VK_ATTACHMENT_UNUSED)
+                       continue;
+
+               emit_resolve(cmd_buffer,
+                            src_iview,
+                            dst_iview,
+                            &(VkOffset2D) { 0, 0 },
+                            &(VkOffset2D) { 0, 0 },
+                            &(VkExtent2D) { fb->width, fb->height });
+       }
+
+       radv_meta_restore(&saved_state, cmd_buffer);
+
+       for (uint32_t i = 0; i < subpass->color_count; ++i) {
+               VkAttachmentReference dest_att = subpass->resolve_attachments[i];
+               struct radv_image *dst_img = cmd_buffer->state.framebuffer->attachments[dest_att.attachment].attachment->image;
+               if (dest_att.attachment == VK_ATTACHMENT_UNUSED)
+                       continue;
+               VkImageSubresourceRange range;
+               range.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT;
+               range.baseMipLevel = 0;
+               range.levelCount = 1;
+               range.baseArrayLayer = 0;
+               range.layerCount = 1;
+               radv_fast_clear_flush_image_inplace(cmd_buffer, dst_img, &range);
+       }
 }