radv: reduce radv_shader_variant struct size.

[mesa.git] / src / amd / vulkan / radv_meta_resolve_cs.c

diff --git a/src/amd/vulkan/radv_meta_resolve_cs.c b/src/amd/vulkan/radv_meta_resolve_cs.c
index 832ae7b8c99d1f2f89d61dc78549d5821d978ac4..ce02884d2d6b6906ee39776756789c3aaaf23685 100644 (file)
--- a/src/amd/vulkan/radv_meta_resolve_cs.c
+++ b/src/amd/vulkan/radv_meta_resolve_cs.c
@@ -31,6 +31,45 @@
 #include "sid.h"
 #include "vk_format.h"
 
+static nir_ssa_def *radv_meta_build_resolve_srgb_conversion(nir_builder *b,
+                                                           nir_ssa_def *input)
+{
+       nir_const_value v;
+       unsigned i;
+       v.u32[0] = 0x3b4d2e1c; // 0.00313080009
+
+       nir_ssa_def *cmp[3];
+       for (i = 0; i < 3; i++)
+               cmp[i] = nir_flt(b, nir_channel(b, input, i),
+                                nir_build_imm(b, 1, 32, v));
+
+       nir_ssa_def *ltvals[3];
+       v.f32[0] = 12.92;
+       for (i = 0; i < 3; i++)
+               ltvals[i] = nir_fmul(b, nir_channel(b, input, i),
+                                    nir_build_imm(b, 1, 32, v));
+
+       nir_ssa_def *gtvals[3];
+
+       for (i = 0; i < 3; i++) {
+               v.f32[0] = 1.0/2.4;
+               gtvals[i] = nir_fpow(b, nir_channel(b, input, i),
+                                    nir_build_imm(b, 1, 32, v));
+               v.f32[0] = 1.055;
+               gtvals[i] = nir_fmul(b, gtvals[i],
+                                    nir_build_imm(b, 1, 32, v));
+               v.f32[0] = 0.055;
+               gtvals[i] = nir_fsub(b, gtvals[i],
+                                    nir_build_imm(b, 1, 32, v));
+       }
+
+       nir_ssa_def *comp[4];
+       for (i = 0; i < 3; i++)
+               comp[i] = nir_bcsel(b, cmp[i], ltvals[i], gtvals[i]);
+       comp[3] = nir_channels(b, input, 1 << 3);
+       return nir_vec(b, comp, 4);
+}
+
 static nir_shader *
 build_resolve_compute_shader(struct radv_device *dev, bool is_integer, bool is_srgb, int samples)
 {
@@ -88,10 +127,13 @@ build_resolve_compute_shader(struct radv_device *dev, bool is_integer, bool is_s
        nir_ssa_def *img_coord = nir_channels(&b, nir_iadd(&b, global_id, &src_offset->dest.ssa), 0x3);
        nir_variable *color = nir_local_variable_create(b.impl, glsl_vec4_type(), "color");
 
-       radv_meta_build_resolve_shader_core(&b, is_integer, is_srgb, samples,
-                                           input_img, color, img_coord);
+       radv_meta_build_resolve_shader_core(&b, is_integer, samples, input_img,
+                                           color, img_coord);
 
        nir_ssa_def *outval = nir_load_var(&b, color);
+       if (is_srgb)
+               outval = radv_meta_build_resolve_srgb_conversion(&b, outval);
+
        nir_ssa_def *coord = nir_iadd(&b, global_id, &dst_offset->dest.ssa);
        nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_store);
        store->src[0] = nir_src_for_ssa(coord);
@@ -479,21 +521,6 @@ radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer)
                if (dest_att.attachment == VK_ATTACHMENT_UNUSED)
                        continue;
 
-               struct radv_subpass resolve_subpass = {
-                       .color_count = 1,
-                       .color_attachments = (VkAttachmentReference[]) { dest_att },
-                       .depth_stencil_attachment = { .attachment = VK_ATTACHMENT_UNUSED },
-               };
-
-               radv_cmd_buffer_set_subpass(cmd_buffer, &resolve_subpass, false);
-
-               /* Subpass resolves must respect the render area. We can ignore the
-                * render area here because vkCmdBeginRenderPass set the render area
-                * with 3DSTATE_DRAWING_RECTANGLE.
-                *
-                * XXX(chadv): Does the hardware really respect
-                * 3DSTATE_DRAWING_RECTANGLE when draing a 3DPRIM_RECTLIST?
-                */
                emit_resolve(cmd_buffer,
                             src_iview,
                             dst_iview,