#include "radv_private.h"
#include "radv_shader.h"
#include "radv_shader_helper.h"
+#include "radv_shader_args.h"
#include "nir/nir.h"
#include <llvm-c/Core.h>
struct radv_shader_context {
struct ac_llvm_context ac;
- const struct radv_nir_compiler_options *options;
- struct radv_shader_variant_info *shader_info;
+ const struct nir_shader *shader;
struct ac_shader_abi abi;
+ const struct radv_shader_args *args;
+
+ gl_shader_stage stage;
unsigned max_workgroup_size;
LLVMContextRef context;
LLVMValueRef main_function;
- LLVMValueRef descriptor_sets[RADV_UD_MAX_SETS];
+ LLVMValueRef descriptor_sets[MAX_SETS];
+
LLVMValueRef ring_offsets;
- LLVMValueRef vertex_buffers;
LLVMValueRef rel_auto_id;
- LLVMValueRef vs_prim_id;
- LLVMValueRef es2gs_offset;
-
- LLVMValueRef oc_lds;
- LLVMValueRef merged_wave_info;
- LLVMValueRef tess_factor_offset;
- LLVMValueRef tes_rel_patch_id;
- LLVMValueRef tes_u;
- LLVMValueRef tes_v;
-
- /* HW GS */
- /* On gfx10:
- * - bits 0..10: ordered_wave_id
- * - bits 12..20: number of vertices in group
- * - bits 22..30: number of primitives in group
- */
- LLVMValueRef gs_tg_info;
- LLVMValueRef gs2vs_offset;
+
LLVMValueRef gs_wave_id;
LLVMValueRef gs_vtx_offset[6];
LLVMValueRef hs_ring_tess_offchip;
LLVMValueRef hs_ring_tess_factor;
- LLVMValueRef persp_sample, persp_center, persp_centroid;
- LLVMValueRef linear_sample, linear_center, linear_centroid;
-
- /* Streamout */
- LLVMValueRef streamout_buffers;
- LLVMValueRef streamout_write_idx;
- LLVMValueRef streamout_config;
- LLVMValueRef streamout_offset[4];
-
- gl_shader_stage stage;
-
LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
- uint64_t float16_shaded_mask;
- uint64_t input_mask;
uint64_t output_mask;
- bool is_gs_copy_shader;
LLVMValueRef gs_next_vertex[4];
LLVMValueRef gs_curprim_verts[4];
LLVMValueRef gs_generated_prims[4];
LLVMValueRef gs_ngg_emit;
LLVMValueRef gs_ngg_scratch;
- unsigned gs_max_out_vertices;
- unsigned gs_output_prim;
- unsigned tes_primitive_mode;
-
- uint32_t tcs_patch_outputs_read;
- uint64_t tcs_outputs_read;
- uint32_t tcs_vertices_per_patch;
uint32_t tcs_num_inputs;
uint32_t tcs_num_patches;
- uint32_t max_gsvs_emit_size;
- uint32_t gsvs_vertex_size;
LLVMValueRef vertexptr; /* GFX10 only */
};
-enum radeon_llvm_calling_convention {
- RADEON_LLVM_AMDGPU_VS = 87,
- RADEON_LLVM_AMDGPU_GS = 88,
- RADEON_LLVM_AMDGPU_PS = 89,
- RADEON_LLVM_AMDGPU_CS = 90,
- RADEON_LLVM_AMDGPU_HS = 93,
+struct radv_shader_output_values {
+ LLVMValueRef values[4];
+ unsigned slot_name;
+ unsigned slot_index;
+ unsigned usage_mask;
};
static inline struct radv_shader_context *
return container_of(abi, ctx, abi);
}
-struct ac_build_if_state
-{
- struct radv_shader_context *ctx;
- LLVMValueRef condition;
- LLVMBasicBlockRef entry_block;
- LLVMBasicBlockRef true_block;
- LLVMBasicBlockRef false_block;
- LLVMBasicBlockRef merge_block;
-};
-
-static LLVMBasicBlockRef
-ac_build_insert_new_block(struct radv_shader_context *ctx, const char *name)
-{
- LLVMBasicBlockRef current_block;
- LLVMBasicBlockRef next_block;
- LLVMBasicBlockRef new_block;
-
- /* get current basic block */
- current_block = LLVMGetInsertBlock(ctx->ac.builder);
-
- /* chqeck if there's another block after this one */
- next_block = LLVMGetNextBasicBlock(current_block);
- if (next_block) {
- /* insert the new block before the next block */
- new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
- }
- else {
- /* append new block after current block */
- LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
- new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
- }
- return new_block;
-}
-
-static void
-ac_nir_build_if(struct ac_build_if_state *ifthen,
- struct radv_shader_context *ctx,
- LLVMValueRef condition)
-{
- LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->ac.builder);
-
- memset(ifthen, 0, sizeof *ifthen);
- ifthen->ctx = ctx;
- ifthen->condition = condition;
- ifthen->entry_block = block;
-
- /* create endif/merge basic block for the phi functions */
- ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
-
- /* create/insert true_block before merge_block */
- ifthen->true_block =
- LLVMInsertBasicBlockInContext(ctx->context,
- ifthen->merge_block,
- "if-true-block");
-
- /* successive code goes into the true block */
- LLVMPositionBuilderAtEnd(ctx->ac.builder, ifthen->true_block);
-}
-
-/**
- * End a conditional.
- */
-static void
-ac_nir_build_endif(struct ac_build_if_state *ifthen)
-{
- LLVMBuilderRef builder = ifthen->ctx->ac.builder;
-
- /* Insert branch to the merge block from current block */
- LLVMBuildBr(builder, ifthen->merge_block);
-
- /*
- * Now patch in the various branch instructions.
- */
-
- /* Insert the conditional branch instruction at the end of entry_block */
- LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
- if (ifthen->false_block) {
- /* we have an else clause */
- LLVMBuildCondBr(builder, ifthen->condition,
- ifthen->true_block, ifthen->false_block);
- }
- else {
- /* no else clause */
- LLVMBuildCondBr(builder, ifthen->condition,
- ifthen->true_block, ifthen->merge_block);
- }
-
- /* Resume building code at end of the ifthen->merge_block */
- LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
-}
-
-
static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
{
switch (ctx->stage) {
case MESA_SHADER_TESS_CTRL:
- return ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
+ return ac_unpack_param(&ctx->ac,
+ ac_get_arg(&ctx->ac, ctx->args->ac.tcs_rel_ids),
+ 0, 8);
case MESA_SHADER_TESS_EVAL:
- return ctx->tes_rel_patch_id;
+ return ac_get_arg(&ctx->ac, ctx->args->tes_rel_patch_id);
break;
default:
unreachable("Illegal stage");
static unsigned
get_tcs_num_patches(struct radv_shader_context *ctx)
{
- unsigned num_tcs_input_cp = ctx->options->key.tcs.input_vertices;
- unsigned num_tcs_output_cp = ctx->tcs_vertices_per_patch;
+ unsigned num_tcs_input_cp = ctx->args->options->key.tcs.input_vertices;
+ unsigned num_tcs_output_cp = ctx->shader->info.tess.tcs_vertices_out;
uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
- uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
- uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
- uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
+ uint32_t input_patch_size = ctx->args->options->key.tcs.input_vertices * input_vertex_size;
+ uint32_t num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
+ uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->args->shader_info->tcs.patch_outputs_written);
uint32_t output_vertex_size = num_tcs_outputs * 16;
- uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
+ uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
unsigned num_patches;
unsigned hardware_lds_size;
*
* Test: dEQP-VK.tessellation.shader_input_output.barrier
*/
- if (ctx->options->chip_class >= GFX7 && ctx->options->family != CHIP_STONEY)
+ if (ctx->args->options->chip_class >= GFX7 && ctx->args->options->family != CHIP_STONEY)
hardware_lds_size = 65536;
num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
/* Make sure the output data fits in the offchip buffer */
- num_patches = MIN2(num_patches, (ctx->options->tess_offchip_block_dw_size * 4) / output_patch_size);
+ num_patches = MIN2(num_patches, (ctx->args->options->tess_offchip_block_dw_size * 4) / output_patch_size);
/* Not necessary for correctness, but improves performance. The
* specific value is taken from the proprietary driver.
*/
num_patches = MIN2(num_patches, 40);
/* GFX6 bug workaround - limit LS-HS threadgroups to only one wave. */
- if (ctx->options->chip_class == GFX6) {
+ if (ctx->args->options->chip_class == GFX6) {
unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
num_patches = MIN2(num_patches, one_wave);
}
static unsigned
calculate_tess_lds_size(struct radv_shader_context *ctx)
{
- unsigned num_tcs_input_cp = ctx->options->key.tcs.input_vertices;
+ unsigned num_tcs_input_cp = ctx->args->options->key.tcs.input_vertices;
unsigned num_tcs_output_cp;
unsigned num_tcs_outputs, num_tcs_patch_outputs;
unsigned input_vertex_size, output_vertex_size;
unsigned num_patches;
unsigned lds_size;
- num_tcs_output_cp = ctx->tcs_vertices_per_patch;
- num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
- num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
+ num_tcs_output_cp = ctx->shader->info.tess.tcs_vertices_out;
+ num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
+ num_tcs_patch_outputs = util_last_bit64(ctx->args->shader_info->tcs.patch_outputs_written);
input_vertex_size = ctx->tcs_num_inputs * 16;
output_vertex_size = num_tcs_outputs * 16;
static LLVMValueRef
get_tcs_in_patch_stride(struct radv_shader_context *ctx)
{
- assert (ctx->stage == MESA_SHADER_TESS_CTRL);
+ assert(ctx->stage == MESA_SHADER_TESS_CTRL);
uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
- uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
+ uint32_t input_patch_size = ctx->args->options->key.tcs.input_vertices * input_vertex_size;
input_patch_size /= 4;
return LLVMConstInt(ctx->ac.i32, input_patch_size, false);
static LLVMValueRef
get_tcs_out_patch_stride(struct radv_shader_context *ctx)
{
- uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
- uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
+ uint32_t num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
+ uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->args->shader_info->tcs.patch_outputs_written);
uint32_t output_vertex_size = num_tcs_outputs * 16;
- uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
+ uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
output_patch_size /= 4;
return LLVMConstInt(ctx->ac.i32, output_patch_size, false);
static LLVMValueRef
get_tcs_out_vertex_stride(struct radv_shader_context *ctx)
{
- uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
+ uint32_t num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
uint32_t output_vertex_size = num_tcs_outputs * 16;
output_vertex_size /= 4;
return LLVMConstInt(ctx->ac.i32, output_vertex_size, false);
{
assert (ctx->stage == MESA_SHADER_TESS_CTRL);
uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
- uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
+ uint32_t input_patch_size = ctx->args->options->key.tcs.input_vertices * input_vertex_size;
uint32_t output_patch0_offset = input_patch_size;
unsigned num_patches = ctx->tcs_num_patches;
{
assert (ctx->stage == MESA_SHADER_TESS_CTRL);
uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
- uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
+ uint32_t input_patch_size = ctx->args->options->key.tcs.input_vertices * input_vertex_size;
uint32_t output_patch0_offset = input_patch_size;
- uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
+ uint32_t num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
uint32_t output_vertex_size = num_tcs_outputs * 16;
- uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
+ uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
unsigned num_patches = ctx->tcs_num_patches;
output_patch0_offset *= num_patches;
patch0_patch_data_offset);
}
-#define MAX_ARGS 64
-struct arg_info {
- LLVMTypeRef types[MAX_ARGS];
- LLVMValueRef *assign[MAX_ARGS];
- uint8_t count;
- uint8_t sgpr_count;
- uint8_t num_sgprs_used;
- uint8_t num_vgprs_used;
-};
-
-enum ac_arg_regfile {
- ARG_SGPR,
- ARG_VGPR,
-};
-
-static void
-add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
- LLVMValueRef *param_ptr)
-{
- assert(info->count < MAX_ARGS);
-
- info->assign[info->count] = param_ptr;
- info->types[info->count] = type;
- info->count++;
-
- if (regfile == ARG_SGPR) {
- info->num_sgprs_used += ac_get_type_size(type) / 4;
- info->sgpr_count++;
- } else {
- assert(regfile == ARG_VGPR);
- info->num_vgprs_used += ac_get_type_size(type) / 4;
- }
-}
-
-static void assign_arguments(LLVMValueRef main_function,
- struct arg_info *info)
-{
- unsigned i;
- for (i = 0; i < info->count; i++) {
- if (info->assign[i])
- *info->assign[i] = LLVMGetParam(main_function, i);
- }
-}
-
static LLVMValueRef
-create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
- LLVMBuilderRef builder, LLVMTypeRef *return_types,
- unsigned num_return_elems,
- struct arg_info *args,
+create_llvm_function(struct ac_llvm_context *ctx, LLVMModuleRef module,
+ LLVMBuilderRef builder,
+ struct ac_shader_args *args,
+ enum ac_llvm_calling_convention convention,
unsigned max_workgroup_size,
const struct radv_nir_compiler_options *options)
{
- LLVMTypeRef main_function_type, ret_type;
- LLVMBasicBlockRef main_function_body;
-
- if (num_return_elems)
- ret_type = LLVMStructTypeInContext(ctx, return_types,
- num_return_elems, true);
- else
- ret_type = LLVMVoidTypeInContext(ctx);
-
- /* Setup the function */
- main_function_type =
- LLVMFunctionType(ret_type, args->types, args->count, 0);
LLVMValueRef main_function =
- LLVMAddFunction(module, "main", main_function_type);
- main_function_body =
- LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
- LLVMPositionBuilderAtEnd(builder, main_function_body);
-
- LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
- for (unsigned i = 0; i < args->sgpr_count; ++i) {
- LLVMValueRef P = LLVMGetParam(main_function, i);
-
- ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
-
- if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
- ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_NOALIAS);
- ac_add_attr_dereferenceable(P, UINT64_MAX);
- }
- }
+ ac_build_main(args, ctx, convention, "main", ctx->voidt, module);
if (options->address32_hi) {
ac_llvm_add_target_dep_function_attr(main_function,
ac_llvm_set_workgroup_size(main_function, max_workgroup_size);
- if (options->unsafe_math) {
- /* These were copied from some LLVM test. */
- LLVMAddTargetDependentFunctionAttr(main_function,
- "less-precise-fpmad",
- "true");
- LLVMAddTargetDependentFunctionAttr(main_function,
- "no-infs-fp-math",
- "true");
- LLVMAddTargetDependentFunctionAttr(main_function,
- "no-nans-fp-math",
- "true");
- LLVMAddTargetDependentFunctionAttr(main_function,
- "unsafe-fp-math",
- "true");
- LLVMAddTargetDependentFunctionAttr(main_function,
- "no-signed-zeros-fp-math",
- "true");
- }
return main_function;
}
}
static void
-set_loc_shader(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
+set_loc_shader(struct radv_shader_args *args, int idx, uint8_t *sgpr_idx,
uint8_t num_sgprs)
{
struct radv_userdata_info *ud_info =
- &ctx->shader_info->user_sgprs_locs.shader_data[idx];
+ &args->shader_info->user_sgprs_locs.shader_data[idx];
assert(ud_info);
set_loc(ud_info, sgpr_idx, num_sgprs);
}
static void
-set_loc_shader_ptr(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx)
+set_loc_shader_ptr(struct radv_shader_args *args, int idx, uint8_t *sgpr_idx)
{
bool use_32bit_pointers = idx != AC_UD_SCRATCH_RING_OFFSETS;
- set_loc_shader(ctx, idx, sgpr_idx, use_32bit_pointers ? 1 : 2);
+ set_loc_shader(args, idx, sgpr_idx, use_32bit_pointers ? 1 : 2);
}
static void
-set_loc_desc(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx)
+set_loc_desc(struct radv_shader_args *args, int idx, uint8_t *sgpr_idx)
{
struct radv_userdata_locations *locs =
- &ctx->shader_info->user_sgprs_locs;
+ &args->shader_info->user_sgprs_locs;
struct radv_userdata_info *ud_info = &locs->descriptor_sets[idx];
assert(ud_info);
uint8_t remaining_sgprs;
};
-static bool needs_view_index_sgpr(struct radv_shader_context *ctx,
+static bool needs_view_index_sgpr(struct radv_shader_args *args,
gl_shader_stage stage)
{
switch (stage) {
case MESA_SHADER_VERTEX:
- if (ctx->shader_info->info.needs_multiview_view_index ||
- (!ctx->options->key.vs_common_out.as_es && !ctx->options->key.vs_common_out.as_ls && ctx->options->key.has_multiview_view_index))
+ if (args->shader_info->needs_multiview_view_index ||
+ (!args->options->key.vs_common_out.as_es && !args->options->key.vs_common_out.as_ls && args->options->key.has_multiview_view_index))
return true;
break;
case MESA_SHADER_TESS_EVAL:
- if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.vs_common_out.as_es && ctx->options->key.has_multiview_view_index))
+ if (args->shader_info->needs_multiview_view_index || (!args->options->key.vs_common_out.as_es && args->options->key.has_multiview_view_index))
return true;
break;
case MESA_SHADER_GEOMETRY:
case MESA_SHADER_TESS_CTRL:
- if (ctx->shader_info->info.needs_multiview_view_index)
+ if (args->shader_info->needs_multiview_view_index)
return true;
break;
default:
}
static uint8_t
-count_vs_user_sgprs(struct radv_shader_context *ctx)
+count_vs_user_sgprs(struct radv_shader_args *args)
{
uint8_t count = 0;
- if (ctx->shader_info->info.vs.has_vertex_buffers)
+ if (args->shader_info->vs.has_vertex_buffers)
count++;
- count += ctx->shader_info->info.vs.needs_draw_id ? 3 : 2;
+ count += args->shader_info->vs.needs_draw_id ? 3 : 2;
return count;
}
-static void allocate_inline_push_consts(struct radv_shader_context *ctx,
+static void allocate_inline_push_consts(struct radv_shader_args *args,
struct user_sgpr_info *user_sgpr_info)
{
uint8_t remaining_sgprs = user_sgpr_info->remaining_sgprs;
/* Only supported if shaders use push constants. */
- if (ctx->shader_info->info.min_push_constant_used == UINT8_MAX)
+ if (args->shader_info->min_push_constant_used == UINT8_MAX)
return;
/* Only supported if shaders don't have indirect push constants. */
- if (ctx->shader_info->info.has_indirect_push_constants)
+ if (args->shader_info->has_indirect_push_constants)
return;
/* Only supported for 32-bit push constants. */
- if (!ctx->shader_info->info.has_only_32bit_push_constants)
+ if (!args->shader_info->has_only_32bit_push_constants)
return;
uint8_t num_push_consts =
- (ctx->shader_info->info.max_push_constant_used -
- ctx->shader_info->info.min_push_constant_used) / 4;
+ (args->shader_info->max_push_constant_used -
+ args->shader_info->min_push_constant_used) / 4;
/* Check if the number of user SGPRs is large enough. */
if (num_push_consts < remaining_sgprs) {
- ctx->shader_info->info.num_inline_push_consts = num_push_consts;
+ args->shader_info->num_inline_push_consts = num_push_consts;
} else {
- ctx->shader_info->info.num_inline_push_consts = remaining_sgprs;
+ args->shader_info->num_inline_push_consts = remaining_sgprs;
}
/* Clamp to the maximum number of allowed inlined push constants. */
- if (ctx->shader_info->info.num_inline_push_consts > AC_MAX_INLINE_PUSH_CONSTS)
- ctx->shader_info->info.num_inline_push_consts = AC_MAX_INLINE_PUSH_CONSTS;
+ if (args->shader_info->num_inline_push_consts > AC_MAX_INLINE_PUSH_CONSTS)
+ args->shader_info->num_inline_push_consts = AC_MAX_INLINE_PUSH_CONSTS;
- if (ctx->shader_info->info.num_inline_push_consts == num_push_consts &&
- !ctx->shader_info->info.loads_dynamic_offsets) {
+ if (args->shader_info->num_inline_push_consts == num_push_consts &&
+ !args->shader_info->loads_dynamic_offsets) {
/* Disable the default push constants path if all constants are
* inlined and if shaders don't use dynamic descriptors.
*/
- ctx->shader_info->info.loads_push_constants = false;
+ args->shader_info->loads_push_constants = false;
}
- ctx->shader_info->info.base_inline_push_consts =
- ctx->shader_info->info.min_push_constant_used / 4;
+ args->shader_info->base_inline_push_consts =
+ args->shader_info->min_push_constant_used / 4;
}
-static void allocate_user_sgprs(struct radv_shader_context *ctx,
+static void allocate_user_sgprs(struct radv_shader_args *args,
gl_shader_stage stage,
bool has_previous_stage,
gl_shader_stage previous_stage,
stage == MESA_SHADER_VERTEX ||
stage == MESA_SHADER_TESS_CTRL ||
stage == MESA_SHADER_TESS_EVAL ||
- ctx->is_gs_copy_shader)
+ args->is_gs_copy_shader)
user_sgpr_info->need_ring_offsets = true;
if (stage == MESA_SHADER_FRAGMENT &&
- ctx->shader_info->info.ps.needs_sample_positions)
+ args->shader_info->ps.needs_sample_positions)
user_sgpr_info->need_ring_offsets = true;
/* 2 user sgprs will nearly always be allocated for scratch/rings */
- if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
+ if (args->options->supports_spill || user_sgpr_info->need_ring_offsets) {
user_sgpr_count += 2;
}
switch (stage) {
case MESA_SHADER_COMPUTE:
- if (ctx->shader_info->info.cs.uses_grid_size)
+ if (args->shader_info->cs.uses_grid_size)
user_sgpr_count += 3;
break;
case MESA_SHADER_FRAGMENT:
- user_sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
+ user_sgpr_count += args->shader_info->ps.needs_sample_positions;
break;
case MESA_SHADER_VERTEX:
- if (!ctx->is_gs_copy_shader)
- user_sgpr_count += count_vs_user_sgprs(ctx);
+ if (!args->is_gs_copy_shader)
+ user_sgpr_count += count_vs_user_sgprs(args);
break;
case MESA_SHADER_TESS_CTRL:
if (has_previous_stage) {
if (previous_stage == MESA_SHADER_VERTEX)
- user_sgpr_count += count_vs_user_sgprs(ctx);
+ user_sgpr_count += count_vs_user_sgprs(args);
}
break;
case MESA_SHADER_TESS_EVAL:
case MESA_SHADER_GEOMETRY:
if (has_previous_stage) {
if (previous_stage == MESA_SHADER_VERTEX) {
- user_sgpr_count += count_vs_user_sgprs(ctx);
+ user_sgpr_count += count_vs_user_sgprs(args);
}
}
break;
if (needs_view_index)
user_sgpr_count++;
- if (ctx->shader_info->info.loads_push_constants)
+ if (args->shader_info->loads_push_constants)
user_sgpr_count++;
- if (ctx->streamout_buffers)
+ if (args->shader_info->so.num_outputs)
user_sgpr_count++;
- uint32_t available_sgprs = ctx->options->chip_class >= GFX9 && stage != MESA_SHADER_COMPUTE ? 32 : 16;
+ uint32_t available_sgprs = args->options->chip_class >= GFX9 && stage != MESA_SHADER_COMPUTE ? 32 : 16;
uint32_t remaining_sgprs = available_sgprs - user_sgpr_count;
uint32_t num_desc_set =
- util_bitcount(ctx->shader_info->info.desc_set_used_mask);
+ util_bitcount(args->shader_info->desc_set_used_mask);
if (remaining_sgprs < num_desc_set) {
user_sgpr_info->indirect_all_descriptor_sets = true;
user_sgpr_info->remaining_sgprs = remaining_sgprs - num_desc_set;
}
- allocate_inline_push_consts(ctx, user_sgpr_info);
+ allocate_inline_push_consts(args, user_sgpr_info);
}
static void
-declare_global_input_sgprs(struct radv_shader_context *ctx,
- const struct user_sgpr_info *user_sgpr_info,
- struct arg_info *args,
- LLVMValueRef *desc_sets)
+declare_global_input_sgprs(struct radv_shader_args *args,
+ const struct user_sgpr_info *user_sgpr_info)
{
- LLVMTypeRef type = ac_array_in_const32_addr_space(ctx->ac.i8);
-
/* 1 for each descriptor set */
if (!user_sgpr_info->indirect_all_descriptor_sets) {
- uint32_t mask = ctx->shader_info->info.desc_set_used_mask;
+ uint32_t mask = args->shader_info->desc_set_used_mask;
while (mask) {
int i = u_bit_scan(&mask);
- add_arg(args, ARG_SGPR, type, &ctx->descriptor_sets[i]);
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_CONST_PTR,
+ &args->descriptor_sets[i]);
}
} else {
- add_arg(args, ARG_SGPR, ac_array_in_const32_addr_space(type),
- desc_sets);
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_CONST_PTR_PTR,
+ &args->descriptor_sets[0]);
}
- if (ctx->shader_info->info.loads_push_constants) {
+ if (args->shader_info->loads_push_constants) {
/* 1 for push constants and dynamic descriptors */
- add_arg(args, ARG_SGPR, type, &ctx->abi.push_constants);
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_CONST_PTR,
+ &args->ac.push_constants);
}
- for (unsigned i = 0; i < ctx->shader_info->info.num_inline_push_consts; i++) {
- add_arg(args, ARG_SGPR, ctx->ac.i32,
- &ctx->abi.inline_push_consts[i]);
+ for (unsigned i = 0; i < args->shader_info->num_inline_push_consts; i++) {
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT,
+ &args->ac.inline_push_consts[i]);
}
- ctx->abi.num_inline_push_consts = ctx->shader_info->info.num_inline_push_consts;
- ctx->abi.base_inline_push_consts = ctx->shader_info->info.base_inline_push_consts;
+ args->ac.num_inline_push_consts = args->shader_info->num_inline_push_consts;
+ args->ac.base_inline_push_consts = args->shader_info->base_inline_push_consts;
- if (ctx->shader_info->info.so.num_outputs) {
- add_arg(args, ARG_SGPR,
- ac_array_in_const32_addr_space(ctx->ac.v4i32),
- &ctx->streamout_buffers);
+ if (args->shader_info->so.num_outputs) {
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_CONST_DESC_PTR,
+ &args->streamout_buffers);
}
}
static void
-declare_vs_specific_input_sgprs(struct radv_shader_context *ctx,
+declare_vs_specific_input_sgprs(struct radv_shader_args *args,
gl_shader_stage stage,
bool has_previous_stage,
- gl_shader_stage previous_stage,
- struct arg_info *args)
+ gl_shader_stage previous_stage)
{
- if (!ctx->is_gs_copy_shader &&
+ if (!args->is_gs_copy_shader &&
(stage == MESA_SHADER_VERTEX ||
(has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
- if (ctx->shader_info->info.vs.has_vertex_buffers) {
- add_arg(args, ARG_SGPR,
- ac_array_in_const32_addr_space(ctx->ac.v4i32),
- &ctx->vertex_buffers);
+ if (args->shader_info->vs.has_vertex_buffers) {
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_CONST_DESC_PTR,
+ &args->vertex_buffers);
}
- add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
- add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
- if (ctx->shader_info->info.vs.needs_draw_id) {
- add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.base_vertex);
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.start_instance);
+ if (args->shader_info->vs.needs_draw_id) {
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.draw_id);
}
}
}
static void
-declare_vs_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
+declare_vs_input_vgprs(struct radv_shader_args *args)
{
- add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
- if (!ctx->is_gs_copy_shader) {
- if (ctx->options->key.vs_common_out.as_ls) {
- add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
- if (ctx->ac.chip_class >= GFX10) {
- add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* user vgpr */
- add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.vertex_id);
+ if (!args->is_gs_copy_shader) {
+ if (args->options->key.vs_common_out.as_ls) {
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->rel_auto_id);
+ if (args->options->chip_class >= GFX10) {
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, NULL); /* user vgpr */
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.instance_id);
} else {
- add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
- add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.instance_id);
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, NULL); /* unused */
}
} else {
- if (ctx->ac.chip_class >= GFX10) {
- add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* user vgpr */
- add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* user vgpr */
- add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
+ if (args->options->chip_class >= GFX10) {
+ if (args->options->key.vs_common_out.as_ngg) {
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, NULL); /* user vgpr */
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, NULL); /* user vgpr */
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.instance_id);
+ } else {
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, NULL); /* unused */
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->vs_prim_id);
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.instance_id);
+ }
} else {
- add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
- add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
- add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.instance_id);
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->vs_prim_id);
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, NULL); /* unused */
}
}
}
}
static void
-declare_streamout_sgprs(struct radv_shader_context *ctx, gl_shader_stage stage,
- struct arg_info *args)
+declare_streamout_sgprs(struct radv_shader_args *args, gl_shader_stage stage)
{
int i;
- if (ctx->ac.chip_class >= GFX10)
+ if (args->options->use_ngg_streamout) {
+ if (stage == MESA_SHADER_TESS_EVAL)
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
return;
+ }
/* Streamout SGPRs. */
- if (ctx->shader_info->info.so.num_outputs) {
+ if (args->shader_info->so.num_outputs) {
assert(stage == MESA_SHADER_VERTEX ||
stage == MESA_SHADER_TESS_EVAL);
- if (stage != MESA_SHADER_TESS_EVAL) {
- add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->streamout_config);
- } else {
- args->assign[args->count - 1] = &ctx->streamout_config;
- args->types[args->count - 1] = ctx->ac.i32;
- }
-
- add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->streamout_write_idx);
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->streamout_config);
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->streamout_write_idx);
+ } else if (stage == MESA_SHADER_TESS_EVAL) {
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
}
/* A streamout buffer offset is loaded if the stride is non-zero. */
for (i = 0; i < 4; i++) {
- if (!ctx->shader_info->info.so.strides[i])
+ if (!args->shader_info->so.strides[i])
continue;
- add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->streamout_offset[i]);
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->streamout_offset[i]);
}
}
static void
-declare_tes_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
+declare_tes_input_vgprs(struct radv_shader_args *args)
{
- add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
- add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
- add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
- add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_FLOAT, &args->tes_u);
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_FLOAT, &args->tes_v);
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->tes_rel_patch_id);
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.tes_patch_id);
}
static void
-set_global_input_locs(struct radv_shader_context *ctx,
+set_global_input_locs(struct radv_shader_args *args,
const struct user_sgpr_info *user_sgpr_info,
- LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
+ uint8_t *user_sgpr_idx)
{
- uint32_t mask = ctx->shader_info->info.desc_set_used_mask;
+ uint32_t mask = args->shader_info->desc_set_used_mask;
if (!user_sgpr_info->indirect_all_descriptor_sets) {
while (mask) {
int i = u_bit_scan(&mask);
- set_loc_desc(ctx, i, user_sgpr_idx);
+ set_loc_desc(args, i, user_sgpr_idx);
}
} else {
- set_loc_shader_ptr(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
- user_sgpr_idx);
+ set_loc_shader_ptr(args, AC_UD_INDIRECT_DESCRIPTOR_SETS,
+ user_sgpr_idx);
+
+ args->shader_info->need_indirect_descriptor_sets = true;
+ }
+
+ if (args->shader_info->loads_push_constants) {
+ set_loc_shader_ptr(args, AC_UD_PUSH_CONSTANTS, user_sgpr_idx);
+ }
+
+ if (args->shader_info->num_inline_push_consts) {
+ set_loc_shader(args, AC_UD_INLINE_PUSH_CONSTANTS, user_sgpr_idx,
+ args->shader_info->num_inline_push_consts);
+ }
+
+ if (args->streamout_buffers.used) {
+ set_loc_shader_ptr(args, AC_UD_STREAMOUT_BUFFERS,
+ user_sgpr_idx);
+ }
+}
+static void
+load_descriptor_sets(struct radv_shader_context *ctx)
+{
+ uint32_t mask = ctx->args->shader_info->desc_set_used_mask;
+ if (ctx->args->shader_info->need_indirect_descriptor_sets) {
+ LLVMValueRef desc_sets =
+ ac_get_arg(&ctx->ac, ctx->args->descriptor_sets[0]);
while (mask) {
int i = u_bit_scan(&mask);
LLVMConstInt(ctx->ac.i32, i, false));
}
+ } else {
+ while (mask) {
+ int i = u_bit_scan(&mask);
- ctx->shader_info->need_indirect_descriptor_sets = true;
- }
-
- if (ctx->shader_info->info.loads_push_constants) {
- set_loc_shader_ptr(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx);
- }
-
- if (ctx->shader_info->info.num_inline_push_consts) {
- set_loc_shader(ctx, AC_UD_INLINE_PUSH_CONSTANTS, user_sgpr_idx,
- ctx->shader_info->info.num_inline_push_consts);
- }
-
- if (ctx->streamout_buffers) {
- set_loc_shader_ptr(ctx, AC_UD_STREAMOUT_BUFFERS,
- user_sgpr_idx);
+ ctx->descriptor_sets[i] =
+ ac_get_arg(&ctx->ac, ctx->args->descriptor_sets[i]);
+ }
}
}
+
static void
-set_vs_specific_input_locs(struct radv_shader_context *ctx,
+set_vs_specific_input_locs(struct radv_shader_args *args,
gl_shader_stage stage, bool has_previous_stage,
gl_shader_stage previous_stage,
uint8_t *user_sgpr_idx)
{
- if (!ctx->is_gs_copy_shader &&
+ if (!args->is_gs_copy_shader &&
(stage == MESA_SHADER_VERTEX ||
(has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
- if (ctx->shader_info->info.vs.has_vertex_buffers) {
- set_loc_shader_ptr(ctx, AC_UD_VS_VERTEX_BUFFERS,
+ if (args->shader_info->vs.has_vertex_buffers) {
+ set_loc_shader_ptr(args, AC_UD_VS_VERTEX_BUFFERS,
user_sgpr_idx);
}
unsigned vs_num = 2;
- if (ctx->shader_info->info.vs.needs_draw_id)
+ if (args->shader_info->vs.needs_draw_id)
vs_num++;
- set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
+ set_loc_shader(args, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
user_sgpr_idx, vs_num);
}
}
-static void set_llvm_calling_convention(LLVMValueRef func,
- gl_shader_stage stage)
+static enum ac_llvm_calling_convention
+get_llvm_calling_convention(LLVMValueRef func, gl_shader_stage stage)
{
- enum radeon_llvm_calling_convention calling_conv;
-
switch (stage) {
case MESA_SHADER_VERTEX:
case MESA_SHADER_TESS_EVAL:
- calling_conv = RADEON_LLVM_AMDGPU_VS;
+ return AC_LLVM_AMDGPU_VS;
break;
case MESA_SHADER_GEOMETRY:
- calling_conv = RADEON_LLVM_AMDGPU_GS;
+ return AC_LLVM_AMDGPU_GS;
break;
case MESA_SHADER_TESS_CTRL:
- calling_conv = RADEON_LLVM_AMDGPU_HS;
+ return AC_LLVM_AMDGPU_HS;
break;
case MESA_SHADER_FRAGMENT:
- calling_conv = RADEON_LLVM_AMDGPU_PS;
+ return AC_LLVM_AMDGPU_PS;
break;
case MESA_SHADER_COMPUTE:
- calling_conv = RADEON_LLVM_AMDGPU_CS;
+ return AC_LLVM_AMDGPU_CS;
break;
default:
unreachable("Unhandle shader type");
}
-
- LLVMSetFunctionCallConv(func, calling_conv);
}
/* Returns whether the stage is a stage that can be directly before the GS */
return stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_TESS_EVAL;
}
-static void create_function(struct radv_shader_context *ctx,
- gl_shader_stage stage,
- bool has_previous_stage,
- gl_shader_stage previous_stage)
+static void declare_inputs(struct radv_shader_args *args,
+ gl_shader_stage stage,
+ bool has_previous_stage,
+ gl_shader_stage previous_stage)
{
- uint8_t user_sgpr_idx;
struct user_sgpr_info user_sgpr_info;
- struct arg_info args = {};
- LLVMValueRef desc_sets;
- bool needs_view_index = needs_view_index_sgpr(ctx, stage);
+ bool needs_view_index = needs_view_index_sgpr(args, stage);
- if (ctx->ac.chip_class >= GFX10) {
- if (is_pre_gs_stage(stage) && ctx->options->key.vs_common_out.as_ngg) {
+ if (args->options->chip_class >= GFX10) {
+ if (is_pre_gs_stage(stage) && args->options->key.vs_common_out.as_ngg) {
/* On GFX10, VS is merged into GS for NGG. */
previous_stage = stage;
stage = MESA_SHADER_GEOMETRY;
}
}
- allocate_user_sgprs(ctx, stage, has_previous_stage,
+ for (int i = 0; i < MAX_SETS; i++)
+ args->shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
+ for (int i = 0; i < AC_UD_MAX_UD; i++)
+ args->shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
+
+
+ allocate_user_sgprs(args, stage, has_previous_stage,
previous_stage, needs_view_index, &user_sgpr_info);
- if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
- add_arg(&args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
- &ctx->ring_offsets);
+ if (user_sgpr_info.need_ring_offsets && !args->options->supports_spill) {
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 2, AC_ARG_CONST_DESC_PTR,
+ &args->ring_offsets);
}
switch (stage) {
case MESA_SHADER_COMPUTE:
- declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
- &desc_sets);
+ declare_global_input_sgprs(args, &user_sgpr_info);
- if (ctx->shader_info->info.cs.uses_grid_size) {
- add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
- &ctx->abi.num_work_groups);
+ if (args->shader_info->cs.uses_grid_size) {
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 3, AC_ARG_INT,
+ &args->ac.num_work_groups);
}
for (int i = 0; i < 3; i++) {
- ctx->abi.workgroup_ids[i] = NULL;
- if (ctx->shader_info->info.cs.uses_block_id[i]) {
- add_arg(&args, ARG_SGPR, ctx->ac.i32,
- &ctx->abi.workgroup_ids[i]);
+ if (args->shader_info->cs.uses_block_id[i]) {
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT,
+ &args->ac.workgroup_ids[i]);
}
}
- if (ctx->shader_info->info.cs.uses_local_invocation_idx)
- add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.tg_size);
- add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
- &ctx->abi.local_invocation_ids);
+ if (args->shader_info->cs.uses_local_invocation_idx) {
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT,
+ &args->ac.tg_size);
+ }
+
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 3, AC_ARG_INT,
+ &args->ac.local_invocation_ids);
break;
case MESA_SHADER_VERTEX:
- declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
- &desc_sets);
+ declare_global_input_sgprs(args, &user_sgpr_info);
- declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
- previous_stage, &args);
+ declare_vs_specific_input_sgprs(args, stage, has_previous_stage,
+ previous_stage);
- if (needs_view_index)
- add_arg(&args, ARG_SGPR, ctx->ac.i32,
- &ctx->abi.view_index);
- if (ctx->options->key.vs_common_out.as_es) {
- add_arg(&args, ARG_SGPR, ctx->ac.i32,
- &ctx->es2gs_offset);
- } else if (ctx->options->key.vs_common_out.as_ls) {
+ if (needs_view_index) {
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT,
+ &args->ac.view_index);
+ }
+
+ if (args->options->key.vs_common_out.as_es) {
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT,
+ &args->es2gs_offset);
+ } else if (args->options->key.vs_common_out.as_ls) {
/* no extra parameters */
} else {
- declare_streamout_sgprs(ctx, stage, &args);
+ declare_streamout_sgprs(args, stage);
}
- declare_vs_input_vgprs(ctx, &args);
+ declare_vs_input_vgprs(args);
break;
case MESA_SHADER_TESS_CTRL:
if (has_previous_stage) {
// First 6 system regs
- add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
- add_arg(&args, ARG_SGPR, ctx->ac.i32,
- &ctx->merged_wave_info);
- add_arg(&args, ARG_SGPR, ctx->ac.i32,
- &ctx->tess_factor_offset);
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->oc_lds);
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT,
+ &args->merged_wave_info);
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT,
+ &args->tess_factor_offset);
- add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
- add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
- add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, NULL); // scratch offset
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, NULL); // unknown
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, NULL); // unknown
- declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
- &desc_sets);
+ declare_global_input_sgprs(args, &user_sgpr_info);
- declare_vs_specific_input_sgprs(ctx, stage,
+ declare_vs_specific_input_sgprs(args, stage,
has_previous_stage,
- previous_stage, &args);
+ previous_stage);
- if (needs_view_index)
- add_arg(&args, ARG_SGPR, ctx->ac.i32,
- &ctx->abi.view_index);
+ if (needs_view_index) {
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT,
+ &args->ac.view_index);
+ }
- add_arg(&args, ARG_VGPR, ctx->ac.i32,
- &ctx->abi.tcs_patch_id);
- add_arg(&args, ARG_VGPR, ctx->ac.i32,
- &ctx->abi.tcs_rel_ids);
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT,
+ &args->ac.tcs_patch_id);
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT,
+ &args->ac.tcs_rel_ids);
- declare_vs_input_vgprs(ctx, &args);
+ declare_vs_input_vgprs(args);
} else {
- declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
- &desc_sets);
-
- if (needs_view_index)
- add_arg(&args, ARG_SGPR, ctx->ac.i32,
- &ctx->abi.view_index);
-
- add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
- add_arg(&args, ARG_SGPR, ctx->ac.i32,
- &ctx->tess_factor_offset);
- add_arg(&args, ARG_VGPR, ctx->ac.i32,
- &ctx->abi.tcs_patch_id);
- add_arg(&args, ARG_VGPR, ctx->ac.i32,
- &ctx->abi.tcs_rel_ids);
+ declare_global_input_sgprs(args, &user_sgpr_info);
+
+ if (needs_view_index) {
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT,
+ &args->ac.view_index);
+ }
+
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->oc_lds);
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT,
+ &args->tess_factor_offset);
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT,
+ &args->ac.tcs_patch_id);
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT,
+ &args->ac.tcs_rel_ids);
}
break;
case MESA_SHADER_TESS_EVAL:
- declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
- &desc_sets);
+ declare_global_input_sgprs(args, &user_sgpr_info);
if (needs_view_index)
- add_arg(&args, ARG_SGPR, ctx->ac.i32,
- &ctx->abi.view_index);
-
- if (ctx->options->key.vs_common_out.as_es) {
- add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
- add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
- add_arg(&args, ARG_SGPR, ctx->ac.i32,
- &ctx->es2gs_offset);
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT,
+ &args->ac.view_index);
+
+ if (args->options->key.vs_common_out.as_es) {
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->oc_lds);
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT,
+ &args->es2gs_offset);
} else {
- add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
- declare_streamout_sgprs(ctx, stage, &args);
- add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
+ declare_streamout_sgprs(args, stage);
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->oc_lds);
}
- declare_tes_input_vgprs(ctx, &args);
+ declare_tes_input_vgprs(args);
break;
case MESA_SHADER_GEOMETRY:
if (has_previous_stage) {
// First 6 system regs
- if (ctx->options->key.vs_common_out.as_ngg) {
- add_arg(&args, ARG_SGPR, ctx->ac.i32,
- &ctx->gs_tg_info);
+ if (args->options->key.vs_common_out.as_ngg) {
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT,
+ &args->gs_tg_info);
} else {
- add_arg(&args, ARG_SGPR, ctx->ac.i32,
- &ctx->gs2vs_offset);
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT,
+ &args->gs2vs_offset);
}
- add_arg(&args, ARG_SGPR, ctx->ac.i32,
- &ctx->merged_wave_info);
- add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT,
+ &args->merged_wave_info);
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->oc_lds);
- add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
- add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
- add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, NULL); // scratch offset
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, NULL); // unknown
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, NULL); // unknown
- declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
- &desc_sets);
+ declare_global_input_sgprs(args, &user_sgpr_info);
if (previous_stage != MESA_SHADER_TESS_EVAL) {
- declare_vs_specific_input_sgprs(ctx, stage,
+ declare_vs_specific_input_sgprs(args, stage,
has_previous_stage,
- previous_stage,
- &args);
+ previous_stage);
+ }
+
+ if (needs_view_index) {
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT,
+ &args->ac.view_index);
}
- if (needs_view_index)
- add_arg(&args, ARG_SGPR, ctx->ac.i32,
- &ctx->abi.view_index);
-
- add_arg(&args, ARG_VGPR, ctx->ac.i32,
- &ctx->gs_vtx_offset[0]);
- add_arg(&args, ARG_VGPR, ctx->ac.i32,
- &ctx->gs_vtx_offset[2]);
- add_arg(&args, ARG_VGPR, ctx->ac.i32,
- &ctx->abi.gs_prim_id);
- add_arg(&args, ARG_VGPR, ctx->ac.i32,
- &ctx->abi.gs_invocation_id);
- add_arg(&args, ARG_VGPR, ctx->ac.i32,
- &ctx->gs_vtx_offset[4]);
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT,
+ &args->gs_vtx_offset[0]);
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT,
+ &args->gs_vtx_offset[2]);
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT,
+ &args->ac.gs_prim_id);
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT,
+ &args->ac.gs_invocation_id);
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT,
+ &args->gs_vtx_offset[4]);
if (previous_stage == MESA_SHADER_VERTEX) {
- declare_vs_input_vgprs(ctx, &args);
+ declare_vs_input_vgprs(args);
} else {
- declare_tes_input_vgprs(ctx, &args);
+ declare_tes_input_vgprs(args);
}
} else {
- declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
- &desc_sets);
-
- if (needs_view_index)
- add_arg(&args, ARG_SGPR, ctx->ac.i32,
- &ctx->abi.view_index);
-
- add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
- add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
- add_arg(&args, ARG_VGPR, ctx->ac.i32,
- &ctx->gs_vtx_offset[0]);
- add_arg(&args, ARG_VGPR, ctx->ac.i32,
- &ctx->gs_vtx_offset[1]);
- add_arg(&args, ARG_VGPR, ctx->ac.i32,
- &ctx->abi.gs_prim_id);
- add_arg(&args, ARG_VGPR, ctx->ac.i32,
- &ctx->gs_vtx_offset[2]);
- add_arg(&args, ARG_VGPR, ctx->ac.i32,
- &ctx->gs_vtx_offset[3]);
- add_arg(&args, ARG_VGPR, ctx->ac.i32,
- &ctx->gs_vtx_offset[4]);
- add_arg(&args, ARG_VGPR, ctx->ac.i32,
- &ctx->gs_vtx_offset[5]);
- add_arg(&args, ARG_VGPR, ctx->ac.i32,
- &ctx->abi.gs_invocation_id);
+ declare_global_input_sgprs(args, &user_sgpr_info);
+
+ if (needs_view_index) {
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT,
+ &args->ac.view_index);
+ }
+
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->gs2vs_offset);
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->gs_wave_id);
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT,
+ &args->gs_vtx_offset[0]);
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT,
+ &args->gs_vtx_offset[1]);
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT,
+ &args->ac.gs_prim_id);
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT,
+ &args->gs_vtx_offset[2]);
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT,
+ &args->gs_vtx_offset[3]);
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT,
+ &args->gs_vtx_offset[4]);
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT,
+ &args->gs_vtx_offset[5]);
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT,
+ &args->ac.gs_invocation_id);
}
break;
case MESA_SHADER_FRAGMENT:
- declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
- &desc_sets);
-
- add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.prim_mask);
- add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
- add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
- add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
- add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
- add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
- add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
- add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
- add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
- add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
- add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
- add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
- add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
- add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
- add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
- add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
- add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
+ declare_global_input_sgprs(args, &user_sgpr_info);
+
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.prim_mask);
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 2, AC_ARG_INT, &args->ac.persp_sample);
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 2, AC_ARG_INT, &args->ac.persp_center);
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 2, AC_ARG_INT, &args->ac.persp_centroid);
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 3, AC_ARG_INT, NULL); /* persp pull model */
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 2, AC_ARG_INT, &args->ac.linear_sample);
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 2, AC_ARG_INT, &args->ac.linear_center);
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 2, AC_ARG_INT, &args->ac.linear_centroid);
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_FLOAT, NULL); /* line stipple tex */
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_FLOAT, &args->ac.frag_pos[0]);
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_FLOAT, &args->ac.frag_pos[1]);
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_FLOAT, &args->ac.frag_pos[2]);
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_FLOAT, &args->ac.frag_pos[3]);
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.front_face);
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.ancillary);
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.sample_coverage);
+ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, NULL); /* fixed pt */
break;
default:
unreachable("Shader stage not implemented");
}
- ctx->main_function = create_llvm_function(
- ctx->context, ctx->ac.module, ctx->ac.builder, NULL, 0, &args,
- ctx->max_workgroup_size, ctx->options);
- set_llvm_calling_convention(ctx->main_function, stage);
-
-
- ctx->shader_info->num_input_vgprs = 0;
- ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
-
- ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
-
- if (ctx->stage != MESA_SHADER_FRAGMENT)
- ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
+ args->shader_info->num_input_vgprs = 0;
+ args->shader_info->num_input_sgprs = args->options->supports_spill ? 2 : 0;
+ args->shader_info->num_input_sgprs += args->ac.num_sgprs_used;
- assign_arguments(ctx->main_function, &args);
+ if (stage != MESA_SHADER_FRAGMENT)
+ args->shader_info->num_input_vgprs = args->ac.num_vgprs_used;
- user_sgpr_idx = 0;
+ uint8_t user_sgpr_idx = 0;
- if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
- set_loc_shader_ptr(ctx, AC_UD_SCRATCH_RING_OFFSETS,
+ if (args->options->supports_spill || user_sgpr_info.need_ring_offsets) {
+ set_loc_shader_ptr(args, AC_UD_SCRATCH_RING_OFFSETS,
&user_sgpr_idx);
- if (ctx->options->supports_spill) {
- ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
- LLVMPointerType(ctx->ac.i8, AC_ADDR_SPACE_CONST),
- NULL, 0, AC_FUNC_ATTR_READNONE);
- ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
- ac_array_in_const_addr_space(ctx->ac.v4i32), "");
- }
}
/* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
if (has_previous_stage)
user_sgpr_idx = 0;
- set_global_input_locs(ctx, &user_sgpr_info, desc_sets, &user_sgpr_idx);
+ set_global_input_locs(args, &user_sgpr_info, &user_sgpr_idx);
switch (stage) {
case MESA_SHADER_COMPUTE:
- if (ctx->shader_info->info.cs.uses_grid_size) {
- set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
+ if (args->shader_info->cs.uses_grid_size) {
+ set_loc_shader(args, AC_UD_CS_GRID_SIZE,
&user_sgpr_idx, 3);
}
break;
case MESA_SHADER_VERTEX:
- set_vs_specific_input_locs(ctx, stage, has_previous_stage,
+ set_vs_specific_input_locs(args, stage, has_previous_stage,
previous_stage, &user_sgpr_idx);
- if (ctx->abi.view_index)
- set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
+ if (args->ac.view_index.used)
+ set_loc_shader(args, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
break;
case MESA_SHADER_TESS_CTRL:
- set_vs_specific_input_locs(ctx, stage, has_previous_stage,
+ set_vs_specific_input_locs(args, stage, has_previous_stage,
previous_stage, &user_sgpr_idx);
- if (ctx->abi.view_index)
- set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
+ if (args->ac.view_index.used)
+ set_loc_shader(args, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
break;
case MESA_SHADER_TESS_EVAL:
- if (ctx->abi.view_index)
- set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
+ if (args->ac.view_index.used)
+ set_loc_shader(args, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
break;
case MESA_SHADER_GEOMETRY:
if (has_previous_stage) {
if (previous_stage == MESA_SHADER_VERTEX)
- set_vs_specific_input_locs(ctx, stage,
+ set_vs_specific_input_locs(args, stage,
has_previous_stage,
previous_stage,
&user_sgpr_idx);
}
- if (ctx->abi.view_index)
- set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
+ if (args->ac.view_index.used)
+ set_loc_shader(args, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
break;
case MESA_SHADER_FRAGMENT:
break;
unreachable("Shader stage not implemented");
}
+ args->shader_info->num_user_sgprs = user_sgpr_idx;
+}
+
+static void create_function(struct radv_shader_context *ctx,
+ gl_shader_stage stage,
+ bool has_previous_stage)
+{
+ if (ctx->ac.chip_class >= GFX10) {
+ if (is_pre_gs_stage(stage) && ctx->args->options->key.vs_common_out.as_ngg) {
+ /* On GFX10, VS is merged into GS for NGG. */
+ stage = MESA_SHADER_GEOMETRY;
+ has_previous_stage = true;
+ }
+ }
+
+ ctx->main_function = create_llvm_function(
+ &ctx->ac, ctx->ac.module, ctx->ac.builder, &ctx->args->ac,
+ get_llvm_calling_convention(ctx->main_function, stage),
+ ctx->max_workgroup_size,
+ ctx->args->options);
+
+ if (ctx->args->options->supports_spill) {
+ ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
+ LLVMPointerType(ctx->ac.i8, AC_ADDR_SPACE_CONST),
+ NULL, 0, AC_FUNC_ATTR_READNONE);
+ ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
+ ac_array_in_const_addr_space(ctx->ac.v4i32), "");
+ } else if (ctx->args->ring_offsets.used) {
+ ctx->ring_offsets = ac_get_arg(&ctx->ac, ctx->args->ring_offsets);
+ }
+
+ load_descriptor_sets(ctx);
+
if (stage == MESA_SHADER_TESS_CTRL ||
- (stage == MESA_SHADER_VERTEX && ctx->options->key.vs_common_out.as_ls) ||
+ (stage == MESA_SHADER_VERTEX && ctx->args->options->key.vs_common_out.as_ls) ||
/* GFX9 has the ESGS ring buffer in LDS. */
(stage == MESA_SHADER_GEOMETRY && has_previous_stage)) {
ac_declare_lds_as_pointer(&ctx->ac);
}
- ctx->shader_info->num_user_sgprs = user_sgpr_idx;
}
{
struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
- struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
+ struct radv_pipeline_layout *pipeline_layout = ctx->args->options->layout;
struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
unsigned base_offset = layout->binding[binding].offset;
LLVMValueRef offset, stride;
layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
layout->binding[binding].dynamic_offset_offset;
- desc_ptr = ctx->abi.push_constants;
+ desc_ptr = ac_get_arg(&ctx->ac, ctx->args->ac.push_constants);
base_offset = pipeline_layout->push_constant_size + 16 * idx;
stride = LLVMConstInt(ctx->ac.i32, 16, false);
} else
uint32_t desc_type = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
- S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
- S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
- S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
+ S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
+
+ if (ctx->ac.chip_class >= GFX10) {
+ desc_type |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
+ S_008F0C_OOB_SELECT(3) |
+ S_008F0C_RESOURCE_LEVEL(1);
+ } else {
+ desc_type |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
+ S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
+ }
LLVMValueRef desc_components[4] = {
LLVMBuildPtrToInt(ctx->ac.builder, desc_ptr, ctx->ac.intptr, ""),
- LLVMConstInt(ctx->ac.i32, S_008F04_BASE_ADDRESS_HI(ctx->options->address32_hi), false),
+ LLVMConstInt(ctx->ac.i32, S_008F04_BASE_ADDRESS_HI(ctx->args->options->address32_hi), false),
/* High limit to support variable sizes. */
LLVMConstInt(ctx->ac.i32, 0xffffffff, false),
LLVMConstInt(ctx->ac.i32, desc_type, false),
uint32_t num_patches = ctx->tcs_num_patches;
uint32_t num_tcs_outputs;
if (ctx->stage == MESA_SHADER_TESS_CTRL)
- num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
+ num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
else
- num_tcs_outputs = ctx->options->key.tes.tcs_num_outputs;
+ num_tcs_outputs = ctx->args->options->key.tes.tcs_num_outputs;
uint32_t output_vertex_size = num_tcs_outputs * 16;
- uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
+ uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
return LLVMConstInt(ctx->ac.i32, pervertex_output_patch_size * num_patches, false);
}
{
LLVMValueRef param_stride;
if (vertex_index)
- param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch * ctx->tcs_num_patches, false);
+ param_stride = LLVMConstInt(ctx->ac.i32, ctx->shader->info.tess.tcs_vertices_out * ctx->tcs_num_patches, false);
else
param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_num_patches, false);
return param_stride;
LLVMValueRef base_addr;
LLVMValueRef param_stride, constant16;
LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
- LLVMValueRef vertices_per_patch = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch, false);
+ LLVMValueRef vertices_per_patch = LLVMConstInt(ctx->ac.i32, ctx->shader->info.tess.tcs_vertices_out, false);
constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
param_stride = calc_param_stride(ctx, vertex_index);
if (vertex_index) {
LLVMValueRef dw_addr;
LLVMValueRef stride = NULL;
LLVMValueRef buf_addr = NULL;
+ LLVMValueRef oc_lds = ac_get_arg(&ctx->ac, ctx->args->oc_lds);
unsigned param;
bool store_lds = true;
if (is_patch) {
- if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
+ if (!(ctx->shader->info.patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
store_lds = false;
} else {
- if (!(ctx->tcs_outputs_read & (1ULL << location)))
+ if (!(ctx->shader->info.outputs_read & (1ULL << location)))
store_lds = false;
}
if (!is_tess_factor && writemask != 0xF)
ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
- buf_addr, ctx->oc_lds,
+ buf_addr, oc_lds,
4 * (base + chan), ac_glc, false);
}
if (writemask == 0xF) {
ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
- buf_addr, ctx->oc_lds,
+ buf_addr, oc_lds,
(base * 4), ac_glc, false);
}
}
struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
LLVMValueRef buf_addr;
LLVMValueRef result;
+ LLVMValueRef oc_lds = ac_get_arg(&ctx->ac, ctx->args->oc_lds);
unsigned param = shader_io_get_unique_index(location);
if ((location == VARYING_SLOT_CLIP_DIST0 || location == VARYING_SLOT_CLIP_DIST1) && is_compact) {
buf_addr = LLVMBuildAdd(ctx->ac.builder, buf_addr, comp_offset, "");
result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
- buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, ac_glc, true, false);
+ buf_addr, oc_lds, is_compact ? (4 * const_index) : 0, ac_glc, true, false);
result = ac_trim_vector(&ctx->ac, result, num_components);
return result;
}
+static LLVMValueRef
+radv_emit_fetch_64bit(struct radv_shader_context *ctx,
+ LLVMTypeRef type, LLVMValueRef a, LLVMValueRef b)
+{
+ LLVMValueRef values[2] = {
+ ac_to_integer(&ctx->ac, a),
+ ac_to_integer(&ctx->ac, b),
+ };
+ LLVMValueRef result = ac_build_gather_values(&ctx->ac, values, 2);
+ return LLVMBuildBitCast(ctx->ac.builder, result, type, "");
+}
+
static LLVMValueRef
load_gs_input(struct ac_shader_abi *abi,
unsigned location,
dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
value[i] = ac_lds_load(&ctx->ac, dw_addr);
+
+ if (ac_get_type_size(type) == 8) {
+ dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
+ LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index + 1, 0), "");
+ LLVMValueRef tmp = ac_lds_load(&ctx->ac, dw_addr);
+
+ value[i] = radv_emit_fetch_64bit(ctx, type, value[i], tmp);
+ }
} else {
LLVMValueRef soffset =
LLVMConstInt(ctx->ac.i32,
ctx->ac.i32_0,
vtx_offset, soffset,
0, ac_glc, true, false);
+
+ if (ac_get_type_size(type) == 8) {
+ soffset = LLVMConstInt(ctx->ac.i32,
+ (param * 4 + i + const_index + 1) * 256,
+ false);
+
+ LLVMValueRef tmp =
+ ac_build_buffer_load(&ctx->ac,
+ ctx->esgs_ring, 1,
+ ctx->ac.i32_0,
+ vtx_offset, soffset,
+ 0, ac_glc, true, false);
+
+ value[i] = radv_emit_fetch_64bit(ctx, type, value[i], tmp);
+ }
}
if (ac_get_type_size(type) == 2) {
ac_build_kill_if_false(&ctx->ac, visible);
}
-static LLVMValueRef lookup_interp_param(struct ac_shader_abi *abi,
- enum glsl_interp_mode interp, unsigned location)
-{
- struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
-
- switch (interp) {
- case INTERP_MODE_FLAT:
- default:
- return NULL;
- case INTERP_MODE_SMOOTH:
- case INTERP_MODE_NONE:
- if (location == INTERP_CENTER)
- return ctx->persp_center;
- else if (location == INTERP_CENTROID)
- return ctx->persp_centroid;
- else if (location == INTERP_SAMPLE)
- return ctx->persp_sample;
- break;
- case INTERP_MODE_NOPERSPECTIVE:
- if (location == INTERP_CENTER)
- return ctx->linear_center;
- else if (location == INTERP_CENTROID)
- return ctx->linear_centroid;
- else if (location == INTERP_SAMPLE)
- return ctx->linear_sample;
- break;
- }
- return NULL;
-}
-
static uint32_t
radv_get_sample_pos_offset(uint32_t num_samples)
{
ac_array_in_const_addr_space(ctx->ac.v2f32), "");
uint32_t sample_pos_offset =
- radv_get_sample_pos_offset(ctx->options->key.fs.num_samples);
+ radv_get_sample_pos_offset(ctx->args->options->key.fs.num_samples);
sample_id =
LLVMBuildAdd(ctx->ac.builder, sample_id,
struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
uint8_t log2_ps_iter_samples;
- if (ctx->shader_info->info.ps.force_persample) {
+ if (ctx->args->shader_info->ps.force_persample) {
log2_ps_iter_samples =
- util_logbase2(ctx->options->key.fs.num_samples);
+ util_logbase2(ctx->args->options->key.fs.num_samples);
} else {
- log2_ps_iter_samples = ctx->options->key.fs.log2_ps_iter_samples;
+ log2_ps_iter_samples = ctx->args->options->key.fs.log2_ps_iter_samples;
}
/* The bit pattern matches that used by fixed function fragment
uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
LLVMValueRef result, sample_id;
- sample_id = ac_unpack_param(&ctx->ac, abi->ancillary, 8, 4);
+ sample_id = ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->ac.ancillary), 8, 4);
sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
- result = LLVMBuildAnd(ctx->ac.builder, sample_id, abi->sample_coverage, "");
+ result = LLVMBuildAnd(ctx->ac.builder, sample_id,
+ ac_get_arg(&ctx->ac, ctx->args->ac.sample_coverage), "");
return result;
}
unsigned offset = 0;
struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
- if (ctx->options->key.vs_common_out.as_ngg) {
+ if (ctx->args->options->key.vs_common_out.as_ngg) {
gfx10_ngg_gs_emit_vertex(ctx, stream, addrs);
return;
}
"");
/* If this thread has already emitted the declared maximum number of
- * vertices, kill it: excessive vertex emissions are not supposed to
- * have any effect, and GS threads have no externally observable
- * effects other than emitting vertices.
+ * vertices, don't emit any more: excessive vertex emissions are not
+ * supposed to have any effect.
*/
can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
- LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
- ac_build_kill_if_false(&ctx->ac, can_emit);
+ LLVMConstInt(ctx->ac.i32, ctx->shader->info.gs.vertices_out, false), "");
+
+ bool use_kill = !ctx->args->shader_info->gs.writes_memory;
+ if (use_kill)
+ ac_build_kill_if_false(&ctx->ac, can_emit);
+ else
+ ac_build_ifcc(&ctx->ac, can_emit, 6505);
for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
unsigned output_usage_mask =
- ctx->shader_info->info.gs.output_usage_mask[i];
+ ctx->args->shader_info->gs.output_usage_mask[i];
uint8_t output_stream =
- ctx->shader_info->info.gs.output_streams[i];
+ ctx->args->shader_info->gs.output_streams[i];
LLVMValueRef *out_ptr = &addrs[i * 4];
int length = util_last_bit(output_usage_mask);
out_ptr[j], "");
LLVMValueRef voffset =
LLVMConstInt(ctx->ac.i32, offset *
- ctx->gs_max_out_vertices, false);
+ ctx->shader->info.gs.vertices_out, false);
offset++;
ac_build_buffer_store_dword(&ctx->ac,
ctx->gsvs_ring[stream],
out_val, 1,
- voffset, ctx->gs2vs_offset, 0,
- ac_glc | ac_slc, true);
+ voffset,
+ ac_get_arg(&ctx->ac,
+ ctx->args->gs2vs_offset),
+ 0, ac_glc | ac_slc, true);
}
}
ac_build_sendmsg(&ctx->ac,
AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
ctx->gs_wave_id);
+
+ if (!use_kill)
+ ac_build_endif(&ctx->ac, 6505);
}
static void
{
struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
- if (ctx->options->key.vs_common_out.as_ngg) {
+ if (ctx->args->options->key.vs_common_out.as_ngg) {
LLVMBuildStore(ctx->ac.builder, ctx->ac.i32_0, ctx->gs_curprim_verts[stream]);
return;
}
struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
LLVMValueRef coord[4] = {
- ctx->tes_u,
- ctx->tes_v,
+ ac_get_arg(&ctx->ac, ctx->args->tes_u),
+ ac_get_arg(&ctx->ac, ctx->args->tes_v),
ctx->ac.f32_0,
ctx->ac.f32_0,
};
- if (ctx->tes_primitive_mode == GL_TRIANGLES)
+ if (ctx->shader->info.tess.primitive_mode == GL_TRIANGLES)
coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
load_patch_vertices_in(struct ac_shader_abi *abi)
{
struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
- return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
+ return LLVMConstInt(ctx->ac.i32, ctx->args->options->key.tcs.input_vertices, false);
}
static LLVMValueRef radv_load_base_vertex(struct ac_shader_abi *abi)
{
- return abi->base_vertex;
+ struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
+ return ac_get_arg(&ctx->ac, ctx->args->ac.base_vertex);
}
static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
{
struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
- struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
+ struct radv_descriptor_set_layout *layout = ctx->args->options->layout->set[descriptor_set].layout;
struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
unsigned offset = binding->offset;
unsigned stride = binding->size;
handle_vs_input_decl(struct radv_shader_context *ctx,
struct nir_variable *variable)
{
- LLVMValueRef t_list_ptr = ctx->vertex_buffers;
+ LLVMValueRef t_list_ptr = ac_get_arg(&ctx->ac, ctx->args->vertex_buffers);
LLVMValueRef t_offset;
LLVMValueRef t_list;
LLVMValueRef input;
LLVMValueRef buffer_index;
unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
uint8_t input_usage_mask =
- ctx->shader_info->info.vs.input_usage_mask[variable->data.location];
+ ctx->args->shader_info->vs.input_usage_mask[variable->data.location];
unsigned num_input_channels = util_last_bit(input_usage_mask);
variable->data.driver_location = variable->data.location * 4;
for (unsigned i = 0; i < attrib_count; ++i) {
LLVMValueRef output[4];
unsigned attrib_index = variable->data.location + i - VERT_ATTRIB_GENERIC0;
- unsigned attrib_format = ctx->options->key.vs.vertex_attribute_formats[attrib_index];
+ unsigned attrib_format = ctx->args->options->key.vs.vertex_attribute_formats[attrib_index];
unsigned data_format = attrib_format & 0x0f;
unsigned num_format = (attrib_format >> 4) & 0x07;
bool is_float = num_format != V_008F0C_BUF_NUM_FORMAT_UINT &&
num_format != V_008F0C_BUF_NUM_FORMAT_SINT;
- if (ctx->options->key.vs.instance_rate_inputs & (1u << attrib_index)) {
- uint32_t divisor = ctx->options->key.vs.instance_rate_divisors[attrib_index];
+ if (ctx->args->options->key.vs.instance_rate_inputs & (1u << attrib_index)) {
+ uint32_t divisor = ctx->args->options->key.vs.instance_rate_divisors[attrib_index];
if (divisor) {
buffer_index = ctx->abi.instance_id;
buffer_index = ctx->ac.i32_0;
}
- buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.start_instance, buffer_index, "");
- } else
- buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.vertex_id,
- ctx->abi.base_vertex, "");
+ buffer_index = LLVMBuildAdd(ctx->ac.builder,
+ ac_get_arg(&ctx->ac,
+ ctx->args->ac.start_instance),\
+ buffer_index, "");
+ } else {
+ buffer_index = LLVMBuildAdd(ctx->ac.builder,
+ ctx->abi.vertex_id,
+ ac_get_arg(&ctx->ac,
+ ctx->args->ac.base_vertex), "");
+ }
/* Adjust the number of channels to load based on the vertex
* attribute format.
*/
unsigned num_format_channels = get_num_channels_from_data_format(data_format);
unsigned num_channels = MIN2(num_input_channels, num_format_channels);
- unsigned attrib_binding = ctx->options->key.vs.vertex_attribute_bindings[attrib_index];
- unsigned attrib_offset = ctx->options->key.vs.vertex_attribute_offsets[attrib_index];
- unsigned attrib_stride = ctx->options->key.vs.vertex_attribute_strides[attrib_index];
+ unsigned attrib_binding = ctx->args->options->key.vs.vertex_attribute_bindings[attrib_index];
+ unsigned attrib_offset = ctx->args->options->key.vs.vertex_attribute_offsets[attrib_index];
+ unsigned attrib_stride = ctx->args->options->key.vs.vertex_attribute_strides[attrib_index];
- if (ctx->options->key.vs.post_shuffle & (1 << attrib_index)) {
+ if (ctx->args->options->key.vs.post_shuffle & (1 << attrib_index)) {
/* Always load, at least, 3 channels for formats that
* need to be shuffled because X<->Z.
*/
num_channels,
data_format, num_format, 0, true);
- if (ctx->options->key.vs.post_shuffle & (1 << attrib_index)) {
+ if (ctx->args->options->key.vs.post_shuffle & (1 << attrib_index)) {
LLVMValueRef c[4];
c[0] = ac_llvm_extract_elem(&ctx->ac, input, 2);
c[1] = ac_llvm_extract_elem(&ctx->ac, input, 1);
}
}
- unsigned alpha_adjust = (ctx->options->key.vs.alpha_adjust >> (attrib_index * 2)) & 3;
+ unsigned alpha_adjust = (ctx->args->options->key.vs.alpha_adjust >> (attrib_index * 2)) & 3;
output[3] = adjust_vertex_fetch_alpha(ctx, alpha_adjust, output[3]);
for (unsigned chan = 0; chan < 4; chan++) {
uses_center = true;
}
+ ctx->abi.persp_centroid = ac_get_arg(&ctx->ac, ctx->args->ac.persp_centroid);
+ ctx->abi.linear_centroid = ac_get_arg(&ctx->ac, ctx->args->ac.linear_centroid);
+
if (uses_center && uses_centroid) {
- LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT, ctx->abi.prim_mask, ctx->ac.i32_0, "");
- ctx->persp_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->persp_center, ctx->persp_centroid, "");
- ctx->linear_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->linear_center, ctx->linear_centroid, "");
+ LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT,
+ ac_get_arg(&ctx->ac, ctx->args->ac.prim_mask),
+ ctx->ac.i32_0, "");
+ ctx->abi.persp_centroid =
+ LLVMBuildSelect(ctx->ac.builder, sel,
+ ac_get_arg(&ctx->ac, ctx->args->ac.persp_center),
+ ctx->abi.persp_centroid, "");
+ ctx->abi.linear_centroid =
+ LLVMBuildSelect(ctx->ac.builder, sel,
+ ac_get_arg(&ctx->ac, ctx->args->ac.linear_center),
+ ctx->abi.linear_centroid, "");
}
}
}
mask_attribs = ((1ull << attrib_count) - 1) << idx;
- if (stage == MESA_SHADER_VERTEX ||
- stage == MESA_SHADER_TESS_EVAL ||
- stage == MESA_SHADER_GEOMETRY) {
- if (idx == VARYING_SLOT_CLIP_DIST0) {
- if (stage == MESA_SHADER_VERTEX) {
- ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
- ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
- ctx->shader_info->vs.outinfo.cull_dist_mask <<= shader->info.clip_distance_array_size;
- }
- if (stage == MESA_SHADER_TESS_EVAL) {
- ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
- ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
- ctx->shader_info->tes.outinfo.cull_dist_mask <<= shader->info.clip_distance_array_size;
- }
- }
- }
ctx->output_mask |= mask_attribs;
}
bool is_16bit = ac_get_type_size(LLVMTypeOf(values[0])) == 2;
if (ctx->stage == MESA_SHADER_FRAGMENT) {
unsigned index = target - V_008DFC_SQ_EXP_MRT;
- unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
- bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
- bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
+ unsigned col_format = (ctx->args->options->key.fs.col_format >> (4 * index)) & 0xf;
+ bool is_int8 = (ctx->args->options->key.fs.is_int8 >> index) & 1;
+ bool is_int10 = (ctx->args->options->key.fs.is_int10 >> index) & 1;
unsigned chan;
LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
static LLVMValueRef
radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
{
- LLVMValueRef output;
-
- if (ctx->vertexptr) {
- LLVMValueRef gep_idx[3] = {
- ctx->ac.i32_0, /* implicit C-style array */
- ctx->ac.i32_0, /* second value of struct */
- ctx->ac.i32_1, /* stream 1: source data index */
- };
-
- gep_idx[2] = LLVMConstInt(ctx->ac.i32, ac_llvm_reg_index_soa(index, chan), false);
- output = LLVMBuildGEP(ctx->ac.builder, ctx->vertexptr, gep_idx, 3, "");
- } else {
- output = ctx->abi.outputs[ac_llvm_reg_index_soa(index, chan)];
- }
-
+ LLVMValueRef output = ctx->abi.outputs[ac_llvm_reg_index_soa(index, chan)];
return LLVMBuildLoad(ctx->ac.builder, output, "");
}
radv_emit_stream_output(struct radv_shader_context *ctx,
LLVMValueRef const *so_buffers,
LLVMValueRef const *so_write_offsets,
- const struct radv_stream_output *output)
+ const struct radv_stream_output *output,
+ struct radv_shader_output_values *shader_out)
{
unsigned num_comps = util_bitcount(output->component_mask);
- unsigned loc = output->location;
unsigned buf = output->buffer;
unsigned offset = output->offset;
unsigned start;
/* Load the output as int. */
for (int i = 0; i < num_comps; i++) {
- out[i] = ac_to_integer(&ctx->ac,
- radv_load_output(ctx, loc, start + i));
+ out[i] = ac_to_integer(&ctx->ac, shader_out->values[start + i]);
}
/* Pack the output. */
static void
radv_emit_streamout(struct radv_shader_context *ctx, unsigned stream)
{
- struct ac_build_if_state if_ctx;
int i;
/* Get bits [22:16], i.e. (so_param >> 16) & 127; */
- assert(ctx->streamout_config);
+ assert(ctx->args->streamout_config.used);
LLVMValueRef so_vtx_count =
- ac_build_bfe(&ctx->ac, ctx->streamout_config,
+ ac_build_bfe(&ctx->ac,
+ ac_get_arg(&ctx->ac, ctx->args->streamout_config),
LLVMConstInt(ctx->ac.i32, 16, false),
LLVMConstInt(ctx->ac.i32, 7, false), false);
* out-of-bounds buffer access. The hw tells us via the SGPR
* (so_vtx_count) which threads are allowed to emit streamout data.
*/
- ac_nir_build_if(&if_ctx, ctx, can_emit);
+ ac_build_ifcc(&ctx->ac, can_emit, 6501);
{
/* The buffer offset is computed as follows:
* ByteOffset = streamout_offset[buffer_id]*4 +
* (streamout_write_index + thread_id)*stride[buffer_id] +
* attrib_offset
*/
- LLVMValueRef so_write_index = ctx->streamout_write_idx;
+ LLVMValueRef so_write_index =
+ ac_get_arg(&ctx->ac, ctx->args->streamout_write_idx);
/* Compute (streamout_write_index + thread_id). */
so_write_index =
*/
LLVMValueRef so_write_offset[4] = {};
LLVMValueRef so_buffers[4] = {};
- LLVMValueRef buf_ptr = ctx->streamout_buffers;
+ LLVMValueRef buf_ptr = ac_get_arg(&ctx->ac, ctx->args->streamout_buffers);
for (i = 0; i < 4; i++) {
- uint16_t stride = ctx->shader_info->info.so.strides[i];
+ uint16_t stride = ctx->args->shader_info->so.strides[i];
if (!stride)
continue;
so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac,
buf_ptr, offset);
- LLVMValueRef so_offset = ctx->streamout_offset[i];
+ LLVMValueRef so_offset =
+ ac_get_arg(&ctx->ac, ctx->args->streamout_offset[i]);
so_offset = LLVMBuildMul(ctx->ac.builder, so_offset,
LLVMConstInt(ctx->ac.i32, 4, false), "");
}
/* Write streamout data. */
- for (i = 0; i < ctx->shader_info->info.so.num_outputs; i++) {
+ for (i = 0; i < ctx->args->shader_info->so.num_outputs; i++) {
+ struct radv_shader_output_values shader_out = {};
struct radv_stream_output *output =
- &ctx->shader_info->info.so.outputs[i];
+ &ctx->args->shader_info->so.outputs[i];
if (stream != output->stream)
continue;
- radv_emit_stream_output(ctx, so_buffers,
- so_write_offset, output);
+ for (int j = 0; j < 4; j++) {
+ shader_out.values[j] =
+ radv_load_output(ctx, output->location, j);
+ }
+
+ radv_emit_stream_output(ctx, so_buffers,so_write_offset,
+ output, &shader_out);
}
}
- ac_nir_build_endif(&if_ctx);
+ ac_build_endif(&ctx->ac, 6501);
}
-struct radv_shader_output_values {
- LLVMValueRef values[4];
- unsigned slot_name;
- unsigned slot_index;
- unsigned usage_mask;
-};
-
static void
radv_build_param_exports(struct radv_shader_context *ctx,
struct radv_shader_output_values *outputs,
if (outinfo->writes_layer == true)
pos_args[1].out[2] = layer_value;
if (outinfo->writes_viewport_index == true) {
- if (ctx->options->chip_class >= GFX9) {
+ if (ctx->args->options->chip_class >= GFX9) {
/* GFX9 has the layer in out.z[10:0] and the viewport
* index in out.z[19:16].
*/
struct radv_shader_output_values *outputs;
unsigned noutput = 0;
- if (ctx->options->key.has_multiview_view_index) {
+ if (ctx->args->options->key.has_multiview_view_index) {
LLVMValueRef* tmp_out = &ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
if(!*tmp_out) {
for(unsigned i = 0; i < 4; ++i)
ac_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
}
- LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, ctx->abi.view_index), *tmp_out);
+ LLVMValueRef view_index = ac_get_arg(&ctx->ac, ctx->args->ac.view_index);
+ LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, view_index), *tmp_out);
ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
}
sizeof(outinfo->vs_output_param_offset));
outinfo->pos_exports = 0;
- if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
- outinfo->writes_pointsize = true;
- }
-
- if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
- outinfo->writes_layer = true;
- }
-
- if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
- outinfo->writes_viewport_index = true;
- }
-
- if (ctx->shader_info->info.so.num_outputs &&
- !ctx->is_gs_copy_shader) {
+ if (!ctx->args->options->use_ngg_streamout &&
+ ctx->args->shader_info->so.num_outputs &&
+ !ctx->args->is_gs_copy_shader) {
/* The GS copy shader emission already emits streamout. */
radv_emit_streamout(ctx, 0);
}
outputs[noutput].slot_index = i == VARYING_SLOT_CLIP_DIST1;
if (ctx->stage == MESA_SHADER_VERTEX &&
- !ctx->is_gs_copy_shader) {
+ !ctx->args->is_gs_copy_shader) {
outputs[noutput].usage_mask =
- ctx->shader_info->info.vs.output_usage_mask[i];
+ ctx->args->shader_info->vs.output_usage_mask[i];
} else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
outputs[noutput].usage_mask =
- ctx->shader_info->info.tes.output_usage_mask[i];
+ ctx->args->shader_info->tes.output_usage_mask[i];
} else {
- assert(ctx->is_gs_copy_shader || ctx->options->key.vs_common_out.as_ngg);
+ assert(ctx->args->is_gs_copy_shader);
outputs[noutput].usage_mask =
- ctx->shader_info->info.gs.output_usage_mask[i];
+ ctx->args->shader_info->gs.output_usage_mask[i];
}
for (unsigned j = 0; j < 4; j++) {
/* Export PrimitiveID. */
if (export_prim_id) {
- outinfo->export_prim_id = true;
-
outputs[noutput].slot_name = VARYING_SLOT_PRIMITIVE_ID;
outputs[noutput].slot_index = 0;
outputs[noutput].usage_mask = 0x1;
- outputs[noutput].values[0] = ctx->vs_prim_id;
+ outputs[noutput].values[0] =
+ ac_get_arg(&ctx->ac, ctx->args->vs_prim_id);
for (unsigned j = 1; j < 4; j++)
outputs[noutput].values[j] = ctx->ac.f32_0;
noutput++;
struct radv_es_output_info *outinfo)
{
int j;
- uint64_t max_output_written = 0;
LLVMValueRef lds_base = NULL;
- for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
- int param_index;
-
- if (!(ctx->output_mask & (1ull << i)))
- continue;
-
- param_index = shader_io_get_unique_index(i);
-
- max_output_written = MAX2(param_index, max_output_written);
- }
-
- outinfo->esgs_itemsize = (max_output_written + 1) * 16;
-
if (ctx->ac.chip_class >= GFX9) {
unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
- LLVMValueRef wave_idx = ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 24, 4);
+ LLVMValueRef wave_idx =
+ ac_unpack_param(&ctx->ac,
+ ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 24, 4);
vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
LLVMBuildMul(ctx->ac.builder, wave_idx,
- LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
+ LLVMConstInt(ctx->ac.i32,
+ ctx->ac.wave_size, false), ""), "");
lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
}
if (ctx->stage == MESA_SHADER_VERTEX) {
output_usage_mask =
- ctx->shader_info->info.vs.output_usage_mask[i];
+ ctx->args->shader_info->vs.output_usage_mask[i];
} else {
assert(ctx->stage == MESA_SHADER_TESS_EVAL);
output_usage_mask =
- ctx->shader_info->info.tes.output_usage_mask[i];
+ ctx->args->shader_info->tes.output_usage_mask[i];
}
param_index = shader_io_get_unique_index(i);
ac_build_buffer_store_dword(&ctx->ac,
ctx->esgs_ring,
out_val, 1,
- NULL, ctx->es2gs_offset,
+ NULL,
+ ac_get_arg(&ctx->ac, ctx->args->es2gs_offset),
(4 * param_index + j) * 4,
ac_glc | ac_slc, true);
}
handle_ls_outputs_post(struct radv_shader_context *ctx)
{
LLVMValueRef vertex_id = ctx->rel_auto_id;
- uint32_t num_tcs_inputs = util_last_bit64(ctx->shader_info->info.vs.ls_outputs_written);
+ uint32_t num_tcs_inputs = util_last_bit64(ctx->args->shader_info->vs.ls_outputs_written);
LLVMValueRef vertex_dw_stride = LLVMConstInt(ctx->ac.i32, num_tcs_inputs * 4, false);
LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
vertex_dw_stride, "");
static LLVMValueRef get_wave_id_in_tg(struct radv_shader_context *ctx)
{
- return ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 24, 4);
+ return ac_unpack_param(&ctx->ac,
+ ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 24, 4);
}
static LLVMValueRef get_tgsize(struct radv_shader_context *ctx)
{
- return ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 28, 4);
+ return ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 28, 4);
}
static LLVMValueRef get_thread_id_in_tg(struct radv_shader_context *ctx)
LLVMBuilderRef builder = ctx->ac.builder;
LLVMValueRef tmp;
tmp = LLVMBuildMul(builder, get_wave_id_in_tg(ctx),
- LLVMConstInt(ctx->ac.i32, 64, false), "");
+ LLVMConstInt(ctx->ac.i32, ctx->ac.wave_size, false), "");
return LLVMBuildAdd(builder, tmp, ac_get_thread_id(&ctx->ac), "");
}
static LLVMValueRef ngg_get_vtx_cnt(struct radv_shader_context *ctx)
{
- return ac_build_bfe(&ctx->ac, ctx->gs_tg_info,
+ return ac_build_bfe(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_tg_info),
LLVMConstInt(ctx->ac.i32, 12, false),
LLVMConstInt(ctx->ac.i32, 9, false),
false);
static LLVMValueRef ngg_get_prim_cnt(struct radv_shader_context *ctx)
{
- return ac_build_bfe(&ctx->ac, ctx->gs_tg_info,
+ return ac_build_bfe(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_tg_info),
LLVMConstInt(ctx->ac.i32, 22, false),
LLVMConstInt(ctx->ac.i32, 9, false),
false);
}
+static LLVMValueRef ngg_get_ordered_id(struct radv_shader_context *ctx)
+{
+ return ac_build_bfe(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_tg_info),
+ ctx->ac.i32_0,
+ LLVMConstInt(ctx->ac.i32, 11, false),
+ false);
+}
+
static LLVMValueRef
ngg_gs_get_vertex_storage(struct radv_shader_context *ctx)
{
unsigned num_outputs = util_bitcount64(ctx->output_mask);
+ if (ctx->args->options->key.has_multiview_view_index)
+ num_outputs++;
+
LLVMTypeRef elements[2] = {
LLVMArrayType(ctx->ac.i32, 4 * num_outputs),
LLVMArrayType(ctx->ac.i8, 4),
LLVMValueRef storage = ngg_gs_get_vertex_storage(ctx);
/* gs_max_out_vertices = 2^(write_stride_2exp) * some odd number */
- unsigned write_stride_2exp = ffs(ctx->gs_max_out_vertices) - 1;
+ unsigned write_stride_2exp = ffs(ctx->shader->info.gs.vertices_out) - 1;
if (write_stride_2exp) {
LLVMValueRef row =
LLVMBuildLShr(builder, vertexidx,
LLVMBuilderRef builder = ctx->ac.builder;
LLVMValueRef tmp;
- tmp = LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false);
+ tmp = LLVMConstInt(ctx->ac.i32, ctx->shader->info.gs.vertices_out, false);
tmp = LLVMBuildMul(builder, tmp, gsthread, "");
const LLVMValueRef vertexidx = LLVMBuildAdd(builder, tmp, emitidx, "");
return ngg_gs_vertex_ptr(ctx, vertexidx);
struct ngg_prim {
unsigned num_vertices;
LLVMValueRef isnull;
+ LLVMValueRef swap;
LLVMValueRef index[3];
LLVMValueRef edgeflag[3];
};
{
LLVMBuilderRef builder = ctx->ac.builder;
struct ac_export_args args;
+ LLVMValueRef vertices[3];
+ LLVMValueRef odd, even;
LLVMValueRef tmp;
tmp = LLVMBuildZExt(builder, prim->isnull, ctx->ac.i32, "");
args.out[0] = LLVMBuildShl(builder, tmp, LLVMConstInt(ctx->ac.i32, 31, false), "");
for (unsigned i = 0; i < prim->num_vertices; ++i) {
- tmp = LLVMBuildShl(builder, prim->index[i],
- LLVMConstInt(ctx->ac.i32, 10 * i, false), "");
- args.out[0] = LLVMBuildOr(builder, args.out[0], tmp, "");
- tmp = LLVMBuildZExt(builder, prim->edgeflag[i], ctx->ac.i32, "");
- tmp = LLVMBuildShl(builder, tmp,
- LLVMConstInt(ctx->ac.i32, 10 * i + 9, false), "");
- args.out[0] = LLVMBuildOr(builder, args.out[0], tmp, "");
+ tmp = LLVMBuildZExt(builder, prim->edgeflag[i], ctx->ac.i32, "");
+ tmp = LLVMBuildShl(builder, tmp,
+ LLVMConstInt(ctx->ac.i32, 9, false), "");
+ vertices[i] = LLVMBuildOr(builder, prim->index[i], tmp, "");
+ }
+
+ switch (prim->num_vertices) {
+ case 1:
+ args.out[0] = LLVMBuildOr(builder, args.out[0], vertices[0], "");
+ break;
+ case 2:
+ tmp = LLVMBuildShl(builder, vertices[1],
+ LLVMConstInt(ctx->ac.i32, 10, false), "");
+ tmp = LLVMBuildOr(builder, args.out[0], tmp, "");
+ args.out[0] = LLVMBuildOr(builder, tmp, vertices[0], "");
+ break;
+ case 3:
+ /* Swap vertices if needed to follow drawing order. */
+ tmp = LLVMBuildShl(builder, vertices[2],
+ LLVMConstInt(ctx->ac.i32, 20, false), "");
+ even = LLVMBuildOr(builder, args.out[0], tmp, "");
+ tmp = LLVMBuildShl(builder, vertices[1],
+ LLVMConstInt(ctx->ac.i32, 10, false), "");
+ even = LLVMBuildOr(builder, even, tmp, "");
+ even = LLVMBuildOr(builder, even, vertices[0], "");
+
+ tmp = LLVMBuildShl(builder, vertices[1],
+ LLVMConstInt(ctx->ac.i32, 20, false), "");
+ odd = LLVMBuildOr(builder, args.out[0], tmp, "");
+ tmp = LLVMBuildShl(builder, vertices[2],
+ LLVMConstInt(ctx->ac.i32, 10, false), "");
+ odd = LLVMBuildOr(builder, odd, tmp, "");
+ odd = LLVMBuildOr(builder, odd, vertices[0], "");
+
+ args.out[0] = LLVMBuildSelect(builder, prim->swap, odd, even, "");
+ break;
+ default:
+ unreachable("invalid number of vertices");
}
args.out[0] = LLVMBuildBitCast(builder, args.out[0], ctx->ac.f32, "");
ac_build_export(&ctx->ac, &args);
}
-static void
-handle_ngg_outputs_post(struct radv_shader_context *ctx)
+static struct radv_stream_output *
+radv_get_stream_output_by_loc(struct radv_streamout_info *so, unsigned location)
+{
+ for (unsigned i = 0; i < so->num_outputs; ++i) {
+ if (so->outputs[i].location == location)
+ return &so->outputs[i];
+ }
+
+ return NULL;
+}
+
+static void build_streamout_vertex(struct radv_shader_context *ctx,
+ LLVMValueRef *so_buffer, LLVMValueRef *wg_offset_dw,
+ unsigned stream, LLVMValueRef offset_vtx,
+ LLVMValueRef vertexptr)
{
+ struct radv_streamout_info *so = &ctx->args->shader_info->so;
LLVMBuilderRef builder = ctx->ac.builder;
- struct ac_build_if_state if_state;
- unsigned num_vertices = 3;
+ LLVMValueRef offset[4] = {};
LLVMValueRef tmp;
- assert((ctx->stage == MESA_SHADER_VERTEX ||
- ctx->stage == MESA_SHADER_TESS_EVAL) && !ctx->is_gs_copy_shader);
+ for (unsigned buffer = 0; buffer < 4; ++buffer) {
+ if (!wg_offset_dw[buffer])
+ continue;
- LLVMValueRef prims_in_wave = ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 8, 8);
- LLVMValueRef vtx_in_wave = ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 0, 8);
- LLVMValueRef is_gs_thread = LLVMBuildICmp(builder, LLVMIntULT,
- ac_get_thread_id(&ctx->ac), prims_in_wave, "");
+ tmp = LLVMBuildMul(builder, offset_vtx,
+ LLVMConstInt(ctx->ac.i32, so->strides[buffer], false), "");
+ tmp = LLVMBuildAdd(builder, wg_offset_dw[buffer], tmp, "");
+ offset[buffer] = LLVMBuildShl(builder, tmp, LLVMConstInt(ctx->ac.i32, 2, false), "");
+ }
+
+ if (ctx->stage == MESA_SHADER_GEOMETRY) {
+ struct radv_shader_output_values outputs[AC_LLVM_MAX_OUTPUTS];
+ unsigned noutput = 0;
+ unsigned out_idx = 0;
+
+ for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
+ unsigned output_usage_mask =
+ ctx->args->shader_info->gs.output_usage_mask[i];
+ uint8_t output_stream =
+ output_stream = ctx->args->shader_info->gs.output_streams[i];
+
+ if (!(ctx->output_mask & (1ull << i)) ||
+ output_stream != stream)
+ continue;
+
+ outputs[noutput].slot_name = i;
+ outputs[noutput].slot_index = i == VARYING_SLOT_CLIP_DIST1;
+ outputs[noutput].usage_mask = output_usage_mask;
+
+ int length = util_last_bit(output_usage_mask);
+
+ for (unsigned j = 0; j < length; j++, out_idx++) {
+ if (!(output_usage_mask & (1 << j)))
+ continue;
+
+ tmp = ac_build_gep0(&ctx->ac, vertexptr,
+ LLVMConstInt(ctx->ac.i32, out_idx, false));
+ outputs[noutput].values[j] = LLVMBuildLoad(builder, tmp, "");
+ }
+
+ for (unsigned j = length; j < 4; j++)
+ outputs[noutput].values[j] = LLVMGetUndef(ctx->ac.f32);
+
+ noutput++;
+ }
+
+ for (unsigned i = 0; i < noutput; i++) {
+ struct radv_stream_output *output =
+ radv_get_stream_output_by_loc(so, outputs[i].slot_name);
+
+ if (!output ||
+ output->stream != stream)
+ continue;
+
+ struct radv_shader_output_values out = {};
+
+ for (unsigned j = 0; j < 4; j++) {
+ out.values[j] = outputs[i].values[j];
+ }
+
+ radv_emit_stream_output(ctx, so_buffer, offset, output, &out);
+ }
+ } else {
+ for (unsigned i = 0; i < so->num_outputs; ++i) {
+ struct radv_stream_output *output =
+ &ctx->args->shader_info->so.outputs[i];
+
+ if (stream != output->stream)
+ continue;
+
+ struct radv_shader_output_values out = {};
+
+ for (unsigned comp = 0; comp < 4; comp++) {
+ if (!(output->component_mask & (1 << comp)))
+ continue;
+
+ tmp = ac_build_gep0(&ctx->ac, vertexptr,
+ LLVMConstInt(ctx->ac.i32, 4 * i + comp, false));
+ out.values[comp] = LLVMBuildLoad(builder, tmp, "");
+ }
+
+ radv_emit_stream_output(ctx, so_buffer, offset, output, &out);
+ }
+ }
+}
+
+struct ngg_streamout {
+ LLVMValueRef num_vertices;
+
+ /* per-thread data */
+ LLVMValueRef prim_enable[4]; /* i1 per stream */
+ LLVMValueRef vertices[3]; /* [N x i32] addrspace(LDS)* */
+
+ /* Output */
+ LLVMValueRef emit[4]; /* per-stream emitted primitives (only valid for used streams) */
+};
+
+/**
+ * Build streamout logic.
+ *
+ * Implies a barrier.
+ *
+ * Writes number of emitted primitives to gs_ngg_scratch[4:7].
+ *
+ * Clobbers gs_ngg_scratch[8:].
+ */
+static void build_streamout(struct radv_shader_context *ctx,
+ struct ngg_streamout *nggso)
+{
+ struct radv_streamout_info *so = &ctx->args->shader_info->so;
+ LLVMBuilderRef builder = ctx->ac.builder;
+ LLVMValueRef buf_ptr = ac_get_arg(&ctx->ac, ctx->args->streamout_buffers);
+ LLVMValueRef tid = get_thread_id_in_tg(ctx);
+ LLVMValueRef cond, tmp, tmp2;
+ LLVMValueRef i32_2 = LLVMConstInt(ctx->ac.i32, 2, false);
+ LLVMValueRef i32_4 = LLVMConstInt(ctx->ac.i32, 4, false);
+ LLVMValueRef i32_8 = LLVMConstInt(ctx->ac.i32, 8, false);
+ LLVMValueRef so_buffer[4] = {};
+ unsigned max_num_vertices = 1 + (nggso->vertices[1] ? 1 : 0) +
+ (nggso->vertices[2] ? 1 : 0);
+ LLVMValueRef prim_stride_dw[4] = {};
+ LLVMValueRef prim_stride_dw_vgpr = LLVMGetUndef(ctx->ac.i32);
+ int stream_for_buffer[4] = { -1, -1, -1, -1 };
+ unsigned bufmask_for_stream[4] = {};
+ bool isgs = ctx->stage == MESA_SHADER_GEOMETRY;
+ unsigned scratch_emit_base = isgs ? 4 : 0;
+ LLVMValueRef scratch_emit_basev = isgs ? i32_4 : ctx->ac.i32_0;
+ unsigned scratch_offset_base = isgs ? 8 : 4;
+ LLVMValueRef scratch_offset_basev = isgs ? i32_8 : i32_4;
+
+ ac_llvm_add_target_dep_function_attr(ctx->main_function,
+ "amdgpu-gds-size", 256);
+
+ /* Determine the mapping of streamout buffers to vertex streams. */
+ for (unsigned i = 0; i < so->num_outputs; ++i) {
+ unsigned buf = so->outputs[i].buffer;
+ unsigned stream = so->outputs[i].stream;
+ assert(stream_for_buffer[buf] < 0 || stream_for_buffer[buf] == stream);
+ stream_for_buffer[buf] = stream;
+ bufmask_for_stream[stream] |= 1 << buf;
+ }
+
+ for (unsigned buffer = 0; buffer < 4; ++buffer) {
+ if (stream_for_buffer[buffer] == -1)
+ continue;
+
+ assert(so->strides[buffer]);
+
+ LLVMValueRef stride_for_buffer =
+ LLVMConstInt(ctx->ac.i32, so->strides[buffer], false);
+ prim_stride_dw[buffer] =
+ LLVMBuildMul(builder, stride_for_buffer,
+ nggso->num_vertices, "");
+ prim_stride_dw_vgpr = ac_build_writelane(
+ &ctx->ac, prim_stride_dw_vgpr, prim_stride_dw[buffer],
+ LLVMConstInt(ctx->ac.i32, buffer, false));
+
+ LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, buffer, false);
+ so_buffer[buffer] = ac_build_load_to_sgpr(&ctx->ac, buf_ptr,
+ offset);
+ }
+
+ cond = LLVMBuildICmp(builder, LLVMIntEQ, get_wave_id_in_tg(ctx), ctx->ac.i32_0, "");
+ ac_build_ifcc(&ctx->ac, cond, 5200);
+ {
+ LLVMTypeRef gdsptr = LLVMPointerType(ctx->ac.i32, AC_ADDR_SPACE_GDS);
+ LLVMValueRef gdsbase = LLVMBuildIntToPtr(builder, ctx->ac.i32_0, gdsptr, "");
+
+ /* Advance the streamout offsets in GDS. */
+ LLVMValueRef offsets_vgpr = ac_build_alloca_undef(&ctx->ac, ctx->ac.i32, "");
+ LLVMValueRef generated_by_stream_vgpr = ac_build_alloca_undef(&ctx->ac, ctx->ac.i32, "");
+
+ cond = LLVMBuildICmp(builder, LLVMIntULT, ac_get_thread_id(&ctx->ac), i32_4, "");
+ ac_build_ifcc(&ctx->ac, cond, 5210);
+ {
+ /* Fetch the number of generated primitives and store
+ * it in GDS for later use.
+ */
+ if (isgs) {
+ tmp = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, tid);
+ tmp = LLVMBuildLoad(builder, tmp, "");
+ } else {
+ tmp = ac_build_writelane(&ctx->ac, ctx->ac.i32_0,
+ ngg_get_prim_cnt(ctx), ctx->ac.i32_0);
+ }
+ LLVMBuildStore(builder, tmp, generated_by_stream_vgpr);
+
+ unsigned swizzle[4];
+ int unused_stream = -1;
+ for (unsigned stream = 0; stream < 4; ++stream) {
+ if (!ctx->args->shader_info->gs.num_stream_output_components[stream]) {
+ unused_stream = stream;
+ break;
+ }
+ }
+ for (unsigned buffer = 0; buffer < 4; ++buffer) {
+ if (stream_for_buffer[buffer] >= 0) {
+ swizzle[buffer] = stream_for_buffer[buffer];
+ } else {
+ assert(unused_stream >= 0);
+ swizzle[buffer] = unused_stream;
+ }
+ }
+
+ tmp = ac_build_quad_swizzle(&ctx->ac, tmp,
+ swizzle[0], swizzle[1], swizzle[2], swizzle[3]);
+ tmp = LLVMBuildMul(builder, tmp, prim_stride_dw_vgpr, "");
+
+ LLVMValueRef args[] = {
+ LLVMBuildIntToPtr(builder, ngg_get_ordered_id(ctx), gdsptr, ""),
+ tmp,
+ ctx->ac.i32_0, // ordering
+ ctx->ac.i32_0, // scope
+ ctx->ac.i1false, // isVolatile
+ LLVMConstInt(ctx->ac.i32, 4 << 24, false), // OA index
+ ctx->ac.i1true, // wave release
+ ctx->ac.i1true, // wave done
+ };
+
+ tmp = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.ds.ordered.add",
+ ctx->ac.i32, args, ARRAY_SIZE(args), 0);
+
+ /* Keep offsets in a VGPR for quick retrieval via readlane by
+ * the first wave for bounds checking, and also store in LDS
+ * for retrieval by all waves later. */
+ LLVMBuildStore(builder, tmp, offsets_vgpr);
+
+ tmp2 = LLVMBuildAdd(builder, ac_get_thread_id(&ctx->ac),
+ scratch_offset_basev, "");
+ tmp2 = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, tmp2);
+ LLVMBuildStore(builder, tmp, tmp2);
+ }
+ ac_build_endif(&ctx->ac, 5210);
+
+ /* Determine the max emit per buffer. This is done via the SALU, in part
+ * because LLVM can't generate divide-by-multiply if we try to do this
+ * via VALU with one lane per buffer.
+ */
+ LLVMValueRef max_emit[4] = {};
+ for (unsigned buffer = 0; buffer < 4; ++buffer) {
+ if (stream_for_buffer[buffer] == -1)
+ continue;
+
+ /* Compute the streamout buffer size in DWORD. */
+ LLVMValueRef bufsize_dw =
+ LLVMBuildLShr(builder,
+ LLVMBuildExtractElement(builder, so_buffer[buffer], i32_2, ""),
+ i32_2, "");
+
+ /* Load the streamout buffer offset from GDS. */
+ tmp = LLVMBuildLoad(builder, offsets_vgpr, "");
+ LLVMValueRef offset_dw =
+ ac_build_readlane(&ctx->ac, tmp,
+ LLVMConstInt(ctx->ac.i32, buffer, false));
+
+ /* Compute the remaining size to emit. */
+ LLVMValueRef remaining_dw =
+ LLVMBuildSub(builder, bufsize_dw, offset_dw, "");
+ tmp = LLVMBuildUDiv(builder, remaining_dw,
+ prim_stride_dw[buffer], "");
+
+ cond = LLVMBuildICmp(builder, LLVMIntULT,
+ bufsize_dw, offset_dw, "");
+ max_emit[buffer] = LLVMBuildSelect(builder, cond,
+ ctx->ac.i32_0, tmp, "");
+ }
+
+ /* Determine the number of emitted primitives per stream and fixup the
+ * GDS counter if necessary.
+ *
+ * This is complicated by the fact that a single stream can emit to
+ * multiple buffers (but luckily not vice versa).
+ */
+ LLVMValueRef emit_vgpr = ctx->ac.i32_0;
+
+ for (unsigned stream = 0; stream < 4; ++stream) {
+ if (!ctx->args->shader_info->gs.num_stream_output_components[stream])
+ continue;
+
+ /* Load the number of generated primitives from GDS and
+ * determine that number for the given stream.
+ */
+ tmp = LLVMBuildLoad(builder, generated_by_stream_vgpr, "");
+ LLVMValueRef generated =
+ ac_build_readlane(&ctx->ac, tmp,
+ LLVMConstInt(ctx->ac.i32, stream, false));
+
+
+ /* Compute the number of emitted primitives. */
+ LLVMValueRef emit = generated;
+ for (unsigned buffer = 0; buffer < 4; ++buffer) {
+ if (stream_for_buffer[buffer] == stream)
+ emit = ac_build_umin(&ctx->ac, emit, max_emit[buffer]);
+ }
+
+ /* Store the number of emitted primitives for that
+ * stream.
+ */
+ emit_vgpr = ac_build_writelane(&ctx->ac, emit_vgpr, emit,
+ LLVMConstInt(ctx->ac.i32, stream, false));
+
+ /* Fixup the offset using a plain GDS atomic if we overflowed. */
+ cond = LLVMBuildICmp(builder, LLVMIntULT, emit, generated, "");
+ ac_build_ifcc(&ctx->ac, cond, 5221); /* scalar branch */
+ tmp = LLVMBuildLShr(builder,
+ LLVMConstInt(ctx->ac.i32, bufmask_for_stream[stream], false),
+ ac_get_thread_id(&ctx->ac), "");
+ tmp = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
+ ac_build_ifcc(&ctx->ac, tmp, 5222);
+ {
+ tmp = LLVMBuildSub(builder, generated, emit, "");
+ tmp = LLVMBuildMul(builder, tmp, prim_stride_dw_vgpr, "");
+ tmp2 = LLVMBuildGEP(builder, gdsbase, &tid, 1, "");
+ LLVMBuildAtomicRMW(builder, LLVMAtomicRMWBinOpSub, tmp2, tmp,
+ LLVMAtomicOrderingMonotonic, false);
+ }
+ ac_build_endif(&ctx->ac, 5222);
+ ac_build_endif(&ctx->ac, 5221);
+ }
+
+ /* Store the number of emitted primitives to LDS for later use. */
+ cond = LLVMBuildICmp(builder, LLVMIntULT, ac_get_thread_id(&ctx->ac), i32_4, "");
+ ac_build_ifcc(&ctx->ac, cond, 5225);
+ {
+ tmp = LLVMBuildAdd(builder, ac_get_thread_id(&ctx->ac),
+ scratch_emit_basev, "");
+ tmp = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, tmp);
+ LLVMBuildStore(builder, emit_vgpr, tmp);
+ }
+ ac_build_endif(&ctx->ac, 5225);
+ }
+ ac_build_endif(&ctx->ac, 5200);
+
+ /* Determine the workgroup-relative per-thread / primitive offset into
+ * the streamout buffers */
+ struct ac_wg_scan primemit_scan[4] = {};
+
+ if (isgs) {
+ for (unsigned stream = 0; stream < 4; ++stream) {
+ if (!ctx->args->shader_info->gs.num_stream_output_components[stream])
+ continue;
+
+ primemit_scan[stream].enable_exclusive = true;
+ primemit_scan[stream].op = nir_op_iadd;
+ primemit_scan[stream].src = nggso->prim_enable[stream];
+ primemit_scan[stream].scratch =
+ ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch,
+ LLVMConstInt(ctx->ac.i32, 12 + 8 * stream, false));
+ primemit_scan[stream].waveidx = get_wave_id_in_tg(ctx);
+ primemit_scan[stream].numwaves = get_tgsize(ctx);
+ primemit_scan[stream].maxwaves = 8;
+ ac_build_wg_scan_top(&ctx->ac, &primemit_scan[stream]);
+ }
+ }
+
+ ac_build_s_barrier(&ctx->ac);
+
+ /* Fetch the per-buffer offsets and per-stream emit counts in all waves. */
+ LLVMValueRef wgoffset_dw[4] = {};
+
+ {
+ LLVMValueRef scratch_vgpr;
+
+ tmp = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, ac_get_thread_id(&ctx->ac));
+ scratch_vgpr = LLVMBuildLoad(builder, tmp, "");
+
+ for (unsigned buffer = 0; buffer < 4; ++buffer) {
+ if (stream_for_buffer[buffer] >= 0) {
+ wgoffset_dw[buffer] = ac_build_readlane(
+ &ctx->ac, scratch_vgpr,
+ LLVMConstInt(ctx->ac.i32, scratch_offset_base + buffer, false));
+ }
+ }
+
+ for (unsigned stream = 0; stream < 4; ++stream) {
+ if (ctx->args->shader_info->gs.num_stream_output_components[stream]) {
+ nggso->emit[stream] = ac_build_readlane(
+ &ctx->ac, scratch_vgpr,
+ LLVMConstInt(ctx->ac.i32, scratch_emit_base + stream, false));
+ }
+ }
+ }
+
+ /* Write out primitive data */
+ for (unsigned stream = 0; stream < 4; ++stream) {
+ if (!ctx->args->shader_info->gs.num_stream_output_components[stream])
+ continue;
+
+ if (isgs) {
+ ac_build_wg_scan_bottom(&ctx->ac, &primemit_scan[stream]);
+ } else {
+ primemit_scan[stream].result_exclusive = tid;
+ }
+
+ cond = LLVMBuildICmp(builder, LLVMIntULT,
+ primemit_scan[stream].result_exclusive,
+ nggso->emit[stream], "");
+ cond = LLVMBuildAnd(builder, cond, nggso->prim_enable[stream], "");
+ ac_build_ifcc(&ctx->ac, cond, 5240);
+ {
+ LLVMValueRef offset_vtx =
+ LLVMBuildMul(builder, primemit_scan[stream].result_exclusive,
+ nggso->num_vertices, "");
+
+ for (unsigned i = 0; i < max_num_vertices; ++i) {
+ cond = LLVMBuildICmp(builder, LLVMIntULT,
+ LLVMConstInt(ctx->ac.i32, i, false),
+ nggso->num_vertices, "");
+ ac_build_ifcc(&ctx->ac, cond, 5241);
+ build_streamout_vertex(ctx, so_buffer, wgoffset_dw,
+ stream, offset_vtx, nggso->vertices[i]);
+ ac_build_endif(&ctx->ac, 5241);
+ offset_vtx = LLVMBuildAdd(builder, offset_vtx, ctx->ac.i32_1, "");
+ }
+ }
+ ac_build_endif(&ctx->ac, 5240);
+ }
+}
+
+static unsigned ngg_nogs_vertex_size(struct radv_shader_context *ctx)
+{
+ unsigned lds_vertex_size = 0;
+
+ if (ctx->args->shader_info->so.num_outputs)
+ lds_vertex_size = 4 * ctx->args->shader_info->so.num_outputs + 1;
+
+ return lds_vertex_size;
+}
+
+/**
+ * Returns an `[N x i32] addrspace(LDS)*` pointing at contiguous LDS storage
+ * for the vertex outputs.
+ */
+static LLVMValueRef ngg_nogs_vertex_ptr(struct radv_shader_context *ctx,
+ LLVMValueRef vtxid)
+{
+ /* The extra dword is used to avoid LDS bank conflicts. */
+ unsigned vertex_size = ngg_nogs_vertex_size(ctx);
+ LLVMTypeRef ai32 = LLVMArrayType(ctx->ac.i32, vertex_size);
+ LLVMTypeRef pai32 = LLVMPointerType(ai32, AC_ADDR_SPACE_LDS);
+ LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, ctx->esgs_ring, pai32, "");
+ return LLVMBuildGEP(ctx->ac.builder, tmp, &vtxid, 1, "");
+}
+
+static void
+handle_ngg_outputs_post_1(struct radv_shader_context *ctx)
+{
+ struct radv_streamout_info *so = &ctx->args->shader_info->so;
+ LLVMBuilderRef builder = ctx->ac.builder;
+ LLVMValueRef vertex_ptr = NULL;
+ LLVMValueRef tmp, tmp2;
+
+ assert((ctx->stage == MESA_SHADER_VERTEX ||
+ ctx->stage == MESA_SHADER_TESS_EVAL) && !ctx->args->is_gs_copy_shader);
+
+ if (!ctx->args->shader_info->so.num_outputs)
+ return;
+
+ vertex_ptr = ngg_nogs_vertex_ptr(ctx, get_thread_id_in_tg(ctx));
+
+ for (unsigned i = 0; i < so->num_outputs; ++i) {
+ struct radv_stream_output *output =
+ &ctx->args->shader_info->so.outputs[i];
+
+ unsigned loc = output->location;
+
+ for (unsigned comp = 0; comp < 4; comp++) {
+ if (!(output->component_mask & (1 << comp)))
+ continue;
+
+ tmp = ac_build_gep0(&ctx->ac, vertex_ptr,
+ LLVMConstInt(ctx->ac.i32, 4 * i + comp, false));
+ tmp2 = LLVMBuildLoad(builder,
+ ctx->abi.outputs[4 * loc + comp], "");
+ tmp2 = ac_to_integer(&ctx->ac, tmp2);
+ LLVMBuildStore(builder, tmp2, tmp);
+ }
+ }
+}
+
+static void
+handle_ngg_outputs_post_2(struct radv_shader_context *ctx)
+{
+ LLVMBuilderRef builder = ctx->ac.builder;
+ LLVMValueRef tmp;
+
+ assert((ctx->stage == MESA_SHADER_VERTEX ||
+ ctx->stage == MESA_SHADER_TESS_EVAL) && !ctx->args->is_gs_copy_shader);
+
+ LLVMValueRef prims_in_wave = ac_unpack_param(&ctx->ac,
+ ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 8, 8);
+ LLVMValueRef vtx_in_wave = ac_unpack_param(&ctx->ac,
+ ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 0, 8);
+ LLVMValueRef is_gs_thread = LLVMBuildICmp(builder, LLVMIntULT,
+ ac_get_thread_id(&ctx->ac), prims_in_wave, "");
LLVMValueRef is_es_thread = LLVMBuildICmp(builder, LLVMIntULT,
ac_get_thread_id(&ctx->ac), vtx_in_wave, "");
LLVMValueRef vtxindex[] = {
- ac_unpack_param(&ctx->ac, ctx->gs_vtx_offset[0], 0, 16),
- ac_unpack_param(&ctx->ac, ctx->gs_vtx_offset[0], 16, 16),
- ac_unpack_param(&ctx->ac, ctx->gs_vtx_offset[2], 0, 16),
+ ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[0]), 0, 16),
+ ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[0]), 16, 16),
+ ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[2]), 0, 16),
};
- /* TODO: streamout */
+ /* Determine the number of vertices per primitive. */
+ unsigned num_vertices;
+ LLVMValueRef num_vertices_val;
+
+ if (ctx->stage == MESA_SHADER_VERTEX) {
+ LLVMValueRef outprim_val =
+ LLVMConstInt(ctx->ac.i32,
+ ctx->args->options->key.vs.outprim, false);
+ num_vertices_val = LLVMBuildAdd(builder, outprim_val,
+ ctx->ac.i32_1, "");
+ num_vertices = 3; /* TODO: optimize for points & lines */
+ } else {
+ assert(ctx->stage == MESA_SHADER_TESS_EVAL);
+
+ if (ctx->shader->info.tess.point_mode)
+ num_vertices = 1;
+ else if (ctx->shader->info.tess.primitive_mode == GL_ISOLINES)
+ num_vertices = 2;
+ else
+ num_vertices = 3;
+
+ num_vertices_val = LLVMConstInt(ctx->ac.i32, num_vertices, false);
+ }
+
+ /* Streamout */
+ if (ctx->args->shader_info->so.num_outputs) {
+ struct ngg_streamout nggso = {};
- /* TODO: VS primitive ID */
- if (ctx->options->key.vs_common_out.export_prim_id)
- assert(0);
+ nggso.num_vertices = num_vertices_val;
+ nggso.prim_enable[0] = is_gs_thread;
+
+ for (unsigned i = 0; i < num_vertices; ++i)
+ nggso.vertices[i] = ngg_nogs_vertex_ptr(ctx, vtxindex[i]);
+
+ build_streamout(ctx, &nggso);
+ }
+
+ /* Copy Primitive IDs from GS threads to the LDS address corresponding
+ * to the ES thread of the provoking vertex.
+ */
+ if (ctx->stage == MESA_SHADER_VERTEX &&
+ ctx->args->options->key.vs_common_out.export_prim_id) {
+ if (ctx->args->shader_info->so.num_outputs)
+ ac_build_s_barrier(&ctx->ac);
+
+ ac_build_ifcc(&ctx->ac, is_gs_thread, 5400);
+ /* Extract the PROVOKING_VTX_INDEX field. */
+ LLVMValueRef provoking_vtx_in_prim =
+ LLVMConstInt(ctx->ac.i32, 0, false);
+
+ /* provoking_vtx_index = vtxindex[provoking_vtx_in_prim]; */
+ LLVMValueRef indices = ac_build_gather_values(&ctx->ac, vtxindex, 3);
+ LLVMValueRef provoking_vtx_index =
+ LLVMBuildExtractElement(builder, indices, provoking_vtx_in_prim, "");
+
+ LLVMBuildStore(builder, ac_get_arg(&ctx->ac, ctx->args->ac.gs_prim_id),
+ ac_build_gep0(&ctx->ac, ctx->esgs_ring, provoking_vtx_index));
+ ac_build_endif(&ctx->ac, 5400);
+ }
/* TODO: primitive culling */
* TODO: culling depends on the primitive type, so can have some
* interaction here.
*/
- ac_nir_build_if(&if_state, ctx, is_gs_thread);
+ ac_build_ifcc(&ctx->ac, is_gs_thread, 6001);
{
struct ngg_prim prim = {};
prim.num_vertices = num_vertices;
prim.isnull = ctx->ac.i1false;
+ prim.swap = ctx->ac.i1false;
memcpy(prim.index, vtxindex, sizeof(vtxindex[0]) * 3);
for (unsigned i = 0; i < num_vertices; ++i) {
- tmp = LLVMBuildLShr(builder, ctx->abi.gs_invocation_id,
+ tmp = LLVMBuildLShr(builder,
+ ac_get_arg(&ctx->ac, ctx->args->ac.gs_invocation_id),
LLVMConstInt(ctx->ac.i32, 8 + i, false), "");
prim.edgeflag[i] = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
}
build_export_prim(ctx, &prim);
}
- ac_nir_build_endif(&if_state);
+ ac_build_endif(&ctx->ac, 6001);
/* Export per-vertex data (positions and parameters). */
- ac_nir_build_if(&if_state, ctx, is_es_thread);
+ ac_build_ifcc(&ctx->ac, is_es_thread, 6002);
{
- handle_vs_outputs_post(ctx, ctx->options->key.vs_common_out.export_prim_id,
- ctx->options->key.vs_common_out.export_clip_dists,
- ctx->stage == MESA_SHADER_TESS_EVAL ? &ctx->shader_info->tes.outinfo : &ctx->shader_info->vs.outinfo);
+ struct radv_vs_output_info *outinfo =
+ ctx->stage == MESA_SHADER_TESS_EVAL ?
+ &ctx->args->shader_info->tes.outinfo : &ctx->args->shader_info->vs.outinfo;
+
+ /* Exporting the primitive ID is handled below. */
+ /* TODO: use the new VS export path */
+ handle_vs_outputs_post(ctx, false,
+ ctx->args->options->key.vs_common_out.export_clip_dists,
+ outinfo);
+
+ if (ctx->args->options->key.vs_common_out.export_prim_id) {
+ unsigned param_count = outinfo->param_exports;
+ LLVMValueRef values[4];
+
+ if (ctx->stage == MESA_SHADER_VERTEX) {
+ /* Wait for GS stores to finish. */
+ ac_build_s_barrier(&ctx->ac);
+
+ tmp = ac_build_gep0(&ctx->ac, ctx->esgs_ring,
+ get_thread_id_in_tg(ctx));
+ values[0] = LLVMBuildLoad(builder, tmp, "");
+ } else {
+ assert(ctx->stage == MESA_SHADER_TESS_EVAL);
+ values[0] = ac_get_arg(&ctx->ac, ctx->args->ac.tes_patch_id);
+ }
+
+ values[0] = ac_to_float(&ctx->ac, values[0]);
+ for (unsigned j = 1; j < 4; j++)
+ values[j] = ctx->ac.f32_0;
+
+ radv_export_param(ctx, param_count, values, 0x1);
+
+ outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
+ outinfo->param_exports = param_count;
+ }
}
- ac_nir_build_endif(&if_state);
+ ac_build_endif(&ctx->ac, 6002);
}
static void gfx10_ngg_gs_emit_prologue(struct radv_shader_context *ctx)
LLVMBuilderRef builder = ctx->ac.builder;
LLVMValueRef scratchptr = ctx->gs_ngg_scratch;
LLVMValueRef tid = get_thread_id_in_tg(ctx);
- LLVMValueRef tmp;
+ LLVMBasicBlockRef merge_block;
+ LLVMValueRef cond;
- tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, LLVMConstInt(ctx->ac.i32, 4, false), "");
- ac_build_ifcc(&ctx->ac, tmp, 5090);
- {
- LLVMValueRef ptr = ac_build_gep0(&ctx->ac, scratchptr, tid);
- LLVMBuildStore(builder, ctx->ac.i32_0, ptr);
- }
- ac_build_endif(&ctx->ac, 5090);
+ LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
+ LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
+ merge_block = LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
+
+ cond = LLVMBuildICmp(builder, LLVMIntULT, tid, LLVMConstInt(ctx->ac.i32, 4, false), "");
+ LLVMBuildCondBr(ctx->ac.builder, cond, then_block, merge_block);
+ LLVMPositionBuilderAtEnd(ctx->ac.builder, then_block);
+
+ LLVMValueRef ptr = ac_build_gep0(&ctx->ac, scratchptr, tid);
+ LLVMBuildStore(builder, ctx->ac.i32_0, ptr);
+
+ LLVMBuildBr(ctx->ac.builder, merge_block);
+ LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
ac_build_s_barrier(&ctx->ac);
}
unsigned num_components;
num_components =
- ctx->shader_info->info.gs.num_stream_output_components[stream];
+ ctx->args->shader_info->gs.num_stream_output_components[stream];
if (!num_components)
continue;
const LLVMValueRef vertexidx =
LLVMBuildLoad(builder, ctx->gs_next_vertex[stream], "");
tmp = LLVMBuildICmp(builder, LLVMIntUGE, vertexidx,
- LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
+ LLVMConstInt(ctx->ac.i32, ctx->shader->info.gs.vertices_out, false), "");
ac_build_ifcc(&ctx->ac, tmp, 5101);
ac_build_break(&ctx->ac);
ac_build_endif(&ctx->ac, 5101);
ac_build_endloop(&ctx->ac, 5100);
}
+
+ /* Accumulate generated primitives counts across the entire threadgroup. */
+ for (unsigned stream = 0; stream < 4; ++stream) {
+ unsigned num_components;
+
+ num_components =
+ ctx->args->shader_info->gs.num_stream_output_components[stream];
+ if (!num_components)
+ continue;
+
+ LLVMValueRef numprims =
+ LLVMBuildLoad(builder, ctx->gs_generated_prims[stream], "");
+ numprims = ac_build_reduce(&ctx->ac, numprims, nir_op_iadd, ctx->ac.wave_size);
+
+ tmp = LLVMBuildICmp(builder, LLVMIntEQ, ac_get_thread_id(&ctx->ac), ctx->ac.i32_0, "");
+ ac_build_ifcc(&ctx->ac, tmp, 5105);
+ {
+ LLVMBuildAtomicRMW(builder, LLVMAtomicRMWBinOpAdd,
+ ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch,
+ LLVMConstInt(ctx->ac.i32, stream, false)),
+ numprims, LLVMAtomicOrderingMonotonic, false);
+ }
+ ac_build_endif(&ctx->ac, 5105);
+ }
}
static void gfx10_ngg_gs_emit_epilogue_2(struct radv_shader_context *ctx)
{
- const unsigned verts_per_prim = si_conv_gl_prim_to_vertices(ctx->gs_output_prim);
+ const unsigned verts_per_prim = si_conv_gl_prim_to_vertices(ctx->shader->info.gs.output_primitive);
LLVMBuilderRef builder = ctx->ac.builder;
LLVMValueRef tmp, tmp2;
const LLVMValueRef tid = get_thread_id_in_tg(ctx);
LLVMValueRef num_emit_threads = ngg_get_prim_cnt(ctx);
- /* TODO: streamout */
+ /* Streamout */
+ if (ctx->args->shader_info->so.num_outputs) {
+ struct ngg_streamout nggso = {};
+
+ nggso.num_vertices = LLVMConstInt(ctx->ac.i32, verts_per_prim, false);
+
+ LLVMValueRef vertexptr = ngg_gs_vertex_ptr(ctx, tid);
+ for (unsigned stream = 0; stream < 4; ++stream) {
+ if (!ctx->args->shader_info->gs.num_stream_output_components[stream])
+ continue;
+
+ LLVMValueRef gep_idx[3] = {
+ ctx->ac.i32_0, /* implicit C-style array */
+ ctx->ac.i32_1, /* second value of struct */
+ LLVMConstInt(ctx->ac.i32, stream, false),
+ };
+ tmp = LLVMBuildGEP(builder, vertexptr, gep_idx, 3, "");
+ tmp = LLVMBuildLoad(builder, tmp, "");
+ tmp = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
+ tmp2 = LLVMBuildICmp(builder, LLVMIntULT, tid, num_emit_threads, "");
+ nggso.prim_enable[stream] = LLVMBuildAnd(builder, tmp, tmp2, "");
+ }
+
+ for (unsigned i = 0; i < verts_per_prim; ++i) {
+ tmp = LLVMBuildSub(builder, tid,
+ LLVMConstInt(ctx->ac.i32, verts_per_prim - i - 1, false), "");
+ tmp = ngg_gs_vertex_ptr(ctx, tmp);
+ nggso.vertices[i] = ac_build_gep0(&ctx->ac, tmp, ctx->ac.i32_0);
+ }
+
+ build_streamout(ctx, &nggso);
+ }
/* TODO: culling */
tmp = LLVMBuildLoad(builder, tmp, "");
prim.isnull = LLVMBuildICmp(builder, LLVMIntEQ, tmp,
LLVMConstInt(ctx->ac.i8, 0, false), "");
+ prim.swap = LLVMBuildICmp(builder, LLVMIntEQ,
+ LLVMBuildAnd(builder, tid, LLVMConstInt(ctx->ac.i32, 1, false), ""),
+ LLVMConstInt(ctx->ac.i32, 1, false), "");
for (unsigned i = 0; i < verts_per_prim; ++i) {
prim.index[i] = LLVMBuildSub(builder, vertlive_scan.result_exclusive,
tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, vertlive_scan.result_reduce, "");
ac_build_ifcc(&ctx->ac, tmp, 5145);
{
- struct radv_vs_output_info *outinfo = &ctx->shader_info->vs.outinfo;
- bool export_view_index = ctx->options->key.has_multiview_view_index;
+ struct radv_vs_output_info *outinfo = &ctx->args->shader_info->vs.outinfo;
+ bool export_view_index = ctx->args->options->key.has_multiview_view_index;
struct radv_shader_output_values *outputs;
unsigned noutput = 0;
tmp = LLVMBuildZExt(builder, tmp, ctx->ac.i32, "");
const LLVMValueRef vertexptr = ngg_gs_vertex_ptr(ctx, tmp);
- if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
- outinfo->writes_pointsize = true;
- }
-
- if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
- outinfo->writes_layer = true;
- }
-
- if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
- outinfo->writes_viewport_index = true;
- }
-
unsigned out_idx = 0;
gep_idx[1] = ctx->ac.i32_0;
for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
+ unsigned output_usage_mask =
+ ctx->args->shader_info->gs.output_usage_mask[i];
+ int length = util_last_bit(output_usage_mask);
+
if (!(ctx->output_mask & (1ull << i)))
continue;
outputs[noutput].slot_name = i;
outputs[noutput].slot_index = i == VARYING_SLOT_CLIP_DIST1;
-
- outputs[noutput].usage_mask = ctx->shader_info->info.gs.output_usage_mask[i];
- int length = util_last_bit(outputs[noutput].usage_mask);
+ outputs[noutput].usage_mask = output_usage_mask;
for (unsigned j = 0; j < length; j++, out_idx++) {
+ if (!(output_usage_mask & (1 << j)))
+ continue;
+
gep_idx[2] = LLVMConstInt(ctx->ac.i32, out_idx, false);
tmp = LLVMBuildGEP(builder, vertexptr, gep_idx, 3, "");
tmp = LLVMBuildLoad(builder, tmp, "");
+
+ LLVMTypeRef type = LLVMGetAllocatedType(ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
+ if (ac_get_type_size(type) == 2) {
+ tmp = ac_to_integer(&ctx->ac, tmp);
+ tmp = LLVMBuildTrunc(ctx->ac.builder, tmp, ctx->ac.i16, "");
+ }
+
outputs[noutput].values[j] = ac_to_float(&ctx->ac, tmp);
}
/* Export ViewIndex. */
if (export_view_index) {
- outinfo->writes_layer = true;
-
outputs[noutput].slot_name = VARYING_SLOT_LAYER;
outputs[noutput].slot_index = 0;
outputs[noutput].usage_mask = 0x1;
- outputs[noutput].values[0] = ac_to_float(&ctx->ac, ctx->abi.view_index);
+ outputs[noutput].values[0] =
+ ac_to_float(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->ac.view_index));
for (unsigned j = 1; j < 4; j++)
outputs[noutput].values[j] = ctx->ac.f32_0;
noutput++;
}
radv_llvm_export_vs(ctx, outputs, noutput, outinfo,
- ctx->options->key.vs_common_out.export_clip_dists);
+ ctx->args->options->key.vs_common_out.export_clip_dists);
FREE(outputs);
}
ac_build_endif(&ctx->ac, 5145);
*/
const LLVMValueRef can_emit =
LLVMBuildICmp(builder, LLVMIntULT, vertexidx,
- LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
- ac_build_kill_if_false(&ctx->ac, can_emit);
+ LLVMConstInt(ctx->ac.i32, ctx->shader->info.gs.vertices_out, false), "");
+ ac_build_ifcc(&ctx->ac, can_emit, 9001);
tmp = LLVMBuildAdd(builder, vertexidx, ctx->ac.i32_1, "");
tmp = LLVMBuildSelect(builder, can_emit, tmp, vertexidx, "");
unsigned out_idx = 0;
for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
unsigned output_usage_mask =
- ctx->shader_info->info.gs.output_usage_mask[i];
+ ctx->args->shader_info->gs.output_usage_mask[i];
uint8_t output_stream =
- ctx->shader_info->info.gs.output_streams[i];
+ ctx->args->shader_info->gs.output_streams[i];
LLVMValueRef *out_ptr = &addrs[i * 4];
int length = util_last_bit(output_usage_mask);
LLVMValueRef ptr = LLVMBuildGEP(builder, vertexptr, gep_idx, 3, "");
out_val = ac_to_integer(&ctx->ac, out_val);
+ out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
+
LLVMBuildStore(builder, out_val, ptr);
}
}
- assert(out_idx * 4 <= ctx->gsvs_vertex_size);
+ assert(out_idx * 4 <= ctx->args->shader_info->gs.gsvs_vertex_size);
/* Determine and store whether this vertex completed a primitive. */
const LLVMValueRef curverts = LLVMBuildLoad(builder, ctx->gs_curprim_verts[stream], "");
- tmp = LLVMConstInt(ctx->ac.i32, si_conv_gl_prim_to_vertices(ctx->gs_output_prim) - 1, false);
+ tmp = LLVMConstInt(ctx->ac.i32, si_conv_gl_prim_to_vertices(ctx->shader->info.gs.output_primitive) - 1, false);
const LLVMValueRef iscompleteprim =
LLVMBuildICmp(builder, LLVMIntUGE, curverts, tmp, "");
tmp = LLVMBuildLoad(builder, ctx->gs_generated_prims[stream], "");
tmp = LLVMBuildAdd(builder, tmp, LLVMBuildZExt(builder, iscompleteprim, ctx->ac.i32, ""), "");
LLVMBuildStore(builder, tmp, ctx->gs_generated_prims[stream]);
+
+ ac_build_endif(&ctx->ac, 9001);
}
static void
write_tess_factors(struct radv_shader_context *ctx)
{
unsigned stride, outer_comps, inner_comps;
- struct ac_build_if_state if_ctx, inner_if_ctx;
- LLVMValueRef invocation_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
- LLVMValueRef rel_patch_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
+ LLVMValueRef tcs_rel_ids = ac_get_arg(&ctx->ac, ctx->args->ac.tcs_rel_ids);
+ LLVMValueRef invocation_id = ac_unpack_param(&ctx->ac, tcs_rel_ids, 8, 5);
+ LLVMValueRef rel_patch_id = ac_unpack_param(&ctx->ac, tcs_rel_ids, 0, 8);
unsigned tess_inner_index = 0, tess_outer_index;
LLVMValueRef lds_base, lds_inner = NULL, lds_outer, byteoffset, buffer;
LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
int i;
ac_emit_barrier(&ctx->ac, ctx->stage);
- switch (ctx->options->key.tcs.primitive_mode) {
+ switch (ctx->args->options->key.tcs.primitive_mode) {
case GL_ISOLINES:
stride = 2;
outer_comps = 2;
return;
}
- ac_nir_build_if(&if_ctx, ctx,
+ ac_build_ifcc(&ctx->ac,
LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
- invocation_id, ctx->ac.i32_0, ""));
+ invocation_id, ctx->ac.i32_0, ""), 6503);
lds_base = get_tcs_out_current_patch_data_offset(ctx);
}
// LINES reversal
- if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
+ if (ctx->args->options->key.tcs.primitive_mode == GL_ISOLINES) {
outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
ctx->ac.i32_1, "");
buffer = ctx->hs_ring_tess_factor;
- tf_base = ctx->tess_factor_offset;
+ tf_base = ac_get_arg(&ctx->ac, ctx->args->tess_factor_offset);
byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
unsigned tf_offset = 0;
- if (ctx->options->chip_class <= GFX8) {
- ac_nir_build_if(&inner_if_ctx, ctx,
+ if (ctx->ac.chip_class <= GFX8) {
+ ac_build_ifcc(&ctx->ac,
LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
- rel_patch_id, ctx->ac.i32_0, ""));
+ rel_patch_id, ctx->ac.i32_0, ""), 6504);
/* Store the dynamic HS control word. */
ac_build_buffer_store_dword(&ctx->ac, buffer,
0, ac_glc, false);
tf_offset += 4;
- ac_nir_build_endif(&inner_if_ctx);
+ ac_build_endif(&ctx->ac, 6504);
}
/* Store the tessellation factors. */
16 + tf_offset, ac_glc, false);
//store to offchip for TES to read - only if TES reads them
- if (ctx->options->key.tcs.tes_reads_tess_factors) {
+ if (ctx->args->options->key.tcs.tes_reads_tess_factors) {
LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
LLVMValueRef tf_inner_offset;
unsigned param_outer, param_inner;
ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
outer_comps, tf_outer_offset,
- ctx->oc_lds, 0, ac_glc, false);
+ ac_get_arg(&ctx->ac, ctx->args->oc_lds),
+ 0, ac_glc, false);
if (inner_comps) {
param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
ac_build_gather_values(&ctx->ac, inner, inner_comps);
ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
inner_comps, tf_inner_offset,
- ctx->oc_lds, 0, ac_glc, false);
+ ac_get_arg(&ctx->ac, ctx->args->oc_lds),
+ 0, ac_glc, false);
}
}
- ac_nir_build_endif(&if_ctx);
+
+ ac_build_endif(&ctx->ac, 6503);
}
static void
}
/* Process depth, stencil, samplemask. */
- if (ctx->shader_info->info.ps.writes_z) {
+ if (ctx->args->shader_info->ps.writes_z) {
depth = ac_to_float(&ctx->ac,
radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
}
- if (ctx->shader_info->info.ps.writes_stencil) {
+ if (ctx->args->shader_info->ps.writes_stencil) {
stencil = ac_to_float(&ctx->ac,
radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
}
- if (ctx->shader_info->info.ps.writes_sample_mask) {
+ if (ctx->args->shader_info->ps.writes_sample_mask) {
samplemask = ac_to_float(&ctx->ac,
radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
}
* exported.
*/
if (index > 0 &&
- !ctx->shader_info->info.ps.writes_z &&
- !ctx->shader_info->info.ps.writes_stencil &&
- !ctx->shader_info->info.ps.writes_sample_mask) {
+ !ctx->args->shader_info->ps.writes_z &&
+ !ctx->args->shader_info->ps.writes_stencil &&
+ !ctx->args->shader_info->ps.writes_sample_mask) {
unsigned last = index - 1;
color_args[last].valid_mask = 1; /* whether the EXEC mask is valid */
static void
emit_gs_epilogue(struct radv_shader_context *ctx)
{
- if (ctx->options->key.vs_common_out.as_ngg) {
+ if (ctx->args->options->key.vs_common_out.as_ngg) {
gfx10_ngg_gs_emit_epilogue_1(ctx);
return;
}
switch (ctx->stage) {
case MESA_SHADER_VERTEX:
- if (ctx->options->key.vs_common_out.as_ls)
+ if (ctx->args->options->key.vs_common_out.as_ls)
handle_ls_outputs_post(ctx);
- else if (ctx->options->key.vs_common_out.as_es)
- handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
- else if (ctx->options->key.vs_common_out.as_ngg)
- break; /* handled outside of the shader body */
+ else if (ctx->args->options->key.vs_common_out.as_es)
+ handle_es_outputs_post(ctx, &ctx->args->shader_info->vs.es_info);
+ else if (ctx->args->options->key.vs_common_out.as_ngg)
+ handle_ngg_outputs_post_1(ctx);
else
- handle_vs_outputs_post(ctx, ctx->options->key.vs_common_out.export_prim_id,
- ctx->options->key.vs_common_out.export_clip_dists,
- &ctx->shader_info->vs.outinfo);
+ handle_vs_outputs_post(ctx, ctx->args->options->key.vs_common_out.export_prim_id,
+ ctx->args->options->key.vs_common_out.export_clip_dists,
+ &ctx->args->shader_info->vs.outinfo);
break;
case MESA_SHADER_FRAGMENT:
handle_fs_outputs_post(ctx);
handle_tcs_outputs_post(ctx);
break;
case MESA_SHADER_TESS_EVAL:
- if (ctx->options->key.vs_common_out.as_ngg)
- break; /* handled outside of the shader body */
- else if (ctx->options->key.vs_common_out.as_es)
- handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
+ if (ctx->args->options->key.vs_common_out.as_es)
+ handle_es_outputs_post(ctx, &ctx->args->shader_info->tes.es_info);
+ else if (ctx->args->options->key.vs_common_out.as_ngg)
+ handle_ngg_outputs_post_1(ctx);
else
- handle_vs_outputs_post(ctx, ctx->options->key.vs_common_out.export_prim_id,
- ctx->options->key.vs_common_out.export_clip_dists,
- &ctx->shader_info->tes.outinfo);
+ handle_vs_outputs_post(ctx, ctx->args->options->key.vs_common_out.export_prim_id,
+ ctx->args->options->key.vs_common_out.export_clip_dists,
+ &ctx->args->shader_info->tes.outinfo);
break;
default:
break;
case MESA_SHADER_GEOMETRY:
return;
case MESA_SHADER_VERTEX:
- if (ctx->options->key.vs_common_out.as_ls ||
- ctx->options->key.vs_common_out.as_es)
+ if (ctx->args->options->key.vs_common_out.as_ls ||
+ ctx->args->options->key.vs_common_out.as_es)
return;
- outinfo = &ctx->shader_info->vs.outinfo;
+ outinfo = &ctx->args->shader_info->vs.outinfo;
break;
case MESA_SHADER_TESS_EVAL:
- if (ctx->options->key.vs_common_out.as_es)
+ if (ctx->args->options->key.vs_common_out.as_es)
return;
- outinfo = &ctx->shader_info->tes.outinfo;
+ outinfo = &ctx->args->shader_info->tes.outinfo;
break;
default:
unreachable("Unhandled shader type");
static void
ac_setup_rings(struct radv_shader_context *ctx)
{
- if (ctx->options->chip_class <= GFX8 &&
+ if (ctx->args->options->chip_class <= GFX8 &&
(ctx->stage == MESA_SHADER_GEOMETRY ||
- ctx->options->key.vs_common_out.as_es || ctx->options->key.vs_common_out.as_es)) {
+ ctx->args->options->key.vs_common_out.as_es || ctx->args->options->key.vs_common_out.as_es)) {
unsigned ring = ctx->stage == MESA_SHADER_GEOMETRY ? RING_ESGS_GS
: RING_ESGS_VS;
LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, ring, false);
offset);
}
- if (ctx->is_gs_copy_shader) {
+ if (ctx->args->is_gs_copy_shader) {
ctx->gsvs_ring[0] =
ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets,
LLVMConstInt(ctx->ac.i32,
*/
LLVMTypeRef v2i64 = LLVMVectorType(ctx->ac.i64, 2);
uint64_t stream_offset = 0;
- unsigned num_records = 64;
+ unsigned num_records = ctx->ac.wave_size;
LLVMValueRef base_ring;
base_ring =
LLVMValueRef ring, tmp;
num_components =
- ctx->shader_info->info.gs.num_stream_output_components[stream];
+ ctx->args->shader_info->gs.num_stream_output_components[stream];
if (!num_components)
continue;
- stride = 4 * num_components * ctx->gs_max_out_vertices;
+ stride = 4 * num_components * ctx->shader->info.gs.vertices_out;
/* Limit on the stride field for <= GFX7. */
assert(stride < (1 << 14));
ring = LLVMBuildInsertElement(ctx->ac.builder,
ring, tmp, ctx->ac.i32_0, "");
- stream_offset += stride * 64;
+ stream_offset += stride * ctx->ac.wave_size;
ring = LLVMBuildBitCast(ctx->ac.builder, ring,
ctx->ac.v4i32, "");
unsigned
radv_nir_get_max_workgroup_size(enum chip_class chip_class,
+ gl_shader_stage stage,
const struct nir_shader *nir)
{
- switch (nir->info.stage) {
- case MESA_SHADER_TESS_CTRL:
- return chip_class >= GFX7 ? 128 : 64;
- case MESA_SHADER_GEOMETRY:
- return chip_class >= GFX9 ? 128 : 64;
- case MESA_SHADER_COMPUTE:
- break;
- default:
- return 0;
- }
-
- unsigned max_workgroup_size = nir->info.cs.local_size[0] *
- nir->info.cs.local_size[1] *
- nir->info.cs.local_size[2];
- return max_workgroup_size;
+ const unsigned backup_sizes[] = {chip_class >= GFX9 ? 128 : 64, 1, 1};
+ unsigned sizes[3];
+ for (unsigned i = 0; i < 3; i++)
+ sizes[i] = nir ? nir->info.cs.local_size[i] : backup_sizes[i];
+ return radv_get_max_workgroup_size(chip_class, stage, sizes);
}
/* Fixup the HW not emitting the TCS regs if there are no HS threads. */
static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx)
{
- LLVMValueRef count = ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 8, 8);
+ LLVMValueRef count =
+ ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 8, 8);
LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
ctx->ac.i32_0, "");
- ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
- ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
- ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
+ ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty,
+ ac_get_arg(&ctx->ac, ctx->args->rel_auto_id),
+ ctx->abi.instance_id, "");
+ ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty,
+ ac_get_arg(&ctx->ac, ctx->args->ac.tcs_rel_ids),
+ ctx->rel_auto_id,
+ "");
+ ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty,
+ ac_get_arg(&ctx->ac, ctx->args->ac.tcs_patch_id),
+ ctx->abi.vertex_id, "");
}
-static void prepare_gs_input_vgprs(struct radv_shader_context *ctx)
+static void prepare_gs_input_vgprs(struct radv_shader_context *ctx, bool merged)
{
- for(int i = 5; i >= 0; --i) {
- ctx->gs_vtx_offset[i] = ac_unpack_param(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
- (i & 1) * 16, 16);
- }
+ if (merged) {
+ for(int i = 5; i >= 0; --i) {
+ ctx->gs_vtx_offset[i] =
+ ac_unpack_param(&ctx->ac,
+ ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[i & ~1]),
+ (i & 1) * 16, 16);
+ }
- ctx->gs_wave_id = ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 16, 8);
+ ctx->gs_wave_id = ac_unpack_param(&ctx->ac,
+ ac_get_arg(&ctx->ac, ctx->args->merged_wave_info),
+ 16, 8);
+ } else {
+ for (int i = 0; i < 6; i++)
+ ctx->gs_vtx_offset[i] = ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[i]);
+ ctx->gs_wave_id = ac_get_arg(&ctx->ac, ctx->args->gs_wave_id);
+ }
}
+/* Ensure that the esgs ring is declared.
+ *
+ * We declare it with 64KB alignment as a hint that the
+ * pointer value will always be 0.
+ */
+static void declare_esgs_ring(struct radv_shader_context *ctx)
+{
+ if (ctx->esgs_ring)
+ return;
+
+ assert(!LLVMGetNamedGlobal(ctx->ac.module, "esgs_ring"));
+
+ ctx->esgs_ring = LLVMAddGlobalInAddressSpace(
+ ctx->ac.module, LLVMArrayType(ctx->ac.i32, 0),
+ "esgs_ring",
+ AC_ADDR_SPACE_LDS);
+ LLVMSetLinkage(ctx->esgs_ring, LLVMExternalLinkage);
+ LLVMSetAlignment(ctx->esgs_ring, 64 * 1024);
+}
static
LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm,
struct nir_shader *const *shaders,
int shader_count,
- struct radv_shader_variant_info *shader_info,
+ struct radv_shader_info *shader_info,
const struct radv_nir_compiler_options *options)
{
struct radv_shader_context ctx = {0};
- unsigned i;
- ctx.options = options;
- ctx.shader_info = shader_info;
-
- ac_llvm_context_init(&ctx.ac, options->chip_class, options->family);
- ctx.context = ctx.ac.context;
- ctx.ac.module = ac_create_module(ac_llvm->tm, ctx.context);
-
- enum ac_float_mode float_mode =
- options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
- AC_FLOAT_MODE_DEFAULT;
+ struct radv_shader_args args = {0};
+ args.options = options;
+ args.shader_info = shader_info;
+ ctx.args = &args;
- ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
+ declare_inputs(&args, shaders[shader_count - 1]->info.stage, shader_count >= 2,
+ shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
- radv_nir_shader_info_init(&shader_info->info);
+ enum ac_float_mode float_mode = AC_FLOAT_MODE_DEFAULT;
- for(int i = 0; i < shader_count; ++i)
- radv_nir_shader_info_pass(shaders[i], options, &shader_info->info);
+ if (shader_info->float_controls_mode & FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32) {
+ float_mode = AC_FLOAT_MODE_DENORM_FLUSH_TO_ZERO;
+ }
- for (i = 0; i < RADV_UD_MAX_SETS; i++)
- shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
- for (i = 0; i < AC_UD_MAX_UD; i++)
- shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
+ ac_llvm_context_init(&ctx.ac, ac_llvm, options->chip_class,
+ options->family, float_mode, shader_info->wave_size, 64);
+ ctx.context = ctx.ac.context;
ctx.max_workgroup_size = 0;
for (int i = 0; i < shader_count; ++i) {
ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
- radv_nir_get_max_workgroup_size(ctx.options->chip_class,
- shaders[i]));
+ radv_nir_get_max_workgroup_size(args.options->chip_class,
+ shaders[i]->info.stage,
+ shaders[i]));
}
if (ctx.ac.chip_class >= GFX10) {
}
}
- create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
- shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
+ create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2);
ctx.abi.inputs = &ctx.inputs[0];
ctx.abi.emit_outputs = handle_shader_outputs_post;
ctx.abi.load_sampler_desc = radv_get_sampler_desc;
ctx.abi.load_resource = radv_load_resource;
ctx.abi.clamp_shadow_reference = false;
- ctx.abi.gfx9_stride_size_workaround = ctx.ac.chip_class == GFX9 && HAVE_LLVM < 0x800;
+ ctx.abi.robust_buffer_access = options->robust_buffer_access;
- /* Because the new raw/struct atomic intrinsics are buggy with LLVM 8,
- * we fallback to the old intrinsics for atomic buffer image operations
- * and thus we need to apply the indexing workaround...
- */
- ctx.abi.gfx9_stride_size_workaround_for_atomic = ctx.ac.chip_class == GFX9 && HAVE_LLVM < 0x900;
-
- bool is_ngg = is_pre_gs_stage(shaders[0]->info.stage) && ctx.options->key.vs_common_out.as_ngg;
+ bool is_ngg = is_pre_gs_stage(shaders[0]->info.stage) && args.options->key.vs_common_out.as_ngg;
if (shader_count >= 2 || is_ngg)
ac_init_exec_full_mask(&ctx.ac);
- if ((ctx.ac.family == CHIP_VEGA10 ||
- ctx.ac.family == CHIP_RAVEN) &&
+ if (args.ac.vertex_id.used)
+ ctx.abi.vertex_id = ac_get_arg(&ctx.ac, args.ac.vertex_id);
+ if (args.rel_auto_id.used)
+ ctx.rel_auto_id = ac_get_arg(&ctx.ac, args.rel_auto_id);
+ if (args.ac.instance_id.used)
+ ctx.abi.instance_id = ac_get_arg(&ctx.ac, args.ac.instance_id);
+
+ if (options->has_ls_vgpr_init_bug &&
shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
ac_nir_fixup_ls_hs_input_vgprs(&ctx);
+ if (is_ngg) {
+ /* Declare scratch space base for streamout and vertex
+ * compaction. Whether space is actually allocated is
+ * determined during linking / PM4 creation.
+ *
+ * Add an extra dword per vertex to ensure an odd stride, which
+ * avoids bank conflicts for SoA accesses.
+ */
+ declare_esgs_ring(&ctx);
+
+ /* This is really only needed when streamout and / or vertex
+ * compaction is enabled.
+ */
+ LLVMTypeRef asi32 = LLVMArrayType(ctx.ac.i32, 8);
+ ctx.gs_ngg_scratch = LLVMAddGlobalInAddressSpace(ctx.ac.module,
+ asi32, "ngg_scratch", AC_ADDR_SPACE_LDS);
+ LLVMSetInitializer(ctx.gs_ngg_scratch, LLVMGetUndef(asi32));
+ LLVMSetAlignment(ctx.gs_ngg_scratch, 4);
+ }
+
for(int i = 0; i < shader_count; ++i) {
ctx.stage = shaders[i]->info.stage;
+ ctx.shader = shaders[i];
ctx.output_mask = 0;
if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
ctx.gs_next_vertex[i] =
ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
}
- if (ctx.options->key.vs_common_out.as_ngg) {
+ if (args.options->key.vs_common_out.as_ngg) {
for (unsigned i = 0; i < 4; ++i) {
ctx.gs_curprim_verts[i] =
ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
}
- /* TODO: streamout */
+ unsigned scratch_size = 8;
+ if (args.shader_info->so.num_outputs)
+ scratch_size = 44;
- LLVMTypeRef ai32 = LLVMArrayType(ctx.ac.i32, 8);
+ LLVMTypeRef ai32 = LLVMArrayType(ctx.ac.i32, scratch_size);
ctx.gs_ngg_scratch =
LLVMAddGlobalInAddressSpace(ctx.ac.module,
ai32, "ngg_scratch", AC_ADDR_SPACE_LDS);
LLVMSetInitializer(ctx.gs_ngg_scratch, LLVMGetUndef(ai32));
LLVMSetAlignment(ctx.gs_ngg_scratch, 4);
- ctx.gs_ngg_emit = LLVMBuildIntToPtr(ctx.ac.builder, ctx.ac.i32_0,
- LLVMPointerType(LLVMArrayType(ctx.ac.i32, 0), AC_ADDR_SPACE_LDS),
- "ngg_emit");
+ ctx.gs_ngg_emit = LLVMAddGlobalInAddressSpace(ctx.ac.module,
+ LLVMArrayType(ctx.ac.i32, 0), "ngg_emit", AC_ADDR_SPACE_LDS);
+ LLVMSetLinkage(ctx.gs_ngg_emit, LLVMExternalLinkage);
LLVMSetAlignment(ctx.gs_ngg_emit, 4);
}
- ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
- ctx.gs_output_prim = shaders[i]->info.gs.output_primitive;
ctx.abi.load_inputs = load_gs_input;
ctx.abi.emit_primitive = visit_end_primitive;
} else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
- ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
- ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
ctx.abi.load_tess_varyings = load_tcs_varyings;
ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
ctx.abi.store_tcs_outputs = store_tcs_output;
- ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
if (shader_count == 1)
- ctx.tcs_num_inputs = ctx.options->key.tcs.num_inputs;
+ ctx.tcs_num_inputs = args.options->key.tcs.num_inputs;
else
- ctx.tcs_num_inputs = util_last_bit64(shader_info->info.vs.ls_outputs_written);
+ ctx.tcs_num_inputs = util_last_bit64(shader_info->vs.ls_outputs_written);
ctx.tcs_num_patches = get_tcs_num_patches(&ctx);
} else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
- ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
ctx.abi.load_tess_varyings = load_tes_input;
ctx.abi.load_tess_coord = load_tess_coord;
ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
- ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
- ctx.tcs_num_patches = ctx.options->key.tes.num_patches;
+ ctx.tcs_num_patches = args.options->key.tes.num_patches;
} else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
ctx.abi.load_base_vertex = radv_load_base_vertex;
} else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
- shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
- ctx.abi.lookup_interp_param = lookup_interp_param;
ctx.abi.load_sample_position = load_sample_position;
ctx.abi.load_sample_mask_in = load_sample_mask_in;
ctx.abi.emit_kill = radv_emit_kill;
}
- if (i)
+ if (shaders[i]->info.stage == MESA_SHADER_VERTEX &&
+ args.options->key.vs_common_out.as_ngg &&
+ args.options->key.vs_common_out.export_prim_id) {
+ declare_esgs_ring(&ctx);
+ }
+
+ bool nested_barrier = false;
+
+ if (i) {
+ if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY &&
+ args.options->key.vs_common_out.as_ngg) {
+ gfx10_ngg_gs_emit_prologue(&ctx);
+ nested_barrier = false;
+ } else {
+ nested_barrier = true;
+ }
+ }
+
+ if (nested_barrier) {
+ /* Execute a barrier before the second shader in
+ * a merged shader.
+ *
+ * Execute the barrier inside the conditional block,
+ * so that empty waves can jump directly to s_endpgm,
+ * which will also signal the barrier.
+ *
+ * This is possible in gfx9, because an empty wave
+ * for the second shader does not participate in
+ * the epilogue. With NGG, empty waves may still
+ * be required to export data (e.g. GS output vertices),
+ * so we cannot let them exit early.
+ *
+ * If the shader is TCS and the TCS epilog is present
+ * and contains a barrier, it will wait there and then
+ * reach s_endpgm.
+ */
ac_emit_barrier(&ctx.ac, ctx.stage);
+ }
nir_foreach_variable(variable, &shaders[i]->outputs)
scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
- if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
- unsigned addclip = shaders[i]->info.clip_distance_array_size +
- shaders[i]->info.cull_distance_array_size > 4;
- ctx.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
- ctx.max_gsvs_emit_size = ctx.gsvs_vertex_size *
- shaders[i]->info.gs.vertices_out;
- }
-
ac_setup_rings(&ctx);
LLVMBasicBlockRef merge_block;
if (shader_count >= 2 || is_ngg) {
-
- if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY &&
- ctx.options->key.vs_common_out.as_ngg) {
- gfx10_ngg_gs_emit_prologue(&ctx);
- }
-
LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
- LLVMValueRef count = ac_unpack_param(&ctx.ac, ctx.merged_wave_info, 8 * i, 8);
+ LLVMValueRef count =
+ ac_unpack_param(&ctx.ac,
+ ac_get_arg(&ctx.ac, args.merged_wave_info),
+ 8 * i, 8);
LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
thread_id, count, "");
prepare_interp_optimize(&ctx, shaders[i]);
else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
handle_vs_inputs(&ctx, shaders[i]);
- else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
- prepare_gs_input_vgprs(&ctx);
+ else if(shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
+ prepare_gs_input_vgprs(&ctx, shader_count >= 2);
- ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i]);
+ ac_nir_translate(&ctx.ac, &ctx.abi, &args.ac, shaders[i]);
if (shader_count >= 2 || is_ngg) {
LLVMBuildBr(ctx.ac.builder, merge_block);
/* This needs to be outside the if wrapping the shader body, as sometimes
* the HW generates waves with 0 es/vs threads. */
if (is_pre_gs_stage(shaders[i]->info.stage) &&
- ctx.options->key.vs_common_out.as_ngg &&
+ args.options->key.vs_common_out.as_ngg &&
i == shader_count - 1) {
- handle_ngg_outputs_post(&ctx);
+ handle_ngg_outputs_post_2(&ctx);
} else if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY &&
- ctx.options->key.vs_common_out.as_ngg) {
+ args.options->key.vs_common_out.as_ngg) {
gfx10_ngg_gs_emit_epilogue_2(&ctx);
}
- if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
- shader_info->gs.gsvs_vertex_size = ctx.gsvs_vertex_size;
- shader_info->gs.max_gsvs_emit_size = ctx.max_gsvs_emit_size;
- } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
+ if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
shader_info->tcs.num_patches = ctx.tcs_num_patches;
shader_info->tcs.lds_size = calculate_tess_lds_size(&ctx);
}
LLVMBuildRetVoid(ctx.ac.builder);
- if (options->dump_preoptir)
+ if (options->dump_preoptir) {
+ fprintf(stderr, "%s LLVM IR:\n\n",
+ radv_get_shader_name(shader_info,
+ shaders[shader_count - 1]->info.stage));
ac_dump_module(ctx.ac.module);
+ fprintf(stderr, "\n");
+ }
ac_llvm_finalize_module(&ctx, ac_llvm->passmgr, options);
ac_nir_eliminate_const_vs_outputs(&ctx);
if (options->dump_shader) {
- ctx.shader_info->private_mem_vgprs =
+ args.shader_info->private_mem_vgprs =
ac_count_scratch_private_memory(ctx.main_function);
}
static void ac_compile_llvm_module(struct ac_llvm_compiler *ac_llvm,
LLVMModuleRef llvm_module,
struct radv_shader_binary **rbinary,
- struct radv_shader_variant_info *shader_info,
gl_shader_stage stage,
+ const char *name,
const struct radv_nir_compiler_options *options)
{
char *elf_buffer = NULL;
size_t elf_size = 0;
char *llvm_ir_string = NULL;
- if (options->dump_shader)
+
+ if (options->dump_shader) {
+ fprintf(stderr, "%s LLVM IR:\n\n", name);
ac_dump_module(llvm_module);
+ fprintf(stderr, "\n");
+ }
- if (options->record_llvm_ir) {
+ if (options->record_ir) {
char *llvm_ir = LLVMPrintModuleToString(llvm_module);
llvm_ir_string = strdup(llvm_ir);
LLVMDisposeMessage(llvm_ir);
free(elf_buffer);
}
-static void
-ac_fill_shader_info(struct radv_shader_variant_info *shader_info, struct nir_shader *nir, const struct radv_nir_compiler_options *options)
-{
- switch (nir->info.stage) {
- case MESA_SHADER_COMPUTE:
- for (int i = 0; i < 3; ++i)
- shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
- break;
- case MESA_SHADER_FRAGMENT:
- shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
- break;
- case MESA_SHADER_GEOMETRY:
- shader_info->gs.vertices_in = nir->info.gs.vertices_in;
- shader_info->gs.vertices_out = nir->info.gs.vertices_out;
- shader_info->gs.output_prim = nir->info.gs.output_primitive;
- shader_info->gs.invocations = nir->info.gs.invocations;
- break;
- case MESA_SHADER_TESS_EVAL:
- shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
- shader_info->tes.spacing = nir->info.tess.spacing;
- shader_info->tes.ccw = nir->info.tess.ccw;
- shader_info->tes.point_mode = nir->info.tess.point_mode;
- shader_info->tes.as_es = options->key.vs_common_out.as_es;
- shader_info->tes.export_prim_id = options->key.vs_common_out.export_prim_id;
- shader_info->is_ngg = options->key.vs_common_out.as_ngg;
- break;
- case MESA_SHADER_TESS_CTRL:
- shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
- break;
- case MESA_SHADER_VERTEX:
- shader_info->vs.as_es = options->key.vs_common_out.as_es;
- shader_info->vs.as_ls = options->key.vs_common_out.as_ls;
- shader_info->vs.export_prim_id = options->key.vs_common_out.export_prim_id;
- shader_info->is_ngg = options->key.vs_common_out.as_ngg;
- break;
- default:
- break;
- }
-}
-
void
radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
struct radv_shader_binary **rbinary,
- struct radv_shader_variant_info *shader_info,
+ struct radv_shader_info *shader_info,
struct nir_shader *const *nir,
int nir_count,
const struct radv_nir_compiler_options *options)
llvm_module = ac_translate_nir_to_llvm(ac_llvm, nir, nir_count, shader_info,
options);
- ac_compile_llvm_module(ac_llvm, llvm_module, rbinary, shader_info,
- nir[nir_count - 1]->info.stage, options);
-
- for (int i = 0; i < nir_count; ++i)
- ac_fill_shader_info(shader_info, nir[i], options);
+ ac_compile_llvm_module(ac_llvm, llvm_module, rbinary,
+ nir[nir_count - 1]->info.stage,
+ radv_get_shader_name(shader_info,
+ nir[nir_count - 1]->info.stage),
+ options);
/* Determine the ES type (VS or TES) for the GS on GFX9. */
if (options->chip_class >= GFX9) {
ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
{
LLVMValueRef vtx_offset =
- LLVMBuildMul(ctx->ac.builder, ctx->abi.vertex_id,
+ LLVMBuildMul(ctx->ac.builder, ac_get_arg(&ctx->ac, ctx->args->ac.vertex_id),
LLVMConstInt(ctx->ac.i32, 4, false), "");
LLVMValueRef stream_id;
/* Fetch the vertex stream ID. */
- if (ctx->shader_info->info.so.num_outputs) {
+ if (!ctx->args->options->use_ngg_streamout &&
+ ctx->args->shader_info->so.num_outputs) {
stream_id =
- ac_unpack_param(&ctx->ac, ctx->streamout_config, 24, 2);
+ ac_unpack_param(&ctx->ac,
+ ac_get_arg(&ctx->ac,
+ ctx->args->streamout_config),
+ 24, 2);
} else {
stream_id = ctx->ac.i32_0;
}
for (unsigned stream = 0; stream < 4; stream++) {
unsigned num_components =
- ctx->shader_info->info.gs.num_stream_output_components[stream];
+ ctx->args->shader_info->gs.num_stream_output_components[stream];
LLVMBasicBlockRef bb;
unsigned offset;
- if (!num_components)
+ if (stream > 0 && !num_components)
continue;
- if (stream > 0 && !ctx->shader_info->info.so.num_outputs)
+ if (stream > 0 && !ctx->args->shader_info->so.num_outputs)
continue;
bb = LLVMInsertBasicBlockInContext(ctx->ac.context, end_bb, "out");
offset = 0;
for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
unsigned output_usage_mask =
- ctx->shader_info->info.gs.output_usage_mask[i];
+ ctx->args->shader_info->gs.output_usage_mask[i];
unsigned output_stream =
- ctx->shader_info->info.gs.output_streams[i];
+ ctx->args->shader_info->gs.output_streams[i];
int length = util_last_bit(output_usage_mask);
if (!(ctx->output_mask & (1ull << i)) ||
soffset = LLVMConstInt(ctx->ac.i32,
offset *
- ctx->gs_max_out_vertices * 16 * 4, false);
+ ctx->shader->info.gs.vertices_out * 16 * 4, false);
offset++;
}
}
- if (ctx->shader_info->info.so.num_outputs)
+ if (!ctx->args->options->use_ngg_streamout &&
+ ctx->args->shader_info->so.num_outputs)
radv_emit_streamout(ctx, stream);
if (stream == 0) {
handle_vs_outputs_post(ctx, false, true,
- &ctx->shader_info->vs.outinfo);
+ &ctx->args->shader_info->vs.outinfo);
}
LLVMBuildBr(ctx->ac.builder, end_bb);
radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
struct nir_shader *geom_shader,
struct radv_shader_binary **rbinary,
- struct radv_shader_variant_info *shader_info,
+ struct radv_shader_info *shader_info,
const struct radv_nir_compiler_options *options)
{
struct radv_shader_context ctx = {0};
- ctx.options = options;
- ctx.shader_info = shader_info;
-
- ac_llvm_context_init(&ctx.ac, options->chip_class, options->family);
- ctx.context = ctx.ac.context;
- ctx.ac.module = ac_create_module(ac_llvm->tm, ctx.context);
+ struct radv_shader_args args = {0};
+ args.options = options;
+ args.shader_info = shader_info;
+ ctx.args = &args;
- ctx.is_gs_copy_shader = true;
+ args.is_gs_copy_shader = true;
+ declare_inputs(&args, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
- enum ac_float_mode float_mode =
- options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
- AC_FLOAT_MODE_DEFAULT;
+ ac_llvm_context_init(&ctx.ac, ac_llvm, options->chip_class,
+ options->family, AC_FLOAT_MODE_DEFAULT, 64, 64);
+ ctx.context = ctx.ac.context;
- ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
ctx.stage = MESA_SHADER_VERTEX;
+ ctx.shader = geom_shader;
- radv_nir_shader_info_pass(geom_shader, options, &shader_info->info);
-
- create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
+ create_function(&ctx, MESA_SHADER_VERTEX, false);
- ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
ac_setup_rings(&ctx);
nir_foreach_variable(variable, &geom_shader->outputs) {
ac_llvm_finalize_module(&ctx, ac_llvm->passmgr, options);
- ac_compile_llvm_module(ac_llvm, ctx.ac.module, rbinary, shader_info,
- MESA_SHADER_VERTEX, options);
+ ac_compile_llvm_module(ac_llvm, ctx.ac.module, rbinary,
+ MESA_SHADER_VERTEX, "GS Copy Shader", options);
(*rbinary)->is_gs_copy_shader = true;
}
projects / mesa.git / blobdiff