bool is_gs_copy_shader;
LLVMValueRef gs_next_vertex[4];
+ LLVMValueRef gs_curprim_verts[4];
+ LLVMValueRef gs_generated_prims[4];
+ LLVMValueRef gs_ngg_emit;
+ LLVMValueRef gs_ngg_scratch;
unsigned gs_max_out_vertices;
+ unsigned gs_output_prim;
unsigned tes_primitive_mode;
uint32_t tcs_num_patches;
uint32_t max_gsvs_emit_size;
uint32_t gsvs_vertex_size;
+
+ LLVMValueRef vertexptr; /* GFX10 only */
};
enum radeon_llvm_calling_convention {
}
+static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context *ctx,
+ unsigned stream,
+ LLVMValueRef *addrs);
+
static void
visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
{
unsigned offset = 0;
struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
+ if (ctx->options->key.vs_common_out.as_ngg) {
+ gfx10_ngg_gs_emit_vertex(ctx, stream, addrs);
+ return;
+ }
+
/* Write vertex attribute values to GSVS ring */
gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
ctx->gs_next_vertex[stream],
visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
{
struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
+
+ if (ctx->options->key.vs_common_out.as_ngg) {
+ LLVMBuildStore(ctx->ac.builder, ctx->ac.i32_0, ctx->gs_curprim_verts[stream]);
+ return;
+ }
+
ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
}
static LLVMValueRef
radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
{
- LLVMValueRef output =
- ctx->abi.outputs[ac_llvm_reg_index_soa(index, chan)];
-
+ LLVMValueRef output = ctx->abi.outputs[ac_llvm_reg_index_soa(index, chan)];
return LLVMBuildLoad(ctx->ac.builder, output, "");
}
ac_nir_build_endif(&if_ctx);
}
+struct radv_shader_output_values {
+ LLVMValueRef values[4];
+ unsigned slot_name;
+ unsigned slot_index;
+ unsigned usage_mask;
+};
+
static void
-handle_vs_outputs_post(struct radv_shader_context *ctx,
- bool export_prim_id,
- bool export_clip_dists,
- struct radv_vs_output_info *outinfo)
+radv_build_param_exports(struct radv_shader_context *ctx,
+ struct radv_shader_output_values *outputs,
+ unsigned noutput,
+ struct radv_vs_output_info *outinfo,
+ bool export_clip_dists)
{
- uint32_t param_count = 0;
- unsigned pos_idx, num_pos_exports = 0;
- struct ac_export_args pos_args[4] = {};
- LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
- int i;
-
- if (ctx->options->key.has_multiview_view_index) {
- LLVMValueRef* tmp_out = &ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
- if(!*tmp_out) {
- for(unsigned i = 0; i < 4; ++i)
- ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
- ac_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
- }
+ unsigned param_count = 0;
- LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, ctx->abi.view_index), *tmp_out);
- ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
- }
+ for (unsigned i = 0; i < noutput; i++) {
+ unsigned slot_name = outputs[i].slot_name;
+ unsigned usage_mask = outputs[i].usage_mask;
- memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
- sizeof(outinfo->vs_output_param_offset));
+ if (slot_name != VARYING_SLOT_LAYER &&
+ slot_name != VARYING_SLOT_PRIMITIVE_ID &&
+ slot_name != VARYING_SLOT_CLIP_DIST0 &&
+ slot_name != VARYING_SLOT_CLIP_DIST1 &&
+ slot_name < VARYING_SLOT_VAR0)
+ continue;
- for(unsigned location = VARYING_SLOT_CLIP_DIST0; location <= VARYING_SLOT_CLIP_DIST1; ++location) {
- if (ctx->output_mask & (1ull << location)) {
- unsigned output_usage_mask, length;
- LLVMValueRef slots[4];
- unsigned j;
-
- if (ctx->stage == MESA_SHADER_VERTEX &&
- !ctx->is_gs_copy_shader) {
- output_usage_mask =
- ctx->shader_info->info.vs.output_usage_mask[location];
- } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
- output_usage_mask =
- ctx->shader_info->info.tes.output_usage_mask[location];
- } else {
- assert(ctx->is_gs_copy_shader);
- output_usage_mask =
- ctx->shader_info->info.gs.output_usage_mask[location];
- }
+ if ((slot_name == VARYING_SLOT_CLIP_DIST0 ||
+ slot_name == VARYING_SLOT_CLIP_DIST1) && !export_clip_dists)
+ continue;
- length = util_last_bit(output_usage_mask);
+ radv_export_param(ctx, param_count, outputs[i].values, usage_mask);
- for (j = 0; j < length; j++)
- slots[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, location, j));
+ assert(i < ARRAY_SIZE(outinfo->vs_output_param_offset));
+ outinfo->vs_output_param_offset[slot_name] = param_count++;
+ }
- for (i = length; i < 4; i++)
- slots[i] = LLVMGetUndef(ctx->ac.f32);
+ outinfo->param_exports = param_count;
+}
- unsigned index = 2 + (location - VARYING_SLOT_CLIP_DIST0);
- si_llvm_init_export_args(ctx, &slots[0], 0xf,
- V_008DFC_SQ_EXP_POS + index,
- &pos_args[index]);
+/* Generate export instructions for hardware VS shader stage or NGG GS stage
+ * (position and parameter data only).
+ */
+static void
+radv_llvm_export_vs(struct radv_shader_context *ctx,
+ struct radv_shader_output_values *outputs,
+ unsigned noutput,
+ struct radv_vs_output_info *outinfo,
+ bool export_clip_dists)
+{
+ LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_value = NULL;
+ struct ac_export_args pos_args[4] = {};
+ unsigned pos_idx, index;
+ int i;
- if (export_clip_dists) {
- /* Export the clip/cull distances values to the next stage. */
- radv_export_param(ctx, param_count, &slots[0], 0xf);
- outinfo->vs_output_param_offset[location] = param_count++;
- }
+ /* Build position exports */
+ for (i = 0; i < noutput; i++) {
+ switch (outputs[i].slot_name) {
+ case VARYING_SLOT_POS:
+ si_llvm_init_export_args(ctx, outputs[i].values, 0xf,
+ V_008DFC_SQ_EXP_POS, &pos_args[0]);
+ break;
+ case VARYING_SLOT_PSIZ:
+ psize_value = outputs[i].values[0];
+ break;
+ case VARYING_SLOT_LAYER:
+ layer_value = outputs[i].values[0];
+ break;
+ case VARYING_SLOT_VIEWPORT:
+ viewport_value = outputs[i].values[0];
+ break;
+ case VARYING_SLOT_CLIP_DIST0:
+ case VARYING_SLOT_CLIP_DIST1:
+ index = 2 + outputs[i].slot_index;
+ si_llvm_init_export_args(ctx, outputs[i].values, 0xf,
+ V_008DFC_SQ_EXP_POS + index,
+ &pos_args[index]);
+ break;
+ default:
+ break;
}
}
- LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
- if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
- for (unsigned j = 0; j < 4; j++)
- pos_values[j] = radv_load_output(ctx, VARYING_SLOT_POS, j);
- }
- si_llvm_init_export_args(ctx, pos_values, 0xf, V_008DFC_SQ_EXP_POS, &pos_args[0]);
-
- if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
- outinfo->writes_pointsize = true;
- psize_value = radv_load_output(ctx, VARYING_SLOT_PSIZ, 0);
- }
-
- if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
- outinfo->writes_layer = true;
- layer_value = radv_load_output(ctx, VARYING_SLOT_LAYER, 0);
- }
-
- if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
- outinfo->writes_viewport_index = true;
- viewport_index_value = radv_load_output(ctx, VARYING_SLOT_VIEWPORT, 0);
- }
-
- if (ctx->shader_info->info.so.num_outputs &&
- !ctx->is_gs_copy_shader) {
- /* The GS copy shader emission already emits streamout. */
- radv_emit_streamout(ctx, 0);
+ /* We need to add the position output manually if it's missing. */
+ if (!pos_args[0].out[0]) {
+ pos_args[0].enabled_channels = 0xf; /* writemask */
+ pos_args[0].valid_mask = 0; /* EXEC mask */
+ pos_args[0].done = 0; /* last export? */
+ pos_args[0].target = V_008DFC_SQ_EXP_POS;
+ pos_args[0].compr = 0; /* COMPR flag */
+ pos_args[0].out[0] = ctx->ac.f32_0; /* X */
+ pos_args[0].out[1] = ctx->ac.f32_0; /* Y */
+ pos_args[0].out[2] = ctx->ac.f32_0; /* Z */
+ pos_args[0].out[3] = ctx->ac.f32_1; /* W */
}
if (outinfo->writes_pointsize ||
/* GFX9 has the layer in out.z[10:0] and the viewport
* index in out.z[19:16].
*/
- LLVMValueRef v = viewport_index_value;
+ LLVMValueRef v = viewport_value;
v = ac_to_integer(&ctx->ac, v);
v = LLVMBuildShl(ctx->ac.builder, v,
LLVMConstInt(ctx->ac.i32, 16, false),
pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
pos_args[1].enabled_channels |= 1 << 2;
} else {
- pos_args[1].out[3] = viewport_index_value;
+ pos_args[1].out[3] = viewport_value;
pos_args[1].enabled_channels |= 1 << 3;
}
}
}
+
for (i = 0; i < 4; i++) {
if (pos_args[i].out[0])
- num_pos_exports++;
+ outinfo->pos_exports++;
}
/* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
/* Specify the target we are exporting */
pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
- if (pos_idx == num_pos_exports)
+
+ if (pos_idx == outinfo->pos_exports)
+ /* Specify that this is the last export */
pos_args[i].done = 1;
+
ac_build_export(&ctx->ac, &pos_args[i]);
}
+ /* Build parameter exports */
+ radv_build_param_exports(ctx, outputs, noutput, outinfo, export_clip_dists);
+}
+
+static void
+handle_vs_outputs_post(struct radv_shader_context *ctx,
+ bool export_prim_id,
+ bool export_clip_dists,
+ struct radv_vs_output_info *outinfo)
+{
+ struct radv_shader_output_values *outputs;
+ unsigned noutput = 0;
+
+ if (ctx->options->key.has_multiview_view_index) {
+ LLVMValueRef* tmp_out = &ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
+ if(!*tmp_out) {
+ for(unsigned i = 0; i < 4; ++i)
+ ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
+ ac_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
+ }
+
+ LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, ctx->abi.view_index), *tmp_out);
+ ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
+ }
+
+ memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
+ sizeof(outinfo->vs_output_param_offset));
+ outinfo->pos_exports = 0;
+
+ if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
+ outinfo->writes_pointsize = true;
+ }
+
+ if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
+ outinfo->writes_layer = true;
+ }
+
+ if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
+ outinfo->writes_viewport_index = true;
+ }
+
+ if (ctx->shader_info->info.so.num_outputs &&
+ !ctx->is_gs_copy_shader) {
+ /* The GS copy shader emission already emits streamout. */
+ radv_emit_streamout(ctx, 0);
+ }
+
+ /* Allocate a temporary array for the output values. */
+ unsigned num_outputs = util_bitcount64(ctx->output_mask) + export_prim_id;
+ outputs = malloc(num_outputs * sizeof(outputs[0]));
+
for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
- LLVMValueRef values[4];
if (!(ctx->output_mask & (1ull << i)))
continue;
- if (i != VARYING_SLOT_LAYER &&
- i != VARYING_SLOT_PRIMITIVE_ID &&
- i < VARYING_SLOT_VAR0)
- continue;
-
- for (unsigned j = 0; j < 4; j++)
- values[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
-
- unsigned output_usage_mask;
+ outputs[noutput].slot_name = i;
+ outputs[noutput].slot_index = i == VARYING_SLOT_CLIP_DIST1;
if (ctx->stage == MESA_SHADER_VERTEX &&
!ctx->is_gs_copy_shader) {
- output_usage_mask =
+ outputs[noutput].usage_mask =
ctx->shader_info->info.vs.output_usage_mask[i];
} else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
- output_usage_mask =
+ outputs[noutput].usage_mask =
ctx->shader_info->info.tes.output_usage_mask[i];
} else {
- assert(ctx->is_gs_copy_shader);
- output_usage_mask =
+ assert(ctx->is_gs_copy_shader || ctx->options->key.vs_common_out.as_ngg);
+ outputs[noutput].usage_mask =
ctx->shader_info->info.gs.output_usage_mask[i];
}
- radv_export_param(ctx, param_count, values, output_usage_mask);
+ for (unsigned j = 0; j < 4; j++) {
+ outputs[noutput].values[j] =
+ ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
+ }
- outinfo->vs_output_param_offset[i] = param_count++;
+ noutput++;
}
+ /* Export PrimitiveID. */
if (export_prim_id) {
- LLVMValueRef values[4];
+ outinfo->export_prim_id = true;
- values[0] = ctx->vs_prim_id;
+ outputs[noutput].slot_name = VARYING_SLOT_PRIMITIVE_ID;
+ outputs[noutput].slot_index = 0;
+ outputs[noutput].usage_mask = 0x1;
+ outputs[noutput].values[0] = ctx->vs_prim_id;
for (unsigned j = 1; j < 4; j++)
- values[j] = ctx->ac.f32_0;
-
- radv_export_param(ctx, param_count, values, 0x1);
-
- outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
- outinfo->export_prim_id = true;
+ outputs[noutput].values[j] = ctx->ac.f32_0;
+ noutput++;
}
- outinfo->pos_exports = num_pos_exports;
- outinfo->param_exports = param_count;
+ radv_llvm_export_vs(ctx, outputs, noutput, outinfo, export_clip_dists);
+
+ free(outputs);
}
static void
return ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 24, 4);
}
+static LLVMValueRef get_tgsize(struct radv_shader_context *ctx)
+{
+ return ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 28, 4);
+}
+
+static LLVMValueRef get_thread_id_in_tg(struct radv_shader_context *ctx)
+{
+ LLVMBuilderRef builder = ctx->ac.builder;
+ LLVMValueRef tmp;
+ tmp = LLVMBuildMul(builder, get_wave_id_in_tg(ctx),
+ LLVMConstInt(ctx->ac.i32, 64, false), "");
+ return LLVMBuildAdd(builder, tmp, ac_get_thread_id(&ctx->ac), "");
+}
+
static LLVMValueRef ngg_get_vtx_cnt(struct radv_shader_context *ctx)
{
return ac_build_bfe(&ctx->ac, ctx->gs_tg_info,
false);
}
+static LLVMValueRef
+ngg_gs_get_vertex_storage(struct radv_shader_context *ctx)
+{
+ unsigned num_outputs = util_bitcount64(ctx->output_mask);
+
+ LLVMTypeRef elements[2] = {
+ LLVMArrayType(ctx->ac.i32, 4 * num_outputs),
+ LLVMArrayType(ctx->ac.i8, 4),
+ };
+ LLVMTypeRef type = LLVMStructTypeInContext(ctx->ac.context, elements, 2, false);
+ type = LLVMPointerType(LLVMArrayType(type, 0), AC_ADDR_SPACE_LDS);
+ return LLVMBuildBitCast(ctx->ac.builder, ctx->gs_ngg_emit, type, "");
+}
+
+/**
+ * Return a pointer to the LDS storage reserved for the N'th vertex, where N
+ * is in emit order; that is:
+ * - during the epilogue, N is the threadidx (relative to the entire threadgroup)
+ * - during vertex emit, i.e. while the API GS shader invocation is running,
+ * N = threadidx * gs_max_out_vertices + emitidx
+ *
+ * Goals of the LDS memory layout:
+ * 1. Eliminate bank conflicts on write for geometry shaders that have all emits
+ * in uniform control flow
+ * 2. Eliminate bank conflicts on read for export if, additionally, there is no
+ * culling
+ * 3. Agnostic to the number of waves (since we don't know it before compiling)
+ * 4. Allow coalescing of LDS instructions (ds_write_b128 etc.)
+ * 5. Avoid wasting memory.
+ *
+ * We use an AoS layout due to point 4 (this also helps point 3). In an AoS
+ * layout, elimination of bank conflicts requires that each vertex occupy an
+ * odd number of dwords. We use the additional dword to store the output stream
+ * index as well as a flag to indicate whether this vertex ends a primitive
+ * for rasterization.
+ *
+ * Swizzling is required to satisfy points 1 and 2 simultaneously.
+ *
+ * Vertices are stored in export order (gsthread * gs_max_out_vertices + emitidx).
+ * Indices are swizzled in groups of 32, which ensures point 1 without
+ * disturbing point 2.
+ *
+ * \return an LDS pointer to type {[N x i32], [4 x i8]}
+ */
+static LLVMValueRef
+ngg_gs_vertex_ptr(struct radv_shader_context *ctx, LLVMValueRef vertexidx)
+{
+ LLVMBuilderRef builder = ctx->ac.builder;
+ LLVMValueRef storage = ngg_gs_get_vertex_storage(ctx);
+
+ /* gs_max_out_vertices = 2^(write_stride_2exp) * some odd number */
+ unsigned write_stride_2exp = ffs(ctx->gs_max_out_vertices) - 1;
+ if (write_stride_2exp) {
+ LLVMValueRef row =
+ LLVMBuildLShr(builder, vertexidx,
+ LLVMConstInt(ctx->ac.i32, 5, false), "");
+ LLVMValueRef swizzle =
+ LLVMBuildAnd(builder, row,
+ LLVMConstInt(ctx->ac.i32, (1u << write_stride_2exp) - 1,
+ false), "");
+ vertexidx = LLVMBuildXor(builder, vertexidx, swizzle, "");
+ }
+
+ return ac_build_gep0(&ctx->ac, storage, vertexidx);
+}
+
+static LLVMValueRef
+ngg_gs_emit_vertex_ptr(struct radv_shader_context *ctx, LLVMValueRef gsthread,
+ LLVMValueRef emitidx)
+{
+ LLVMBuilderRef builder = ctx->ac.builder;
+ LLVMValueRef tmp;
+
+ tmp = LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false);
+ tmp = LLVMBuildMul(builder, tmp, gsthread, "");
+ const LLVMValueRef vertexidx = LLVMBuildAdd(builder, tmp, emitidx, "");
+ return ngg_gs_vertex_ptr(ctx, vertexidx);
+}
+
/* Send GS Alloc Req message from the first wave of the group to SPI.
* Message payload is:
* - bits 0..10: vertices in group
/* TODO: streamout */
- /* TODO: VS primitive ID */
- if (ctx->options->key.vs_common_out.export_prim_id)
- assert(0);
+ /* Copy Primitive IDs from GS threads to the LDS address corresponding
+ * to the ES thread of the provoking vertex.
+ */
+ if (ctx->stage == MESA_SHADER_VERTEX &&
+ ctx->options->key.vs_common_out.export_prim_id) {
+ /* TODO: streamout */
+
+ ac_build_ifcc(&ctx->ac, is_gs_thread, 5400);
+ /* Extract the PROVOKING_VTX_INDEX field. */
+ LLVMValueRef provoking_vtx_in_prim =
+ LLVMConstInt(ctx->ac.i32, 0, false);
+
+ /* provoking_vtx_index = vtxindex[provoking_vtx_in_prim]; */
+ LLVMValueRef indices = ac_build_gather_values(&ctx->ac, vtxindex, 3);
+ LLVMValueRef provoking_vtx_index =
+ LLVMBuildExtractElement(builder, indices, provoking_vtx_in_prim, "");
+
+ LLVMBuildStore(builder, ctx->abi.gs_prim_id,
+ ac_build_gep0(&ctx->ac, ctx->esgs_ring, provoking_vtx_index));
+ ac_build_endif(&ctx->ac, 5400);
+ }
/* TODO: primitive culling */
/* Export per-vertex data (positions and parameters). */
ac_nir_build_if(&if_state, ctx, is_es_thread);
{
- handle_vs_outputs_post(ctx, ctx->options->key.vs_common_out.export_prim_id,
+ struct radv_vs_output_info *outinfo =
+ ctx->stage == MESA_SHADER_TESS_EVAL ? &ctx->shader_info->tes.outinfo : &ctx->shader_info->vs.outinfo;
+
+ /* Exporting the primitive ID is handled below. */
+ /* TODO: use the new VS export path */
+ handle_vs_outputs_post(ctx, false,
ctx->options->key.vs_common_out.export_clip_dists,
- ctx->stage == MESA_SHADER_TESS_EVAL ? &ctx->shader_info->tes.outinfo : &ctx->shader_info->vs.outinfo);
+ outinfo);
+
+ if (ctx->options->key.vs_common_out.export_prim_id) {
+ unsigned param_count = outinfo->param_exports;
+ LLVMValueRef values[4];
+
+ if (ctx->stage == MESA_SHADER_VERTEX) {
+ /* Wait for GS stores to finish. */
+ ac_build_s_barrier(&ctx->ac);
+
+ tmp = ac_build_gep0(&ctx->ac, ctx->esgs_ring,
+ get_thread_id_in_tg(ctx));
+ values[0] = LLVMBuildLoad(builder, tmp, "");
+ } else {
+ assert(ctx->stage == MESA_SHADER_TESS_EVAL);
+ values[0] = ctx->abi.tes_patch_id;
+ }
+
+ values[0] = ac_to_float(&ctx->ac, values[0]);
+ for (unsigned j = 1; j < 4; j++)
+ values[j] = ctx->ac.f32_0;
+
+ radv_export_param(ctx, param_count, values, 0x1);
+
+ outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
+ outinfo->export_prim_id = true;
+ outinfo->param_exports = param_count;
+ }
}
ac_nir_build_endif(&if_state);
}
+static void gfx10_ngg_gs_emit_prologue(struct radv_shader_context *ctx)
+{
+ /* Zero out the part of LDS scratch that is used to accumulate the
+ * per-stream generated primitive count.
+ */
+ LLVMBuilderRef builder = ctx->ac.builder;
+ LLVMValueRef scratchptr = ctx->gs_ngg_scratch;
+ LLVMValueRef tid = get_thread_id_in_tg(ctx);
+ LLVMBasicBlockRef merge_block;
+ LLVMValueRef cond;
+
+ LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
+ LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
+ merge_block = LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
+
+ cond = LLVMBuildICmp(builder, LLVMIntULT, tid, LLVMConstInt(ctx->ac.i32, 4, false), "");
+ LLVMBuildCondBr(ctx->ac.builder, cond, then_block, merge_block);
+ LLVMPositionBuilderAtEnd(ctx->ac.builder, then_block);
+
+ LLVMValueRef ptr = ac_build_gep0(&ctx->ac, scratchptr, tid);
+ LLVMBuildStore(builder, ctx->ac.i32_0, ptr);
+
+ LLVMBuildBr(ctx->ac.builder, merge_block);
+ LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
+
+ ac_build_s_barrier(&ctx->ac);
+}
+
+static void gfx10_ngg_gs_emit_epilogue_1(struct radv_shader_context *ctx)
+{
+ LLVMBuilderRef builder = ctx->ac.builder;
+ LLVMValueRef i8_0 = LLVMConstInt(ctx->ac.i8, 0, false);
+ LLVMValueRef tmp;
+
+ /* Zero out remaining (non-emitted) primitive flags.
+ *
+ * Note: Alternatively, we could pass the relevant gs_next_vertex to
+ * the emit threads via LDS. This is likely worse in the expected
+ * typical case where each GS thread emits the full set of
+ * vertices.
+ */
+ for (unsigned stream = 0; stream < 4; ++stream) {
+ unsigned num_components;
+
+ num_components =
+ ctx->shader_info->info.gs.num_stream_output_components[stream];
+ if (!num_components)
+ continue;
+
+ const LLVMValueRef gsthread = get_thread_id_in_tg(ctx);
+
+ ac_build_bgnloop(&ctx->ac, 5100);
+
+ const LLVMValueRef vertexidx =
+ LLVMBuildLoad(builder, ctx->gs_next_vertex[stream], "");
+ tmp = LLVMBuildICmp(builder, LLVMIntUGE, vertexidx,
+ LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
+ ac_build_ifcc(&ctx->ac, tmp, 5101);
+ ac_build_break(&ctx->ac);
+ ac_build_endif(&ctx->ac, 5101);
+
+ tmp = LLVMBuildAdd(builder, vertexidx, ctx->ac.i32_1, "");
+ LLVMBuildStore(builder, tmp, ctx->gs_next_vertex[stream]);
+
+ tmp = ngg_gs_emit_vertex_ptr(ctx, gsthread, vertexidx);
+ LLVMValueRef gep_idx[3] = {
+ ctx->ac.i32_0, /* implied C-style array */
+ ctx->ac.i32_1, /* second entry of struct */
+ LLVMConstInt(ctx->ac.i32, stream, false),
+ };
+ tmp = LLVMBuildGEP(builder, tmp, gep_idx, 3, "");
+ LLVMBuildStore(builder, i8_0, tmp);
+
+ ac_build_endloop(&ctx->ac, 5100);
+ }
+}
+
+static void gfx10_ngg_gs_emit_epilogue_2(struct radv_shader_context *ctx)
+{
+ const unsigned verts_per_prim = si_conv_gl_prim_to_vertices(ctx->gs_output_prim);
+ LLVMBuilderRef builder = ctx->ac.builder;
+ LLVMValueRef tmp, tmp2;
+
+ ac_build_s_barrier(&ctx->ac);
+
+ const LLVMValueRef tid = get_thread_id_in_tg(ctx);
+ LLVMValueRef num_emit_threads = ngg_get_prim_cnt(ctx);
+
+ /* TODO: streamout */
+
+ /* TODO: culling */
+
+ /* Determine vertex liveness. */
+ LLVMValueRef vertliveptr = ac_build_alloca(&ctx->ac, ctx->ac.i1, "vertexlive");
+
+ tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, num_emit_threads, "");
+ ac_build_ifcc(&ctx->ac, tmp, 5120);
+ {
+ for (unsigned i = 0; i < verts_per_prim; ++i) {
+ const LLVMValueRef primidx =
+ LLVMBuildAdd(builder, tid,
+ LLVMConstInt(ctx->ac.i32, i, false), "");
+
+ if (i > 0) {
+ tmp = LLVMBuildICmp(builder, LLVMIntULT, primidx, num_emit_threads, "");
+ ac_build_ifcc(&ctx->ac, tmp, 5121 + i);
+ }
+
+ /* Load primitive liveness */
+ tmp = ngg_gs_vertex_ptr(ctx, primidx);
+ LLVMValueRef gep_idx[3] = {
+ ctx->ac.i32_0, /* implicit C-style array */
+ ctx->ac.i32_1, /* second value of struct */
+ ctx->ac.i32_0, /* stream 0 */
+ };
+ tmp = LLVMBuildGEP(builder, tmp, gep_idx, 3, "");
+ tmp = LLVMBuildLoad(builder, tmp, "");
+ const LLVMValueRef primlive =
+ LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
+
+ tmp = LLVMBuildLoad(builder, vertliveptr, "");
+ tmp = LLVMBuildOr(builder, tmp, primlive, ""),
+ LLVMBuildStore(builder, tmp, vertliveptr);
+
+ if (i > 0)
+ ac_build_endif(&ctx->ac, 5121 + i);
+ }
+ }
+ ac_build_endif(&ctx->ac, 5120);
+
+ /* Inclusive scan addition across the current wave. */
+ LLVMValueRef vertlive = LLVMBuildLoad(builder, vertliveptr, "");
+ struct ac_wg_scan vertlive_scan = {};
+ vertlive_scan.op = nir_op_iadd;
+ vertlive_scan.enable_reduce = true;
+ vertlive_scan.enable_exclusive = true;
+ vertlive_scan.src = vertlive;
+ vertlive_scan.scratch = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, ctx->ac.i32_0);
+ vertlive_scan.waveidx = get_wave_id_in_tg(ctx);
+ vertlive_scan.numwaves = get_tgsize(ctx);
+ vertlive_scan.maxwaves = 8;
+
+ ac_build_wg_scan(&ctx->ac, &vertlive_scan);
+
+ /* Skip all exports (including index exports) when possible. At least on
+ * early gfx10 revisions this is also to avoid hangs.
+ */
+ LLVMValueRef have_exports =
+ LLVMBuildICmp(builder, LLVMIntNE, vertlive_scan.result_reduce, ctx->ac.i32_0, "");
+ num_emit_threads =
+ LLVMBuildSelect(builder, have_exports, num_emit_threads, ctx->ac.i32_0, "");
+
+ /* Allocate export space. Send this message as early as possible, to
+ * hide the latency of the SQ <-> SPI roundtrip.
+ *
+ * Note: We could consider compacting primitives for export as well.
+ * PA processes 1 non-null prim / clock, but it fetches 4 DW of
+ * prim data per clock and skips null primitives at no additional
+ * cost. So compacting primitives can only be beneficial when
+ * there are 4 or more contiguous null primitives in the export
+ * (in the common case of single-dword prim exports).
+ */
+ build_sendmsg_gs_alloc_req(ctx, vertlive_scan.result_reduce, num_emit_threads);
+
+ /* Setup the reverse vertex compaction permutation. We re-use stream 1
+ * of the primitive liveness flags, relying on the fact that each
+ * threadgroup can have at most 256 threads. */
+ ac_build_ifcc(&ctx->ac, vertlive, 5130);
+ {
+ tmp = ngg_gs_vertex_ptr(ctx, vertlive_scan.result_exclusive);
+ LLVMValueRef gep_idx[3] = {
+ ctx->ac.i32_0, /* implicit C-style array */
+ ctx->ac.i32_1, /* second value of struct */
+ ctx->ac.i32_1, /* stream 1 */
+ };
+ tmp = LLVMBuildGEP(builder, tmp, gep_idx, 3, "");
+ tmp2 = LLVMBuildTrunc(builder, tid, ctx->ac.i8, "");
+ LLVMBuildStore(builder, tmp2, tmp);
+ }
+ ac_build_endif(&ctx->ac, 5130);
+
+ ac_build_s_barrier(&ctx->ac);
+
+ /* Export primitive data */
+ tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, num_emit_threads, "");
+ ac_build_ifcc(&ctx->ac, tmp, 5140);
+ {
+ struct ngg_prim prim = {};
+ prim.num_vertices = verts_per_prim;
+
+ tmp = ngg_gs_vertex_ptr(ctx, tid);
+ LLVMValueRef gep_idx[3] = {
+ ctx->ac.i32_0, /* implicit C-style array */
+ ctx->ac.i32_1, /* second value of struct */
+ ctx->ac.i32_0, /* primflag */
+ };
+ tmp = LLVMBuildGEP(builder, tmp, gep_idx, 3, "");
+ tmp = LLVMBuildLoad(builder, tmp, "");
+ prim.isnull = LLVMBuildICmp(builder, LLVMIntEQ, tmp,
+ LLVMConstInt(ctx->ac.i8, 0, false), "");
+
+ for (unsigned i = 0; i < verts_per_prim; ++i) {
+ prim.index[i] = LLVMBuildSub(builder, vertlive_scan.result_exclusive,
+ LLVMConstInt(ctx->ac.i32, verts_per_prim - i - 1, false), "");
+ prim.edgeflag[i] = ctx->ac.i1false;
+ }
+
+ build_export_prim(ctx, &prim);
+ }
+ ac_build_endif(&ctx->ac, 5140);
+
+ /* Export position and parameter data */
+ tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, vertlive_scan.result_reduce, "");
+ ac_build_ifcc(&ctx->ac, tmp, 5145);
+ {
+ struct radv_vs_output_info *outinfo = &ctx->shader_info->vs.outinfo;
+ bool export_view_index = ctx->options->key.has_multiview_view_index;
+ struct radv_shader_output_values *outputs;
+ unsigned noutput = 0;
+
+ /* Allocate a temporary array for the output values. */
+ unsigned num_outputs = util_bitcount64(ctx->output_mask) + export_view_index;
+ outputs = calloc(num_outputs, sizeof(outputs[0]));
+
+ memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
+ sizeof(outinfo->vs_output_param_offset));
+ outinfo->pos_exports = 0;
+
+ tmp = ngg_gs_vertex_ptr(ctx, tid);
+ LLVMValueRef gep_idx[3] = {
+ ctx->ac.i32_0, /* implicit C-style array */
+ ctx->ac.i32_1, /* second value of struct */
+ ctx->ac.i32_1, /* stream 1: source data index */
+ };
+ tmp = LLVMBuildGEP(builder, tmp, gep_idx, 3, "");
+ tmp = LLVMBuildLoad(builder, tmp, "");
+ tmp = LLVMBuildZExt(builder, tmp, ctx->ac.i32, "");
+ const LLVMValueRef vertexptr = ngg_gs_vertex_ptr(ctx, tmp);
+
+ if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
+ outinfo->writes_pointsize = true;
+ }
+
+ if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
+ outinfo->writes_layer = true;
+ }
+
+ if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
+ outinfo->writes_viewport_index = true;
+ }
+
+ unsigned out_idx = 0;
+ gep_idx[1] = ctx->ac.i32_0;
+ for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
+ if (!(ctx->output_mask & (1ull << i)))
+ continue;
+
+ outputs[noutput].slot_name = i;
+ outputs[noutput].slot_index = i == VARYING_SLOT_CLIP_DIST1;
+
+ outputs[noutput].usage_mask = ctx->shader_info->info.gs.output_usage_mask[i];
+ int length = util_last_bit(outputs[noutput].usage_mask);
+
+ for (unsigned j = 0; j < length; j++, out_idx++) {
+ gep_idx[2] = LLVMConstInt(ctx->ac.i32, out_idx, false);
+ tmp = LLVMBuildGEP(builder, vertexptr, gep_idx, 3, "");
+ tmp = LLVMBuildLoad(builder, tmp, "");
+
+ LLVMTypeRef type = LLVMGetAllocatedType(ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
+ if (ac_get_type_size(type) == 2) {
+ tmp = ac_to_integer(&ctx->ac, tmp);
+ tmp = LLVMBuildTrunc(ctx->ac.builder, tmp, ctx->ac.i16, "");
+ }
+
+ outputs[noutput].values[j] = ac_to_float(&ctx->ac, tmp);
+ }
+
+ for (unsigned j = length; j < 4; j++)
+ outputs[noutput].values[j] = LLVMGetUndef(ctx->ac.f32);
+
+ noutput++;
+ }
+
+ /* Export ViewIndex. */
+ if (export_view_index) {
+ outinfo->writes_layer = true;
+
+ outputs[noutput].slot_name = VARYING_SLOT_LAYER;
+ outputs[noutput].slot_index = 0;
+ outputs[noutput].usage_mask = 0x1;
+ outputs[noutput].values[0] = ac_to_float(&ctx->ac, ctx->abi.view_index);
+ for (unsigned j = 1; j < 4; j++)
+ outputs[noutput].values[j] = ctx->ac.f32_0;
+ noutput++;
+ }
+
+ radv_llvm_export_vs(ctx, outputs, noutput, outinfo,
+ ctx->options->key.vs_common_out.export_clip_dists);
+ FREE(outputs);
+ }
+ ac_build_endif(&ctx->ac, 5145);
+}
+
+static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context *ctx,
+ unsigned stream,
+ LLVMValueRef *addrs)
+{
+ LLVMBuilderRef builder = ctx->ac.builder;
+ LLVMValueRef tmp;
+ const LLVMValueRef vertexidx =
+ LLVMBuildLoad(builder, ctx->gs_next_vertex[stream], "");
+
+ /* If this thread has already emitted the declared maximum number of
+ * vertices, skip the write: excessive vertex emissions are not
+ * supposed to have any effect.
+ */
+ const LLVMValueRef can_emit =
+ LLVMBuildICmp(builder, LLVMIntULT, vertexidx,
+ LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
+ ac_build_kill_if_false(&ctx->ac, can_emit);
+
+ tmp = LLVMBuildAdd(builder, vertexidx, ctx->ac.i32_1, "");
+ tmp = LLVMBuildSelect(builder, can_emit, tmp, vertexidx, "");
+ LLVMBuildStore(builder, tmp, ctx->gs_next_vertex[stream]);
+
+ const LLVMValueRef vertexptr =
+ ngg_gs_emit_vertex_ptr(ctx, get_thread_id_in_tg(ctx), vertexidx);
+ unsigned out_idx = 0;
+ for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
+ unsigned output_usage_mask =
+ ctx->shader_info->info.gs.output_usage_mask[i];
+ uint8_t output_stream =
+ ctx->shader_info->info.gs.output_streams[i];
+ LLVMValueRef *out_ptr = &addrs[i * 4];
+ int length = util_last_bit(output_usage_mask);
+
+ if (!(ctx->output_mask & (1ull << i)) ||
+ output_stream != stream)
+ continue;
+
+ for (unsigned j = 0; j < length; j++, out_idx++) {
+ if (!(output_usage_mask & (1 << j)))
+ continue;
+
+ LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
+ out_ptr[j], "");
+ LLVMValueRef gep_idx[3] = {
+ ctx->ac.i32_0, /* implied C-style array */
+ ctx->ac.i32_0, /* first entry of struct */
+ LLVMConstInt(ctx->ac.i32, out_idx, false),
+ };
+ LLVMValueRef ptr = LLVMBuildGEP(builder, vertexptr, gep_idx, 3, "");
+
+ out_val = ac_to_integer(&ctx->ac, out_val);
+ out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
+
+ LLVMBuildStore(builder, out_val, ptr);
+ }
+ }
+ assert(out_idx * 4 <= ctx->gsvs_vertex_size);
+
+ /* Determine and store whether this vertex completed a primitive. */
+ const LLVMValueRef curverts = LLVMBuildLoad(builder, ctx->gs_curprim_verts[stream], "");
+
+ tmp = LLVMConstInt(ctx->ac.i32, si_conv_gl_prim_to_vertices(ctx->gs_output_prim) - 1, false);
+ const LLVMValueRef iscompleteprim =
+ LLVMBuildICmp(builder, LLVMIntUGE, curverts, tmp, "");
+
+ tmp = LLVMBuildAdd(builder, curverts, ctx->ac.i32_1, "");
+ LLVMBuildStore(builder, tmp, ctx->gs_curprim_verts[stream]);
+
+ LLVMValueRef gep_idx[3] = {
+ ctx->ac.i32_0, /* implied C-style array */
+ ctx->ac.i32_1, /* second struct entry */
+ LLVMConstInt(ctx->ac.i32, stream, false),
+ };
+ const LLVMValueRef primflagptr =
+ LLVMBuildGEP(builder, vertexptr, gep_idx, 3, "");
+
+ tmp = LLVMBuildZExt(builder, iscompleteprim, ctx->ac.i8, "");
+ LLVMBuildStore(builder, tmp, primflagptr);
+
+ tmp = LLVMBuildLoad(builder, ctx->gs_generated_prims[stream], "");
+ tmp = LLVMBuildAdd(builder, tmp, LLVMBuildZExt(builder, iscompleteprim, ctx->ac.i32, ""), "");
+ LLVMBuildStore(builder, tmp, ctx->gs_generated_prims[stream]);
+}
+
static void
write_tess_factors(struct radv_shader_context *ctx)
{
static void
emit_gs_epilogue(struct radv_shader_context *ctx)
{
+ if (ctx->options->key.vs_common_out.as_ngg) {
+ gfx10_ngg_gs_emit_epilogue_1(ctx);
+ return;
+ }
+
+ if (ctx->ac.chip_class >= GFX10)
+ LLVMBuildFence(ctx->ac.builder, LLVMAtomicOrderingRelease, false, "");
+
ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
}
case MESA_SHADER_VERTEX:
if (ctx->options->key.vs_common_out.as_ls)
handle_ls_outputs_post(ctx);
- else if (ctx->options->key.vs_common_out.as_ngg)
- break; /* handled outside of the shader body */
else if (ctx->options->key.vs_common_out.as_es)
handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
+ else if (ctx->options->key.vs_common_out.as_ngg)
+ break; /* handled outside of the shader body */
else
handle_vs_outputs_post(ctx, ctx->options->key.vs_common_out.export_prim_id,
ctx->options->key.vs_common_out.export_clip_dists,
ctx->gs_wave_id = ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 16, 8);
}
+/* Ensure that the esgs ring is declared.
+ *
+ * We declare it with 64KB alignment as a hint that the
+ * pointer value will always be 0.
+ */
+static void declare_esgs_ring(struct radv_shader_context *ctx)
+{
+ if (ctx->esgs_ring)
+ return;
+
+ assert(!LLVMGetNamedGlobal(ctx->ac.module, "esgs_ring"));
+
+ ctx->esgs_ring = LLVMAddGlobalInAddressSpace(
+ ctx->ac.module, LLVMArrayType(ctx->ac.i32, 0),
+ "esgs_ring",
+ AC_ADDR_SPACE_LDS);
+ LLVMSetLinkage(ctx->esgs_ring, LLVMExternalLinkage);
+ LLVMSetAlignment(ctx->esgs_ring, 64 * 1024);
+}
static
LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm,
ctx.gs_next_vertex[i] =
ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
}
+ if (ctx.options->key.vs_common_out.as_ngg) {
+ for (unsigned i = 0; i < 4; ++i) {
+ ctx.gs_curprim_verts[i] =
+ ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
+ ctx.gs_generated_prims[i] =
+ ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
+ }
+
+ /* TODO: streamout */
+
+ LLVMTypeRef ai32 = LLVMArrayType(ctx.ac.i32, 8);
+ ctx.gs_ngg_scratch =
+ LLVMAddGlobalInAddressSpace(ctx.ac.module,
+ ai32, "ngg_scratch", AC_ADDR_SPACE_LDS);
+ LLVMSetInitializer(ctx.gs_ngg_scratch, LLVMGetUndef(ai32));
+ LLVMSetAlignment(ctx.gs_ngg_scratch, 4);
+
+ ctx.gs_ngg_emit = LLVMBuildIntToPtr(ctx.ac.builder, ctx.ac.i32_0,
+ LLVMPointerType(LLVMArrayType(ctx.ac.i32, 0), AC_ADDR_SPACE_LDS),
+ "ngg_emit");
+ }
+
ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
+ ctx.gs_output_prim = shaders[i]->info.gs.output_primitive;
ctx.abi.load_inputs = load_gs_input;
ctx.abi.emit_primitive = visit_end_primitive;
} else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
ctx.abi.emit_kill = radv_emit_kill;
}
+ if (shaders[i]->info.stage == MESA_SHADER_VERTEX &&
+ ctx.options->key.vs_common_out.as_ngg &&
+ ctx.options->key.vs_common_out.export_prim_id) {
+ declare_esgs_ring(&ctx);
+ }
+
if (i)
ac_emit_barrier(&ctx.ac, ctx.stage);
LLVMBasicBlockRef merge_block;
if (shader_count >= 2 || is_ngg) {
+
+ if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY &&
+ ctx.options->key.vs_common_out.as_ngg) {
+ gfx10_ngg_gs_emit_prologue(&ctx);
+ }
+
LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
ctx.options->key.vs_common_out.as_ngg &&
i == shader_count - 1) {
handle_ngg_outputs_post(&ctx);
+ } else if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY &&
+ ctx.options->key.vs_common_out.as_ngg) {
+ gfx10_ngg_gs_emit_epilogue_2(&ctx);
}
if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
LLVMBuildRetVoid(ctx.ac.builder);
- if (options->dump_preoptir)
+ if (options->dump_preoptir) {
+ fprintf(stderr, "%s LLVM IR:\n\n",
+ radv_get_shader_name(shader_info,
+ shaders[shader_count - 1]->info.stage));
ac_dump_module(ctx.ac.module);
+ fprintf(stderr, "\n");
+ }
ac_llvm_finalize_module(&ctx, ac_llvm->passmgr, options);
struct radv_shader_binary **rbinary,
struct radv_shader_variant_info *shader_info,
gl_shader_stage stage,
+ const char *name,
const struct radv_nir_compiler_options *options)
{
char *elf_buffer = NULL;
size_t elf_size = 0;
char *llvm_ir_string = NULL;
- if (options->dump_shader)
+
+ if (options->dump_shader) {
+ fprintf(stderr, "%s LLVM IR:\n\n", name);
ac_dump_module(llvm_module);
+ fprintf(stderr, "\n");
+ }
if (options->record_llvm_ir) {
char *llvm_ir = LLVMPrintModuleToString(llvm_module);
options);
ac_compile_llvm_module(ac_llvm, llvm_module, rbinary, shader_info,
- nir[nir_count - 1]->info.stage, options);
+ nir[nir_count - 1]->info.stage,
+ radv_get_shader_name(shader_info,
+ nir[nir_count - 1]->info.stage),
+ options);
for (int i = 0; i < nir_count; ++i)
ac_fill_shader_info(shader_info, nir[i], options);
ac_llvm_finalize_module(&ctx, ac_llvm->passmgr, options);
ac_compile_llvm_module(ac_llvm, ctx.ac.module, rbinary, shader_info,
- MESA_SHADER_VERTEX, options);
+ MESA_SHADER_VERTEX, "GS Copy Shader", options);
(*rbinary)->is_gs_copy_shader = true;
}