#include "util/debug.h"
#include "ac_exp_param.h"
#include "ac_shader_util.h"
+#include "main/menums.h"
struct radv_blend_state {
- uint32_t blend_enable;
+ uint32_t blend_enable_4bit;
uint32_t need_src_alpha;
uint32_t cb_color_control;
uint32_t cb_target_mask;
+ uint32_t cb_target_enabled_4bit;
uint32_t sx_mrt_blend_opt[8];
uint32_t cb_blend_control[8];
uint32_t cb_shader_mask;
uint32_t db_alpha_to_mask;
+ uint32_t commutative_4bit;
+
bool single_cb_enable;
bool mrt0_is_dual_src;
};
+struct radv_dsa_order_invariance {
+ /* Whether the final result in Z/S buffers is guaranteed to be
+ * invariant under changes to the order in which fragments arrive.
+ */
+ bool zs;
+
+ /* Whether the set of fragments that pass the combined Z/S test is
+ * guaranteed to be invariant under changes to the order in which
+ * fragments arrive.
+ */
+ bool pass_set;
+};
+
struct radv_tessellation_state {
uint32_t ls_hs_config;
unsigned num_patches;
if (scratch_bytes_per_wave && max_waves < min_waves) {
/* Not really true at this moment, but will be true on first
* execution. Avoid having hanging shaders. */
- return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
+ return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
}
pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
pipeline->max_waves = max_waves;
return VK_SUCCESS;
}
+static uint32_t si_translate_blend_logic_op(VkLogicOp op)
+{
+ switch (op) {
+ case VK_LOGIC_OP_CLEAR:
+ return V_028808_ROP3_CLEAR;
+ case VK_LOGIC_OP_AND:
+ return V_028808_ROP3_AND;
+ case VK_LOGIC_OP_AND_REVERSE:
+ return V_028808_ROP3_AND_REVERSE;
+ case VK_LOGIC_OP_COPY:
+ return V_028808_ROP3_COPY;
+ case VK_LOGIC_OP_AND_INVERTED:
+ return V_028808_ROP3_AND_INVERTED;
+ case VK_LOGIC_OP_NO_OP:
+ return V_028808_ROP3_NO_OP;
+ case VK_LOGIC_OP_XOR:
+ return V_028808_ROP3_XOR;
+ case VK_LOGIC_OP_OR:
+ return V_028808_ROP3_OR;
+ case VK_LOGIC_OP_NOR:
+ return V_028808_ROP3_NOR;
+ case VK_LOGIC_OP_EQUIVALENT:
+ return V_028808_ROP3_EQUIVALENT;
+ case VK_LOGIC_OP_INVERT:
+ return V_028808_ROP3_INVERT;
+ case VK_LOGIC_OP_OR_REVERSE:
+ return V_028808_ROP3_OR_REVERSE;
+ case VK_LOGIC_OP_COPY_INVERTED:
+ return V_028808_ROP3_COPY_INVERTED;
+ case VK_LOGIC_OP_OR_INVERTED:
+ return V_028808_ROP3_OR_INVERTED;
+ case VK_LOGIC_OP_NAND:
+ return V_028808_ROP3_NAND;
+ case VK_LOGIC_OP_SET:
+ return V_028808_ROP3_SET;
+ default:
+ unreachable("Unhandled logic op");
+ }
+}
+
+
static uint32_t si_translate_blend_function(VkBlendOp op)
{
switch (op) {
RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
unsigned col_format = 0;
+ unsigned num_targets;
for (unsigned i = 0; i < (blend->single_cb_enable ? 1 : subpass->color_count); ++i) {
unsigned cf;
cf = V_028714_SPI_SHADER_ZERO;
} else {
struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
+ bool blend_enable =
+ blend->blend_enable_4bit & (0xfu << (i * 4));
cf = si_choose_spi_color_format(attachment->format,
- blend->blend_enable & (1 << i),
+ blend_enable,
blend->need_src_alpha & (1 << i));
}
col_format |= cf << (4 * i);
}
+ /* If the i-th target format is set, all previous target formats must
+ * be non-zero to avoid hangs.
+ */
+ num_targets = (util_last_bit(col_format) + 3) / 4;
+ for (unsigned i = 0; i < num_targets; i++) {
+ if (!(col_format & (0xf << (i * 4)))) {
+ col_format |= V_028714_SPI_SHADER_32_R << (i * 4);
+ }
+ }
+
blend->cb_shader_mask = ac_get_cb_shader_mask(col_format);
if (blend->mrt0_is_dual_src)
}
}
+static void
+radv_blend_check_commutativity(struct radv_blend_state *blend,
+ VkBlendOp op, VkBlendFactor src,
+ VkBlendFactor dst, unsigned chanmask)
+{
+ /* Src factor is allowed when it does not depend on Dst. */
+ static const uint32_t src_allowed =
+ (1u << VK_BLEND_FACTOR_ONE) |
+ (1u << VK_BLEND_FACTOR_SRC_COLOR) |
+ (1u << VK_BLEND_FACTOR_SRC_ALPHA) |
+ (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE) |
+ (1u << VK_BLEND_FACTOR_CONSTANT_COLOR) |
+ (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA) |
+ (1u << VK_BLEND_FACTOR_SRC1_COLOR) |
+ (1u << VK_BLEND_FACTOR_SRC1_ALPHA) |
+ (1u << VK_BLEND_FACTOR_ZERO) |
+ (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR) |
+ (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA) |
+ (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR) |
+ (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA) |
+ (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR) |
+ (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA);
+
+ if (dst == VK_BLEND_FACTOR_ONE &&
+ (src_allowed & (1u << src))) {
+ /* Addition is commutative, but floating point addition isn't
+ * associative: subtle changes can be introduced via different
+ * rounding. Be conservative, only enable for min and max.
+ */
+ if (op == VK_BLEND_OP_MAX || op == VK_BLEND_OP_MIN)
+ blend->commutative_4bit |= chanmask;
+ }
+}
+
static struct radv_blend_state
radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
const VkGraphicsPipelineCreateInfo *pCreateInfo,
}
blend.cb_color_control = 0;
if (vkblend->logicOpEnable)
- blend.cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
+ blend.cb_color_control |= S_028808_ROP3(si_translate_blend_logic_op(vkblend->logicOp));
else
- blend.cb_color_control |= S_028808_ROP3(0xcc);
+ blend.cb_color_control |= S_028808_ROP3(V_028808_ROP3_COPY);
blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
continue;
blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
+ blend.cb_target_enabled_4bit |= 0xf << (4 * i);
if (!att->blendEnable) {
blend.cb_blend_control[i] = blend_cntl;
continue;
dstA = VK_BLEND_FACTOR_ONE;
}
+ radv_blend_check_commutativity(&blend, eqRGB, srcRGB, dstRGB,
+ 0x7 << (4 * i));
+ radv_blend_check_commutativity(&blend, eqA, srcA, dstA,
+ 0x8 << (4 * i));
+
/* Blending optimizations for RB+.
* These transformations don't change the behavior.
*
}
blend.cb_blend_control[i] = blend_cntl;
- blend.blend_enable |= 1 << i;
+ blend.blend_enable_4bit |= 0xfu << (i * 4);
if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
return ps_iter_samples;
}
+static bool
+radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
+{
+ return pCreateInfo->depthTestEnable &&
+ pCreateInfo->depthWriteEnable &&
+ pCreateInfo->depthCompareOp != VK_COMPARE_OP_NEVER;
+}
+
+static bool
+radv_writes_stencil(const VkStencilOpState *state)
+{
+ return state->writeMask &&
+ (state->failOp != VK_STENCIL_OP_KEEP ||
+ state->passOp != VK_STENCIL_OP_KEEP ||
+ state->depthFailOp != VK_STENCIL_OP_KEEP);
+}
+
+static bool
+radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
+{
+ return pCreateInfo->stencilTestEnable &&
+ (radv_writes_stencil(&pCreateInfo->front) ||
+ radv_writes_stencil(&pCreateInfo->back));
+}
+
+static bool
+radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
+{
+ return radv_is_depth_write_enabled(pCreateInfo) ||
+ radv_is_stencil_write_enabled(pCreateInfo);
+}
+
+static bool
+radv_order_invariant_stencil_op(VkStencilOp op)
+{
+ /* REPLACE is normally order invariant, except when the stencil
+ * reference value is written by the fragment shader. Tracking this
+ * interaction does not seem worth the effort, so be conservative.
+ */
+ return op != VK_STENCIL_OP_INCREMENT_AND_CLAMP &&
+ op != VK_STENCIL_OP_DECREMENT_AND_CLAMP &&
+ op != VK_STENCIL_OP_REPLACE;
+}
+
+static bool
+radv_order_invariant_stencil_state(const VkStencilOpState *state)
+{
+ /* Compute whether, assuming Z writes are disabled, this stencil state
+ * is order invariant in the sense that the set of passing fragments as
+ * well as the final stencil buffer result does not depend on the order
+ * of fragments.
+ */
+ return !state->writeMask ||
+ /* The following assumes that Z writes are disabled. */
+ (state->compareOp == VK_COMPARE_OP_ALWAYS &&
+ radv_order_invariant_stencil_op(state->passOp) &&
+ radv_order_invariant_stencil_op(state->depthFailOp)) ||
+ (state->compareOp == VK_COMPARE_OP_NEVER &&
+ radv_order_invariant_stencil_op(state->failOp));
+}
+
+static bool
+radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline,
+ struct radv_blend_state *blend,
+ const VkGraphicsPipelineCreateInfo *pCreateInfo)
+{
+ RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
+ struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
+ unsigned colormask = blend->cb_target_enabled_4bit;
+
+ if (!pipeline->device->physical_device->out_of_order_rast_allowed)
+ return false;
+
+ /* Be conservative if a logic operation is enabled with color buffers. */
+ if (colormask && pCreateInfo->pColorBlendState->logicOpEnable)
+ return false;
+
+ /* Default depth/stencil invariance when no attachment is bound. */
+ struct radv_dsa_order_invariance dsa_order_invariant = {
+ .zs = true, .pass_set = true
+ };
+
+ if (pCreateInfo->pDepthStencilState &&
+ subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
+ const VkPipelineDepthStencilStateCreateInfo *vkds =
+ pCreateInfo->pDepthStencilState;
+ struct radv_render_pass_attachment *attachment =
+ pass->attachments + subpass->depth_stencil_attachment.attachment;
+ bool has_stencil = vk_format_is_stencil(attachment->format);
+ struct radv_dsa_order_invariance order_invariance[2];
+ struct radv_shader_variant *ps =
+ pipeline->shaders[MESA_SHADER_FRAGMENT];
+
+ /* Compute depth/stencil order invariance in order to know if
+ * it's safe to enable out-of-order.
+ */
+ bool zfunc_is_ordered =
+ vkds->depthCompareOp == VK_COMPARE_OP_NEVER ||
+ vkds->depthCompareOp == VK_COMPARE_OP_LESS ||
+ vkds->depthCompareOp == VK_COMPARE_OP_LESS_OR_EQUAL ||
+ vkds->depthCompareOp == VK_COMPARE_OP_GREATER ||
+ vkds->depthCompareOp == VK_COMPARE_OP_GREATER_OR_EQUAL;
+
+ bool nozwrite_and_order_invariant_stencil =
+ !radv_is_ds_write_enabled(vkds) ||
+ (!radv_is_depth_write_enabled(vkds) &&
+ radv_order_invariant_stencil_state(&vkds->front) &&
+ radv_order_invariant_stencil_state(&vkds->back));
+
+ order_invariance[1].zs =
+ nozwrite_and_order_invariant_stencil ||
+ (!radv_is_stencil_write_enabled(vkds) &&
+ zfunc_is_ordered);
+ order_invariance[0].zs =
+ !radv_is_depth_write_enabled(vkds) || zfunc_is_ordered;
+
+ order_invariance[1].pass_set =
+ nozwrite_and_order_invariant_stencil ||
+ (!radv_is_stencil_write_enabled(vkds) &&
+ (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
+ vkds->depthCompareOp == VK_COMPARE_OP_NEVER));
+ order_invariance[0].pass_set =
+ !radv_is_depth_write_enabled(vkds) ||
+ (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
+ vkds->depthCompareOp == VK_COMPARE_OP_NEVER);
+
+ dsa_order_invariant = order_invariance[has_stencil];
+ if (!dsa_order_invariant.zs)
+ return false;
+
+ /* The set of PS invocations is always order invariant,
+ * except when early Z/S tests are requested.
+ */
+ if (ps &&
+ ps->info.info.ps.writes_memory &&
+ ps->info.fs.early_fragment_test &&
+ !dsa_order_invariant.pass_set)
+ return false;
+
+ /* Determine if out-of-order rasterization should be disabled
+ * when occlusion queries are used.
+ */
+ pipeline->graphics.disable_out_of_order_rast_for_occlusion =
+ !dsa_order_invariant.pass_set;
+ }
+
+ /* No color buffers are enabled for writing. */
+ if (!colormask)
+ return true;
+
+ unsigned blendmask = colormask & blend->blend_enable_4bit;
+
+ if (blendmask) {
+ /* Only commutative blending. */
+ if (blendmask & ~blend->commutative_4bit)
+ return false;
+
+ if (!dsa_order_invariant.pass_set)
+ return false;
+ }
+
+ if (colormask & ~blendmask)
+ return false;
+
+ return true;
+}
+
static void
radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
+ struct radv_blend_state *blend,
const VkGraphicsPipelineCreateInfo *pCreateInfo)
{
const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
struct radv_multisample_state *ms = &pipeline->graphics.ms;
unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
+ bool out_of_order_rast = false;
int ps_iter_samples = 1;
uint32_t mask = 0xffff;
const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
+ /* Out-of-order rasterization is explicitly enabled by the
+ * application.
+ */
+ out_of_order_rast = true;
+ } else {
+ /* Determine if the driver can enable out-of-order
+ * rasterization internally.
+ */
+ out_of_order_rast =
+ radv_pipeline_out_of_order_rast(pipeline, blend, pCreateInfo);
+ }
+
+ if (out_of_order_rast) {
ms->pa_sc_mode_cntl_1 |= S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(1) |
- S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7);
+ S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7);
}
if (vkms && vkms->pSampleMask) {
}
struct radv_shader_variant *
-radv_get_vertex_shader(struct radv_pipeline *pipeline)
-{
- if (pipeline->shaders[MESA_SHADER_VERTEX])
- return pipeline->shaders[MESA_SHADER_VERTEX];
- if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
- return pipeline->shaders[MESA_SHADER_TESS_CTRL];
- return pipeline->shaders[MESA_SHADER_GEOMETRY];
-}
-
-static struct radv_shader_variant *
-radv_get_tess_eval_shader(struct radv_pipeline *pipeline)
-{
- if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
- return pipeline->shaders[MESA_SHADER_TESS_EVAL];
- return pipeline->shaders[MESA_SHADER_GEOMETRY];
+radv_get_shader(struct radv_pipeline *pipeline,
+ gl_shader_stage stage)
+{
+ if (stage == MESA_SHADER_VERTEX) {
+ if (pipeline->shaders[MESA_SHADER_VERTEX])
+ return pipeline->shaders[MESA_SHADER_VERTEX];
+ if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
+ return pipeline->shaders[MESA_SHADER_TESS_CTRL];
+ if (pipeline->shaders[MESA_SHADER_GEOMETRY])
+ return pipeline->shaders[MESA_SHADER_GEOMETRY];
+ } else if (stage == MESA_SHADER_TESS_EVAL) {
+ if (!radv_pipeline_has_tess(pipeline))
+ return NULL;
+ if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
+ return pipeline->shaders[MESA_SHADER_TESS_EVAL];
+ if (pipeline->shaders[MESA_SHADER_GEOMETRY])
+ return pipeline->shaders[MESA_SHADER_GEOMETRY];
+ }
+ return pipeline->shaders[stage];
}
static struct radv_tessellation_state
S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
tess.num_patches = num_patches;
- struct radv_shader_variant *tes = radv_get_tess_eval_shader(pipeline);
+ struct radv_shader_variant *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL);
unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
switch (tes->info.tes.primitive_mode) {
ac_lower_indirect_derefs(ordered_shaders[i],
pipeline->device->physical_device->rad_info.chip_class);
}
- radv_optimize_nir(ordered_shaders[i]);
+ radv_optimize_nir(ordered_shaders[i], false);
if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
ac_lower_indirect_derefs(ordered_shaders[i - 1],
pipeline->device->physical_device->rad_info.chip_class);
}
- radv_optimize_nir(ordered_shaders[i - 1]);
+ radv_optimize_nir(ordered_shaders[i - 1], false);
}
}
}
{
const VkPipelineVertexInputStateCreateInfo *input_state =
pCreateInfo->pVertexInputState;
+ const VkPipelineVertexInputDivisorStateCreateInfoEXT *divisor_state =
+ vk_find_struct_const(input_state->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
+
struct radv_pipeline_key key;
memset(&key, 0, sizeof(key));
+ if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
+ key.optimisations_disabled = 1;
+
key.has_multiview_view_index = has_view_index;
uint32_t binding_input_rate = 0;
+ uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
- if (input_state->pVertexBindingDescriptions[i].inputRate)
- binding_input_rate |= 1u << input_state->pVertexBindingDescriptions[i].binding;
+ if (input_state->pVertexBindingDescriptions[i].inputRate) {
+ unsigned binding = input_state->pVertexBindingDescriptions[i].binding;
+ binding_input_rate |= 1u << binding;
+ instance_rate_divisors[binding] = 1;
+ }
+ }
+ if (divisor_state) {
+ for (unsigned i = 0; i < divisor_state->vertexBindingDivisorCount; ++i) {
+ instance_rate_divisors[divisor_state->pVertexBindingDivisors[i].binding] =
+ divisor_state->pVertexBindingDivisors[i].divisor;
+ }
}
for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
- unsigned binding;
- binding = input_state->pVertexAttributeDescriptions[i].binding;
- if (binding_input_rate & (1u << binding))
- key.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location;
+ unsigned location = input_state->pVertexAttributeDescriptions[i].location;
+ unsigned binding = input_state->pVertexAttributeDescriptions[i].binding;
+ if (binding_input_rate & (1u << binding)) {
+ key.instance_rate_inputs |= 1u << location;
+ key.instance_rate_divisors[location] = instance_rate_divisors[binding];
+ }
+
+ if (pipeline->device->physical_device->rad_info.chip_class <= VI &&
+ pipeline->device->physical_device->rad_info.family != CHIP_STONEY) {
+ VkFormat format = input_state->pVertexAttributeDescriptions[i].format;
+ uint64_t adjust;
+ switch(format) {
+ case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
+ case VK_FORMAT_A2B10G10R10_SNORM_PACK32:
+ adjust = RADV_ALPHA_ADJUST_SNORM;
+ break;
+ case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
+ case VK_FORMAT_A2B10G10R10_SSCALED_PACK32:
+ adjust = RADV_ALPHA_ADJUST_SSCALED;
+ break;
+ case VK_FORMAT_A2R10G10B10_SINT_PACK32:
+ case VK_FORMAT_A2B10G10R10_SINT_PACK32:
+ adjust = RADV_ALPHA_ADJUST_SINT;
+ break;
+ default:
+ adjust = 0;
+ break;
+ }
+ key.vertex_alpha_adjust |= adjust << (2 * location);
+ }
}
if (pCreateInfo->pTessellationState)
pCreateInfo->pMultisampleState->rasterizationSamples > 1) {
uint32_t num_samples = pCreateInfo->pMultisampleState->rasterizationSamples;
uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo->pMultisampleState);
- key.multisample = true;
- key.log2_num_samples = util_logbase2(num_samples);
+ key.num_samples = num_samples;
key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
}
nir_shader **nir)
{
keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
+ keys[MESA_SHADER_VERTEX].vs.alpha_adjust = key->vertex_alpha_adjust;
+ for (unsigned i = 0; i < MAX_VERTEX_ATTRIBS; ++i)
+ keys[MESA_SHADER_VERTEX].vs.instance_rate_divisors[i] = key->instance_rate_divisors[i];
if (nir[MESA_SHADER_TESS_CTRL]) {
keys[MESA_SHADER_VERTEX].vs.as_ls = true;
for(int i = 0; i < MESA_SHADER_STAGES; ++i)
keys[i].has_multiview_view_index = key->has_multiview_view_index;
- keys[MESA_SHADER_FRAGMENT].fs.multisample = key->multisample;
keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
- keys[MESA_SHADER_FRAGMENT].fs.log2_num_samples = key->log2_num_samples;
+ keys[MESA_SHADER_FRAGMENT].fs.num_samples = key->num_samples;
}
static void
struct radv_device *device,
struct radv_pipeline_cache *cache,
struct radv_pipeline_key key,
- const VkPipelineShaderStageCreateInfo **pStages)
+ const VkPipelineShaderStageCreateInfo **pStages,
+ const VkPipelineCreateFlags flags)
{
struct radv_shader_module fs_m = {0};
struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
_mesa_sha1_compute(modules[i]->nir->info.name,
strlen(modules[i]->nir->info.name),
modules[i]->sha1);
+
+ pipeline->active_stages |= mesa_to_vk_shader_stage(i);
}
}
if (radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders) &&
(!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
- for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
- if (pipeline->shaders[i])
- pipeline->active_stages |= mesa_to_vk_shader_stage(i);
- }
return;
}
nir[i] = radv_shader_compile_to_nir(device, modules[i],
stage ? stage->pName : "main", i,
- stage ? stage->pSpecializationInfo : NULL);
- pipeline->active_stages |= mesa_to_vk_shader_stage(i);
+ stage ? stage->pSpecializationInfo : NULL,
+ flags);
/* We don't want to alter meta shaders IR directly so clone it
* first.
if (i != last)
mask = mask | nir_var_shader_out;
- nir_lower_io_to_scalar_early(nir[i], mask);
- radv_optimize_nir(nir[i]);
+ if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)) {
+ nir_lower_io_to_scalar_early(nir[i], mask);
+ radv_optimize_nir(nir[i], false);
+ }
}
}
merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
}
- radv_link_shaders(pipeline, nir);
+ if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
+ radv_link_shaders(pipeline, nir);
for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
- if (modules[i] && radv_can_dump_shader(device, modules[i]))
+ if (radv_can_dump_shader(device, modules[i], false))
nir_print_shader(nir[i], stderr);
}
}
static void
-radv_pipeline_generate_binning_state(struct radeon_winsys_cs *cs,
+radv_pipeline_generate_binning_state(struct radeon_cmdbuf *cs,
struct radv_pipeline *pipeline,
const VkGraphicsPipelineCreateInfo *pCreateInfo)
{
static void
-radv_pipeline_generate_depth_stencil_state(struct radeon_winsys_cs *cs,
+radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *cs,
struct radv_pipeline *pipeline,
const VkGraphicsPipelineCreateInfo *pCreateInfo,
const struct radv_graphics_pipeline_create_info *extra)
}
static void
-radv_pipeline_generate_blend_state(struct radeon_winsys_cs *cs,
+radv_pipeline_generate_blend_state(struct radeon_cmdbuf *cs,
struct radv_pipeline *pipeline,
const struct radv_blend_state *blend)
{
radeon_set_context_reg_seq(cs, R_028760_SX_MRT0_BLEND_OPT, 8);
radeon_emit_array(cs, blend->sx_mrt_blend_opt, 8);
-
- radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
- radeon_emit(cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
- radeon_emit(cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
- radeon_emit(cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
}
radeon_set_context_reg(cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
radeon_set_context_reg(cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
+
+ pipeline->graphics.col_format = blend->spi_shader_col_format;
+ pipeline->graphics.cb_target_mask = blend->cb_target_mask;
}
static void
-radv_pipeline_generate_raster_state(struct radeon_winsys_cs *cs,
+radv_pipeline_generate_raster_state(struct radeon_cmdbuf *cs,
const VkGraphicsPipelineCreateInfo *pCreateInfo)
{
const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
static void
-radv_pipeline_generate_multisample_state(struct radeon_winsys_cs *cs,
+radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *cs,
struct radv_pipeline *pipeline)
{
struct radv_multisample_state *ms = &pipeline->graphics.ms;
radeon_set_context_reg(cs, R_028804_DB_EQAA, ms->db_eqaa);
radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
-
- if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
- uint32_t offset;
- struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
- uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_FRAGMENT];
- if (loc->sgpr_idx == -1)
- return;
- assert(loc->num_sgprs == 1);
- assert(!loc->indirect);
- switch (pipeline->graphics.ms.num_samples) {
- default:
- offset = 0;
- break;
- case 2:
- offset = 1;
- break;
- case 4:
- offset = 3;
- break;
- case 8:
- offset = 7;
- break;
- case 16:
- offset = 15;
- break;
- }
-
- radeon_set_sh_reg(cs, base_reg + loc->sgpr_idx * 4, offset);
- }
}
static void
-radv_pipeline_generate_vgt_gs_mode(struct radeon_winsys_cs *cs,
+radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *cs,
const struct radv_pipeline *pipeline)
{
const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
}
static void
-radv_pipeline_generate_hw_vs(struct radeon_winsys_cs *cs,
+radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *cs,
struct radv_pipeline *pipeline,
struct radv_shader_variant *shader)
{
}
static void
-radv_pipeline_generate_hw_es(struct radeon_winsys_cs *cs,
+radv_pipeline_generate_hw_es(struct radeon_cmdbuf *cs,
struct radv_pipeline *pipeline,
struct radv_shader_variant *shader)
{
}
static void
-radv_pipeline_generate_hw_ls(struct radeon_winsys_cs *cs,
+radv_pipeline_generate_hw_ls(struct radeon_cmdbuf *cs,
struct radv_pipeline *pipeline,
struct radv_shader_variant *shader,
const struct radv_tessellation_state *tess)
}
static void
-radv_pipeline_generate_hw_hs(struct radeon_winsys_cs *cs,
+radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs,
struct radv_pipeline *pipeline,
struct radv_shader_variant *shader,
const struct radv_tessellation_state *tess)
}
static void
-radv_pipeline_generate_vertex_shader(struct radeon_winsys_cs *cs,
+radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf *cs,
struct radv_pipeline *pipeline,
const struct radv_tessellation_state *tess)
{
}
static void
-radv_pipeline_generate_tess_shaders(struct radeon_winsys_cs *cs,
+radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *cs,
struct radv_pipeline *pipeline,
const struct radv_tessellation_state *tess)
{
}
static void
-radv_pipeline_generate_geometry_shader(struct radeon_winsys_cs *cs,
+radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *cs,
struct radv_pipeline *pipeline,
const struct radv_gs_state *gs_state)
{
}
static void
-radv_pipeline_generate_ps_inputs(struct radeon_winsys_cs *cs,
+radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *cs,
struct radv_pipeline *pipeline)
{
struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
else
z_order = V_02880C_LATE_Z;
+ bool disable_rbplus = device->physical_device->has_rbplus &&
+ !device->physical_device->rbplus_allowed;
+
return S_02880C_Z_EXPORT_ENABLE(ps->info.info.ps.writes_z) |
S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.info.ps.writes_stencil) |
S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
S_02880C_EXEC_ON_HIER_FAIL(ps->info.info.ps.writes_memory) |
S_02880C_EXEC_ON_NOOP(ps->info.info.ps.writes_memory) |
- S_02880C_DUAL_QUAD_DISABLE(!!device->physical_device->has_rbplus);
+ S_02880C_DUAL_QUAD_DISABLE(disable_rbplus);
}
static void
-radv_pipeline_generate_fragment_shader(struct radeon_winsys_cs *cs,
+radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf *cs,
struct radv_pipeline *pipeline)
{
struct radv_shader_variant *ps;
}
static void
-radv_pipeline_generate_vgt_vertex_reuse(struct radeon_winsys_cs *cs,
+radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf *cs,
struct radv_pipeline *pipeline)
{
if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10)
unsigned vtx_reuse_depth = 30;
if (radv_pipeline_has_tess(pipeline) &&
- radv_get_tess_eval_shader(pipeline)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
+ radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
vtx_reuse_depth = 14;
}
radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
}
}
/* GS requirement. */
- if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
- ia_multi_vgt_param.partial_es_wave = true;
+ if (radv_pipeline_has_gs(pipeline) && device->physical_device->rad_info.chip_class <= VI)
+ if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
+ ia_multi_vgt_param.partial_es_wave = true;
ia_multi_vgt_param.wd_switch_on_eop = false;
if (device->physical_device->rad_info.chip_class >= CIK) {
if (radv_pipeline_has_tess(pipeline)) {
/* SWITCH_ON_EOI must be set if PrimID is used. */
if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.uses_prim_id ||
- radv_get_tess_eval_shader(pipeline)->info.info.uses_prim_id)
+ radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.info.uses_prim_id)
ia_multi_vgt_param.ia_switch_on_eoi = true;
}
device->physical_device->rad_info.family == CHIP_FIJI ||
device->physical_device->rad_info.family == CHIP_POLARIS10 ||
device->physical_device->rad_info.family == CHIP_POLARIS11 ||
- device->physical_device->rad_info.family == CHIP_POLARIS12)
+ device->physical_device->rad_info.family == CHIP_POLARIS12 ||
+ device->physical_device->rad_info.family == CHIP_VEGAM)
ia_multi_vgt_param.partial_vs_wave = true;
} else {
ia_multi_vgt_param.partial_vs_wave = true;
radv_create_shaders(pipeline, device, cache,
radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend, has_view_index),
- pStages);
+ pStages, pCreateInfo->flags);
pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
- radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
+ radv_pipeline_init_multisample_state(pipeline, &blend, pCreateInfo);
uint32_t gs_out;
uint32_t prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
if (loc->sgpr_idx != -1) {
pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
- if (radv_get_vertex_shader(pipeline)->info.info.vs.needs_draw_id)
+ if (radv_get_shader(pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id)
pipeline->graphics.vtx_emit_num = 3;
else
pipeline->graphics.vtx_emit_num = 2;
pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
if (pipeline == NULL)
- return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
+ return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
result = radv_pipeline_init(pipeline, device, cache,
pCreateInfo, extra, pAllocator);
pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
if (pipeline == NULL)
- return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
+ return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
pipeline->device = device;
pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
assert(pipeline->layout);
pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
- radv_create_shaders(pipeline, device, cache, (struct radv_pipeline_key) {0}, pStages);
+ radv_create_shaders(pipeline, device, cache, (struct radv_pipeline_key) {0}, pStages, pCreateInfo->flags);
pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
projects / mesa.git / blobdiff