radv: do not use an user SGPR for the sample position offset

[mesa.git] / src / amd / vulkan / radv_pipeline.c

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 54faddf5882a35411020ce35e7d951a9fcfaab36..1f01d2ff4d633ea815279fa13d313b6c2bdfede6 100644 (file)
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -2710,35 +2710,6 @@ radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *cs,
 
        radeon_set_context_reg(cs, R_028804_DB_EQAA, ms->db_eqaa);
        radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
-
-       if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
-               uint32_t offset;
-               struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
-               uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_FRAGMENT];
-               if (loc->sgpr_idx == -1)
-                       return;
-               assert(loc->num_sgprs == 1);
-               assert(!loc->indirect);
-               switch (pipeline->graphics.ms.num_samples) {
-               default:
-                       offset = 0;
-                       break;
-               case 2:
-                       offset = 1;
-                       break;
-               case 4:
-                       offset = 3;
-                       break;
-               case 8:
-                       offset = 7;
-                       break;
-               case 16:
-                       offset = 15;
-                       break;
-               }
-
-               radeon_set_sh_reg(cs, base_reg + loc->sgpr_idx * 4, offset);
-       }
 }
 
 static void