return false;
}
+/*
+ * Ordered so that for each i,
+ * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
+ */
+const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS] = {
+ VK_FORMAT_R32_SFLOAT,
+ VK_FORMAT_R32G32_SFLOAT,
+ VK_FORMAT_R8G8B8A8_UNORM,
+ VK_FORMAT_R16G16B16A16_UNORM,
+ VK_FORMAT_R16G16B16A16_SNORM,
+ VK_FORMAT_R16G16B16A16_UINT,
+ VK_FORMAT_R16G16B16A16_SINT,
+ VK_FORMAT_R32G32B32A32_SFLOAT,
+ VK_FORMAT_R8G8B8A8_UINT,
+ VK_FORMAT_R8G8B8A8_SINT,
+ VK_FORMAT_A2R10G10B10_UINT_PACK32,
+ VK_FORMAT_A2R10G10B10_SINT_PACK32,
+};
+
unsigned radv_format_meta_fs_key(VkFormat format)
{
- unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
+ unsigned col_format = si_choose_spi_color_format(format, false, false);
+
+ assert(col_format != V_028714_SPI_SHADER_32_AR);
+ if (col_format >= V_028714_SPI_SHADER_32_AR)
+ --col_format; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
+
+ --col_format; /* Skip V_028714_SPI_SHADER_ZERO */
bool is_int8 = format_is_int8(format);
bool is_int10 = format_is_int10(format);
ps_iter_samples = ms->num_samples;
}
+ const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
+ vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
+ if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
+ /* Out-of-order rasterization is explicitly enabled by the
+ * application.
+ */
+ out_of_order_rast = true;
+ } else {
+ /* Determine if the driver can enable out-of-order
+ * rasterization internally.
+ */
+ out_of_order_rast =
+ radv_pipeline_out_of_order_rast(pipeline, blend, pCreateInfo);
+ }
+
ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
ms->pa_sc_aa_config = 0;
ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
- S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
+ S_028804_INCOHERENT_EQAA_READS(1) |
+ S_028804_INTERPOLATE_COMP_Z(1) |
+ S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
ms->pa_sc_mode_cntl_1 =
S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
+ S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
+ S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
/* always 1: */
S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
}
- const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
- vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
- if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
- /* Out-of-order rasterization is explicitly enabled by the
- * application.
- */
- out_of_order_rast = true;
- } else {
- /* Determine if the driver can enable out-of-order
- * rasterization internally.
- */
- out_of_order_rast =
- radv_pipeline_out_of_order_rast(pipeline, blend, pCreateInfo);
- }
-
- if (out_of_order_rast) {
- ms->pa_sc_mode_cntl_1 |= S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(1) |
- S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7);
- }
-
if (vkms && vkms->pSampleMask) {
mask = vkms->pSampleMask[0] & 0xffff;
}
unsigned num_se = device->physical_device->rad_info.max_se;
unsigned wave_size = 64;
unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
- unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
+ /* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16.
+ * On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
+ */
+ unsigned gs_vertex_reuse =
+ (device->physical_device->rad_info.chip_class >= VI ? 32 : 16) * num_se;
unsigned alignment = 256 * num_se;
/* The maximum size is 63.999 MB per SE. */
unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
}
+ if (shader_count > 1) {
+ unsigned first = ordered_shaders[shader_count - 1]->info.stage;
+ unsigned last = ordered_shaders[0]->info.stage;
+
+ for (int i = 0; i < shader_count; ++i) {
+ nir_variable_mode mask = 0;
+
+ if (ordered_shaders[i]->info.stage != first)
+ mask = mask | nir_var_shader_in;
+
+ if (ordered_shaders[i]->info.stage != last)
+ mask = mask | nir_var_shader_out;
+
+ nir_lower_io_to_scalar_early(ordered_shaders[i], mask);
+ radv_optimize_nir(ordered_shaders[i], false, false);
+ }
+ }
+
for (int i = 1; i < shader_count; ++i) {
nir_lower_io_arrays_to_elements(ordered_shaders[i],
ordered_shaders[i - 1]);
ac_lower_indirect_derefs(ordered_shaders[i],
pipeline->device->physical_device->rad_info.chip_class);
}
- radv_optimize_nir(ordered_shaders[i], false);
+ radv_optimize_nir(ordered_shaders[i], false, false);
if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
ac_lower_indirect_derefs(ordered_shaders[i - 1],
pipeline->device->physical_device->rad_info.chip_class);
}
- radv_optimize_nir(ordered_shaders[i - 1], false);
+ radv_optimize_nir(ordered_shaders[i - 1], false, false);
}
}
}
void radv_create_shaders(struct radv_pipeline *pipeline,
struct radv_device *device,
struct radv_pipeline_cache *cache,
- struct radv_pipeline_key key,
+ const struct radv_pipeline_key *key,
const VkPipelineShaderStageCreateInfo **pStages,
const VkPipelineCreateFlags flags)
{
}
}
- radv_hash_shaders(hash, pStages, pipeline->layout, &key, get_hash_flags(device));
+ radv_hash_shaders(hash, pStages, pipeline->layout, key, get_hash_flags(device));
memcpy(gs_copy_hash, hash, 20);
gs_copy_hash[0] ^= 1;
modules[MESA_SHADER_FRAGMENT] = &fs_m;
}
- /* Determine first and last stage. */
- unsigned first = MESA_SHADER_STAGES;
- unsigned last = 0;
- for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
- if (!pStages[i])
- continue;
- if (first == MESA_SHADER_STAGES)
- first = i;
- last = i;
- }
-
for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
const VkPipelineShaderStageCreateInfo *stage = pStages[i];
if (nir[i]->info.name) {
nir[i] = nir_shader_clone(NULL, nir[i]);
}
-
- if (first != last) {
- nir_variable_mode mask = 0;
-
- if (i != first)
- mask = mask | nir_var_shader_in;
-
- if (i != last)
- mask = mask | nir_var_shader_out;
-
- if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)) {
- nir_lower_io_to_scalar_early(nir[i], mask);
- radv_optimize_nir(nir[i], false);
- }
- }
}
if (nir[MESA_SHADER_TESS_CTRL]) {
- nir_lower_tes_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out);
+ nir_lower_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out, NULL);
merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
}
nir_print_shader(nir[i], stderr);
}
- radv_fill_shader_keys(keys, &key, nir);
+ radv_fill_shader_keys(keys, key, nir);
if (nir[MESA_SHADER_FRAGMENT]) {
if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
free(codes[i]);
- if (modules[i]) {
+ if (nir[i]) {
if (!pipeline->device->keep_shader_info)
ralloc_free(nir[i]);
}
const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
- while(color_entry->bpp <= color_bytes_per_pixel)
+ while(color_entry[1].bpp <= color_bytes_per_pixel)
++color_entry;
extent = color_entry->extent;
unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
- while(ds_entry->bpp <= ds_bytes_per_pixel)
+ while(ds_entry[1].bpp <= ds_bytes_per_pixel)
++ds_entry;
extent.width = MIN2(extent.width, ds_entry->extent.width);
switch (pipeline->device->physical_device->rad_info.family) {
case CHIP_VEGA10:
case CHIP_VEGA12:
+ case CHIP_VEGA20:
context_states_per_bin = 1;
persistent_states_per_bin = 1;
fpovs_per_batch = 63;
pipeline->graphics.cb_target_mask = blend->cb_target_mask;
}
+static const VkConservativeRasterizationModeEXT
+radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo *pCreateInfo)
+{
+ const VkPipelineRasterizationConservativeStateCreateInfoEXT *conservative_raster =
+ vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT);
+
+ if (!conservative_raster)
+ return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT;
+ return conservative_raster->conservativeRasterizationMode;
+}
static void
radv_pipeline_generate_raster_state(struct radeon_cmdbuf *cs,
+ struct radv_pipeline *pipeline,
const VkGraphicsPipelineCreateInfo *pCreateInfo)
{
const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
+ const VkConservativeRasterizationModeEXT mode =
+ radv_get_conservative_raster_mode(vkraster);
+ uint32_t pa_sc_conservative_rast = 0;
radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
- S_028810_PS_UCP_MODE(3) |
S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0));
+
+ /* Conservative rasterization. */
+ if (mode != VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT) {
+ struct radv_multisample_state *ms = &pipeline->graphics.ms;
+
+ ms->pa_sc_aa_config |= S_028BE0_AA_MASK_CENTROID_DTMN(1);
+ ms->db_eqaa |= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
+ S_028804_OVERRASTERIZATION_AMOUNT(4);
+
+ pa_sc_conservative_rast = S_028C4C_PREZ_AA_MASK_ENABLE(1) |
+ S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
+ S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
+
+ if (mode == VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT) {
+ pa_sc_conservative_rast |=
+ S_028C4C_OVER_RAST_ENABLE(1) |
+ S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
+ S_028C4C_UNDER_RAST_ENABLE(0) |
+ S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
+ S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
+ } else {
+ assert(mode == VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT);
+ pa_sc_conservative_rast |=
+ S_028C4C_OVER_RAST_ENABLE(0) |
+ S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
+ S_028C4C_UNDER_RAST_ENABLE(1) |
+ S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
+ S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
+ }
+ }
+
+ radeon_set_context_reg(cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
+ pa_sc_conservative_rast);
}
ps_offset++;
}
+ if (ps->info.info.ps.num_input_clips_culls) {
+ unsigned vs_offset;
+
+ vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0];
+ if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
+ ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false);
+ ++ps_offset;
+ }
+
+ vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1];
+ if (vs_offset != AC_EXP_PARAM_UNDEFINED &&
+ ps->info.info.ps.num_input_clips_culls > 4) {
+ ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false);
+ ++ps_offset;
+ }
+ }
+
for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
unsigned vs_offset;
bool flat_shade;
radv_pipeline_generate_depth_stencil_state(&pipeline->cs, pipeline, pCreateInfo, extra);
radv_pipeline_generate_blend_state(&pipeline->cs, pipeline, blend);
- radv_pipeline_generate_raster_state(&pipeline->cs, pCreateInfo);
+ radv_pipeline_generate_raster_state(&pipeline->cs, pipeline, pCreateInfo);
radv_pipeline_generate_multisample_state(&pipeline->cs, pipeline);
radv_pipeline_generate_vgt_gs_mode(&pipeline->cs, pipeline);
radv_pipeline_generate_vertex_shader(&pipeline->cs, pipeline, tess);
}
}
+ /* Workaround for a VGT hang when strip primitive types are used with
+ * primitive restart.
+ */
+ if (pipeline->graphics.prim_restart_enable &&
+ (prim == V_008958_DI_PT_LINESTRIP ||
+ prim == V_008958_DI_PT_TRISTRIP ||
+ prim == V_008958_DI_PT_LINESTRIP_ADJ ||
+ prim == V_008958_DI_PT_TRISTRIP_ADJ)) {
+ ia_multi_vgt_param.partial_vs_wave = true;
+ }
+
ia_multi_vgt_param.base =
S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
/* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
pStages[stage] = &pCreateInfo->pStages[i];
}
- radv_create_shaders(pipeline, device, cache,
- radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend, has_view_index),
- pStages, pCreateInfo->flags);
+ struct radv_pipeline_key key = radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend, has_view_index);
+ radv_create_shaders(pipeline, device, cache, &key, pStages, pCreateInfo->flags);
pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
radv_pipeline_init_multisample_state(pipeline, &blend, pCreateInfo);
assert(pipeline->layout);
pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
- radv_create_shaders(pipeline, device, cache, (struct radv_pipeline_key) {0}, pStages, pCreateInfo->flags);
+ radv_create_shaders(pipeline, device, cache, &(struct radv_pipeline_key) {0}, pStages, pCreateInfo->flags);
pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
projects / mesa.git / blobdiff