radv/gfx10: compute the LDS size for exporting PrimID for VS

[mesa.git] / src / amd / vulkan / radv_pipeline.c

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 4e9e9e9c9cd1a5e18777ce5e1d4728957772e71b..3e448db1fd532351deafd25ddcd38651cb31799e 100644 (file)
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -865,7 +865,7 @@ radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
                blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
        }
 
-       if (pipeline->device->physical_device->has_rbplus) {
+       if (pipeline->device->physical_device->rad_info.has_rbplus) {
                /* Disable RB+ blend optimizations for dual source blending. */
                if (blend.mrt0_is_dual_src) {
                        for (i = 0; i < 8; i++) {
@@ -1751,6 +1751,15 @@ calculate_ngg_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
                if (es_info->info.so.num_outputs)
                        esvert_lds_size = 4 * es_info->info.so.num_outputs + 1;
                */
+
+               /* LDS size for passing data from GS to ES.
+                * GS stores Primitive IDs (one DWORD) into LDS at the address
+                * corresponding to the ES thread of the provoking vertex. All
+                * ES threads load and export PrimitiveID for their thread.
+                */
+               if (!radv_pipeline_has_tess(pipeline) &&
+                   pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.export_prim_id)
+                       esvert_lds_size = MAX2(esvert_lds_size, 1);
        }
 
        unsigned max_gsprims = max_gsprims_base;
@@ -2010,7 +2019,7 @@ calculate_tess_state(struct radv_pipeline *pipeline,
        else
                topology = V_028B6C_OUTPUT_TRIANGLE_CW;
 
-       if (pipeline->device->has_distributed_tess) {
+       if (pipeline->device->physical_device->rad_info.has_distributed_tess) {
                if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
                    pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
                        distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
@@ -2320,6 +2329,7 @@ radv_fill_shader_keys(struct radv_device *device,
        }
 
        if (device->physical_device->rad_info.chip_class >= GFX10 &&
+           device->physical_device->rad_info.family != CHIP_NAVI14 &&
            !(device->instance->debug_flags & RADV_DEBUG_NO_NGG)) {
                if (nir[MESA_SHADER_TESS_CTRL]) {
                        keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = true;
@@ -2339,6 +2349,26 @@ radv_fill_shader_keys(struct radv_device *device,
                        keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
                }
 
+               /*
+                * Disable NGG with geometry shaders. There are a bunch of
+                * issues still:
+                *   * GS primitives in pipeline statistic queries do not get
+                *     updates. See dEQP-VK.query_pool.statistics_query.geometry_shader_primitives
+                *   * dEQP-VK.clipping.user_defined.clip_cull_distance_dynamic_index.*geom* failures
+                *   * Interactions with tessellation failing:
+                *     dEQP-VK.tessellation.geometry_interaction.passthrough.tessellate_isolines_passthrough_geometry_no_change
+                *   * General issues with the last primitive missing/corrupt:
+                *     https://bugs.freedesktop.org/show_bug.cgi?id=111248
+                *
+                * Furthermore, XGL/AMDVLK also disables this as of 9b632ef.
+                */
+               if (nir[MESA_SHADER_GEOMETRY]) {
+                       if (nir[MESA_SHADER_TESS_CTRL])
+                               keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
+                       else
+                               keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
+               }
+
                /* TODO: Implement streamout support for NGG. */
                gl_shader_stage last_xfb_stage = MESA_SHADER_VERTEX;
 
@@ -3191,7 +3221,7 @@ radv_pipeline_generate_binning_state(struct radeon_cmdbuf *ctx_cs,
                        fpovs_per_batch = 63;
                } else {
                        /* The context states are affected by the scissor bug. */
-                       context_states_per_bin = pipeline->device->physical_device->has_scissor_bug ? 1 : 6;
+                       context_states_per_bin = pipeline->device->physical_device->rad_info.has_gfx9_scissor_bug ? 1 : 6;
                        /* 32 causes hangs for RAVEN. */
                        persistent_states_per_bin = 16;
                        fpovs_per_batch = 63;
@@ -3308,7 +3338,7 @@ radv_pipeline_generate_blend_state(struct radeon_cmdbuf *ctx_cs,
        radeon_set_context_reg(ctx_cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
        radeon_set_context_reg(ctx_cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
 
-       if (pipeline->device->physical_device->has_rbplus) {
+       if (pipeline->device->physical_device->rad_info.has_rbplus) {
 
                radeon_set_context_reg_seq(ctx_cs, R_028760_SX_MRT0_BLEND_OPT, 8);
                radeon_emit_array(ctx_cs, blend->sx_mrt_blend_opt, 8);
@@ -4033,8 +4063,8 @@ radv_compute_db_shader_control(const struct radv_device *device,
        else
                z_order = V_02880C_LATE_Z;
 
-       bool disable_rbplus = device->physical_device->has_rbplus &&
-                             !device->physical_device->rbplus_allowed;
+       bool disable_rbplus = device->physical_device->rad_info.has_rbplus &&
+                             !device->physical_device->rad_info.rbplus_allowed;
 
        /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
         * but this appears to break Project Cars (DXVK). See
@@ -4357,7 +4387,7 @@ radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
                    radv_pipeline_has_gs(pipeline))
                        ia_multi_vgt_param.partial_vs_wave = true;
                /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
-               if (device->has_distributed_tess) {
+               if (device->physical_device->rad_info.has_distributed_tess) {
                        if (radv_pipeline_has_gs(pipeline)) {
                                if (device->physical_device->rad_info.chip_class <= GFX8)
                                        ia_multi_vgt_param.partial_es_wave = true;