#include "nir/nir.h"
#include "nir/nir_builder.h"
#include "spirv/nir_spirv.h"
+#include "vk_util.h"
#include <llvm-c/Core.h>
#include <llvm-c/TargetMachine.h>
#include "sid.h"
#include "gfx9d.h"
-#include "r600d_common.h"
#include "ac_binary.h"
#include "ac_llvm_util.h"
#include "ac_nir_to_llvm.h"
static void radv_dump_pipeline_stats(struct radv_device *device, struct radv_pipeline *pipeline)
{
- unsigned lds_increment = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
- struct radv_shader_variant *var;
- struct ac_shader_config *conf;
int i;
- FILE *file = stderr;
- unsigned max_simd_waves;
- unsigned lds_per_wave = 0;
-
- switch (device->physical_device->rad_info.family) {
- /* These always have 8 waves: */
- case CHIP_POLARIS10:
- case CHIP_POLARIS11:
- case CHIP_POLARIS12:
- max_simd_waves = 8;
- break;
- default:
- max_simd_waves = 10;
- }
for (i = 0; i < MESA_SHADER_STAGES; i++) {
if (!pipeline->shaders[i])
continue;
- var = pipeline->shaders[i];
-
- conf = &var->config;
-
- if (i == MESA_SHADER_FRAGMENT) {
- lds_per_wave = conf->lds_size * lds_increment +
- align(var->info.fs.num_interp * 48, lds_increment);
- }
- if (conf->num_sgprs) {
- if (device->physical_device->rad_info.chip_class >= VI)
- max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
- else
- max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
- }
-
- if (conf->num_vgprs)
- max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
-
- /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
- * that PS can use.
- */
- if (lds_per_wave)
- max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
-
- fprintf(file, "\n%s:\n",
- radv_get_shader_name(var, i));
- if (i == MESA_SHADER_FRAGMENT) {
- fprintf(file, "*** SHADER CONFIG ***\n"
- "SPI_PS_INPUT_ADDR = 0x%04x\n"
- "SPI_PS_INPUT_ENA = 0x%04x\n",
- conf->spi_ps_input_addr, conf->spi_ps_input_ena);
- }
- fprintf(file, "*** SHADER STATS ***\n"
- "SGPRS: %d\n"
- "VGPRS: %d\n"
- "Spilled SGPRs: %d\n"
- "Spilled VGPRs: %d\n"
- "Code Size: %d bytes\n"
- "LDS: %d blocks\n"
- "Scratch: %d bytes per wave\n"
- "Max Waves: %d\n"
- "********************\n\n\n",
- conf->num_sgprs, conf->num_vgprs,
- conf->spilled_sgprs, conf->spilled_vgprs, var->code_size,
- conf->lds_size, conf->scratch_bytes_per_wave,
- max_simd_waves);
- }
-}
-
-static struct radv_shader_variant *
-radv_pipeline_compile(struct radv_pipeline *pipeline,
- struct radv_pipeline_cache *cache,
- struct radv_shader_module *module,
- const char *entrypoint,
- gl_shader_stage stage,
- const VkSpecializationInfo *spec_info,
- struct radv_pipeline_layout *layout,
- const struct ac_shader_variant_key *key)
-{
- unsigned char sha1[20];
- unsigned char gs_copy_sha1[20];
- struct radv_shader_variant *variant;
- nir_shader *nir;
- void *code = NULL;
- unsigned code_size = 0;
-
- if (module->nir)
- _mesa_sha1_compute(module->nir->info.name,
- strlen(module->nir->info.name),
- module->sha1);
-
- radv_hash_shader(sha1, module, entrypoint, spec_info, layout, key, 0);
- if (stage == MESA_SHADER_GEOMETRY)
- radv_hash_shader(gs_copy_sha1, module, entrypoint, spec_info,
- layout, key, 1);
-
- variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
- cache,
- sha1);
-
- if (stage == MESA_SHADER_GEOMETRY) {
- pipeline->gs_copy_shader =
- radv_create_shader_variant_from_pipeline_cache(
- pipeline->device,
- cache,
- gs_copy_sha1);
- }
-
- if (variant &&
- (stage != MESA_SHADER_GEOMETRY || pipeline->gs_copy_shader))
- return variant;
-
- nir = radv_shader_compile_to_nir(pipeline->device,
- module, entrypoint, stage,
- spec_info);
- if (nir == NULL)
- return NULL;
-
- if (!variant) {
- variant = radv_shader_variant_create(pipeline->device, nir,
- layout, key, &code,
- &code_size);
- }
-
- if (stage == MESA_SHADER_GEOMETRY && !pipeline->gs_copy_shader) {
- void *gs_copy_code = NULL;
- unsigned gs_copy_code_size = 0;
- pipeline->gs_copy_shader = radv_create_gs_copy_shader(
- pipeline->device, nir, &gs_copy_code,
- &gs_copy_code_size, key->has_multiview_view_index);
-
- if (pipeline->gs_copy_shader) {
- pipeline->gs_copy_shader =
- radv_pipeline_cache_insert_shader(cache,
- gs_copy_sha1,
- pipeline->gs_copy_shader,
- gs_copy_code,
- gs_copy_code_size);
- }
-
- free(gs_copy_code);
+ radv_shader_dump_stats(device, pipeline->shaders[i], i, stderr);
}
- if (!module->nir)
- ralloc_free(nir);
-
- if (variant)
- variant = radv_pipeline_cache_insert_shader(cache, sha1, variant,
- code, code_size);
-
- if (code)
- free(code);
- return variant;
}
-static struct ac_shader_variant_key
-radv_compute_tes_key(bool as_es, bool export_prim_id)
+static uint32_t get_hash_flags(struct radv_device *device)
{
- struct ac_shader_variant_key key;
- memset(&key, 0, sizeof(key));
- key.tes.as_es = as_es;
- /* export prim id only happens when no geom shader */
- if (!as_es)
- key.tes.export_prim_id = export_prim_id;
- return key;
-}
+ uint32_t hash_flags = 0;
-static struct ac_shader_variant_key
-radv_compute_tcs_key(unsigned primitive_mode, unsigned input_vertices)
-{
- struct ac_shader_variant_key key;
- memset(&key, 0, sizeof(key));
- key.tcs.primitive_mode = primitive_mode;
- key.tcs.input_vertices = input_vertices;
- return key;
-}
-
-static void
-radv_tess_pipeline_compile(struct radv_pipeline *pipeline,
- struct radv_pipeline_cache *cache,
- struct radv_shader_module *tcs_module,
- struct radv_shader_module *tes_module,
- const char *tcs_entrypoint,
- const char *tes_entrypoint,
- const VkSpecializationInfo *tcs_spec_info,
- const VkSpecializationInfo *tes_spec_info,
- struct radv_pipeline_layout *layout,
- unsigned input_vertices,
- bool has_view_index)
-{
- unsigned char tcs_sha1[20], tes_sha1[20];
- struct radv_shader_variant *tes_variant = NULL, *tcs_variant = NULL;
- nir_shader *tes_nir, *tcs_nir;
- void *tes_code = NULL, *tcs_code = NULL;
- unsigned tes_code_size = 0, tcs_code_size = 0;
- struct ac_shader_variant_key tes_key;
- struct ac_shader_variant_key tcs_key;
-
- tes_key = radv_compute_tes_key(radv_pipeline_has_gs(pipeline),
- pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input);
- tes_key.has_multiview_view_index = has_view_index;
- if (tes_module->nir)
- _mesa_sha1_compute(tes_module->nir->info.name,
- strlen(tes_module->nir->info.name),
- tes_module->sha1);
- radv_hash_shader(tes_sha1, tes_module, tes_entrypoint, tes_spec_info, layout, &tes_key, 0);
-
- tes_variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
- cache,
- tes_sha1);
-
- if (tes_variant) {
- tcs_key = radv_compute_tcs_key(tes_variant->info.tes.primitive_mode, input_vertices);
-
- if (tcs_module->nir)
- _mesa_sha1_compute(tcs_module->nir->info.name,
- strlen(tcs_module->nir->info.name),
- tcs_module->sha1);
-
- radv_hash_shader(tcs_sha1, tcs_module, tcs_entrypoint, tcs_spec_info, layout, &tcs_key, 0);
-
- tcs_variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
- cache,
- tcs_sha1);
- }
-
- if (tcs_variant && tes_variant) {
- pipeline->shaders[MESA_SHADER_TESS_CTRL] = tcs_variant;
- pipeline->shaders[MESA_SHADER_TESS_EVAL] = tes_variant;
- return;
- }
-
- tes_nir = radv_shader_compile_to_nir(pipeline->device,
- tes_module, tes_entrypoint, MESA_SHADER_TESS_EVAL,
- tes_spec_info);
- if (tes_nir == NULL)
- return;
-
- tcs_nir = radv_shader_compile_to_nir(pipeline->device,
- tcs_module, tcs_entrypoint, MESA_SHADER_TESS_CTRL,
- tcs_spec_info);
- if (tcs_nir == NULL)
- return;
-
- nir_lower_tes_patch_vertices(tes_nir,
- tcs_nir->info.tess.tcs_vertices_out);
-
- tes_variant = radv_shader_variant_create(pipeline->device, tes_nir,
- layout, &tes_key, &tes_code,
- &tes_code_size);
-
- tcs_key = radv_compute_tcs_key(tes_nir->info.tess.primitive_mode, input_vertices);
- if (tcs_module->nir)
- _mesa_sha1_compute(tcs_module->nir->info.name,
- strlen(tcs_module->nir->info.name),
- tcs_module->sha1);
-
- radv_hash_shader(tcs_sha1, tcs_module, tcs_entrypoint, tcs_spec_info, layout, &tcs_key, 0);
-
- tcs_variant = radv_shader_variant_create(pipeline->device, tcs_nir,
- layout, &tcs_key, &tcs_code,
- &tcs_code_size);
-
- if (!tes_module->nir)
- ralloc_free(tes_nir);
-
- if (!tcs_module->nir)
- ralloc_free(tcs_nir);
-
- if (tes_variant)
- tes_variant = radv_pipeline_cache_insert_shader(cache, tes_sha1, tes_variant,
- tes_code, tes_code_size);
-
- if (tcs_variant)
- tcs_variant = radv_pipeline_cache_insert_shader(cache, tcs_sha1, tcs_variant,
- tcs_code, tcs_code_size);
-
- if (tes_code)
- free(tes_code);
- if (tcs_code)
- free(tcs_code);
- pipeline->shaders[MESA_SHADER_TESS_CTRL] = tcs_variant;
- pipeline->shaders[MESA_SHADER_TESS_EVAL] = tes_variant;
- return;
+ if (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH)
+ hash_flags |= RADV_HASH_SHADER_UNSAFE_MATH;
+ if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
+ hash_flags |= RADV_HASH_SHADER_SISCHED;
+ return hash_flags;
}
static VkResult
const struct radv_graphics_pipeline_create_info *extra)
{
const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
+ const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
struct radv_blend_state *blend = &pipeline->graphics.blend;
unsigned mode = V_028808_CB_NORMAL;
uint32_t blend_enable = 0, blend_need_alpha = 0;
S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
S_028B70_ALPHA_TO_MASK_OFFSET3(2);
+ if (vkms && vkms->alphaToCoverageEnable) {
+ blend->db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
+ }
+
blend->cb_target_mask = 0;
for (i = 0; i < vkblend->attachmentCount; i++) {
const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
- memset(ds, 0, sizeof(*ds));
if (!vkds)
return;
const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
struct radv_raster_state *raster = &pipeline->graphics.raster;
- memset(raster, 0, sizeof(*raster));
-
raster->spi_interp_control =
S_0286D4_FLAT_SHADE_ENA(1) |
S_0286D4_PNT_SPRITE_ENA(1) |
const VkGraphicsPipelineCreateInfo *pCreateInfo)
{
const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
- struct radv_blend_state *blend = &pipeline->graphics.blend;
struct radv_multisample_state *ms = &pipeline->graphics.ms;
unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
int ps_iter_samples = 1;
S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
- EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
- EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
+ S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
+ S_028A4C_FORCE_EOV_REZ_ENABLE(1);
ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9);
if (ms->num_samples > 1) {
ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
- ms->pa_sc_mode_cntl_1 |= EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
+ ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
}
- if (vkms) {
- if (vkms->alphaToCoverageEnable)
- blend->db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
+ const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
+ vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
+ if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
+ ms->pa_sc_mode_cntl_1 |= S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(1) |
+ S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7);
+ }
- if (vkms->pSampleMask)
- mask = vkms->pSampleMask[0] & 0xffff;
+ if (vkms && vkms->pSampleMask) {
+ mask = vkms->pSampleMask[0] & 0xffff;
}
ms->pa_sc_aa_mask[0] = mask | (mask << 16);
}
static struct ac_shader_variant_key
-radv_compute_vs_key(const VkGraphicsPipelineCreateInfo *pCreateInfo, bool as_es, bool as_ls, bool export_prim_id)
+radv_compute_vs_key(const VkGraphicsPipelineCreateInfo *pCreateInfo, bool as_es, bool as_ls)
{
struct ac_shader_variant_key key;
const VkPipelineVertexInputStateCreateInfo *input_state =
key.vs.instance_rate_inputs = 0;
key.vs.as_es = as_es;
key.vs.as_ls = as_ls;
- key.vs.export_prim_id = export_prim_id;
for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
unsigned binding;
*lds_size = MAX2(*lds_size, 8);
}
+struct radv_shader_variant *
+radv_get_vertex_shader(struct radv_pipeline *pipeline)
+{
+ if (pipeline->shaders[MESA_SHADER_VERTEX])
+ return pipeline->shaders[MESA_SHADER_VERTEX];
+ if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
+ return pipeline->shaders[MESA_SHADER_TESS_CTRL];
+ return pipeline->shaders[MESA_SHADER_GEOMETRY];
+}
+
static void
calculate_tess_state(struct radv_pipeline *pipeline,
const VkGraphicsPipelineCreateInfo *pCreateInfo)
/* This calculates how shader inputs and outputs among VS, TCS, and TES
* are laid out in LDS. */
- num_tcs_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outputs_written);
+ num_tcs_inputs = util_last_bit64(radv_get_vertex_shader(pipeline)->info.vs.outputs_written);
num_tcs_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written); //tcs->outputs_written
num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
break;
}
+ bool ccw = tes->info.tes.ccw;
+ const VkPipelineTessellationDomainOriginStateCreateInfoKHR *domain_origin_state =
+ vk_find_struct_const(pCreateInfo->pTessellationState,
+ PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO_KHR);
+
+ if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT_KHR)
+ ccw = !ccw;
+
if (tes->info.tes.point_mode)
topology = V_028B6C_OUTPUT_POINT;
else if (tes->info.tes.primitive_mode == GL_ISOLINES)
topology = V_028B6C_OUTPUT_LINE;
- else if (tes->info.tes.ccw)
- topology = V_028B6C_OUTPUT_TRIANGLE_CW;
- else
+ else if (ccw)
topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
+ else
+ topology = V_028B6C_OUTPUT_TRIANGLE_CW;
if (pipeline->device->has_distributed_tess) {
if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
pipeline->graphics.ps_input_cntl_num = ps_offset;
}
-VkResult
+static void
+radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
+{
+ nir_shader* ordered_shaders[MESA_SHADER_STAGES];
+ int shader_count = 0;
+
+ if(shaders[MESA_SHADER_FRAGMENT]) {
+ ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
+ }
+ if(shaders[MESA_SHADER_GEOMETRY]) {
+ ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
+ }
+ if(shaders[MESA_SHADER_TESS_EVAL]) {
+ ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
+ }
+ if(shaders[MESA_SHADER_TESS_CTRL]) {
+ ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
+ }
+ if(shaders[MESA_SHADER_VERTEX]) {
+ ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
+ }
+
+ for (int i = 1; i < shader_count; ++i) {
+ nir_remove_dead_variables(ordered_shaders[i],
+ nir_var_shader_out);
+ nir_remove_dead_variables(ordered_shaders[i - 1],
+ nir_var_shader_in);
+
+ bool progress = nir_remove_unused_varyings(ordered_shaders[i],
+ ordered_shaders[i - 1]);
+
+ if (progress) {
+ nir_lower_global_vars_to_local(ordered_shaders[i]);
+ radv_optimize_nir(ordered_shaders[i]);
+ nir_lower_global_vars_to_local(ordered_shaders[i - 1]);
+ radv_optimize_nir(ordered_shaders[i - 1]);
+ }
+ }
+}
+
+static
+void radv_create_shaders(struct radv_pipeline *pipeline,
+ struct radv_device *device,
+ struct radv_pipeline_cache *cache,
+ struct ac_shader_variant_key *keys,
+ const VkPipelineShaderStageCreateInfo **pStages)
+{
+ struct radv_shader_module fs_m = {0};
+ struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
+ nir_shader *nir[MESA_SHADER_STAGES] = {0};
+ void *codes[MESA_SHADER_STAGES] = {0};
+ unsigned code_sizes[MESA_SHADER_STAGES] = {0};
+ unsigned char hash[20], gs_copy_hash[20];
+
+ for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
+ if (pStages[i]) {
+ modules[i] = radv_shader_module_from_handle(pStages[i]->module);
+ if (modules[i]->nir)
+ _mesa_sha1_compute(modules[i]->nir->info.name,
+ strlen(modules[i]->nir->info.name),
+ modules[i]->sha1);
+ }
+ }
+
+ radv_hash_shaders(hash, pStages, pipeline->layout, keys, get_hash_flags(device));
+ memcpy(gs_copy_hash, hash, 20);
+ gs_copy_hash[0] ^= 1;
+
+ if (modules[MESA_SHADER_GEOMETRY]) {
+ struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
+ radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants);
+ pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
+ }
+
+ if (radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders) &&
+ (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
+ for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
+ if (pipeline->shaders[i])
+ pipeline->active_stages |= mesa_to_vk_shader_stage(i);
+ }
+ return;
+ }
+
+ if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
+ nir_builder fs_b;
+ nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
+ fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
+ fs_m.nir = fs_b.shader;
+ modules[MESA_SHADER_FRAGMENT] = &fs_m;
+ }
+
+ for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
+ const VkPipelineShaderStageCreateInfo *stage = pStages[i];
+
+ if (!modules[i])
+ continue;
+
+ nir[i] = radv_shader_compile_to_nir(device, modules[i],
+ stage ? stage->pName : "main", i,
+ stage ? stage->pSpecializationInfo : NULL);
+ pipeline->active_stages |= mesa_to_vk_shader_stage(i);
+ }
+
+ if (nir[MESA_SHADER_TESS_CTRL]) {
+ /* TODO: This is no longer used as a key we should refactor this */
+ if (keys)
+ keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
+
+ nir_lower_tes_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out);
+ }
+
+ radv_link_shaders(pipeline, nir);
+
+ if (nir[MESA_SHADER_FRAGMENT]) {
+ pipeline->shaders[MESA_SHADER_FRAGMENT] =
+ radv_shader_variant_create(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
+ pipeline->layout, keys ? keys + MESA_SHADER_FRAGMENT : 0,
+ &codes[MESA_SHADER_FRAGMENT], &code_sizes[MESA_SHADER_FRAGMENT]);
+
+ /* TODO: These are no longer used as keys we should refactor this */
+ if (keys) {
+ keys[MESA_SHADER_VERTEX].vs.export_prim_id =
+ pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input;
+ keys[MESA_SHADER_TESS_EVAL].tes.export_prim_id =
+ pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input;
+ }
+
+ pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_FRAGMENT);
+ }
+
+ if (device->physical_device->rad_info.chip_class >= GFX9 &&
+ modules[MESA_SHADER_TESS_CTRL] && !pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
+ struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
+ struct ac_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
+ key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
+ pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_create(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
+ pipeline->layout,
+ &key, &codes[MESA_SHADER_TESS_CTRL],
+ &code_sizes[MESA_SHADER_TESS_CTRL]);
+ modules[MESA_SHADER_VERTEX] = NULL;
+ }
+
+ if (device->physical_device->rad_info.chip_class >= GFX9 &&
+ modules[MESA_SHADER_GEOMETRY] && !pipeline->shaders[MESA_SHADER_GEOMETRY]) {
+ gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
+ struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
+ pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_create(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
+ pipeline->layout,
+ &keys[pre_stage] , &codes[MESA_SHADER_GEOMETRY],
+ &code_sizes[MESA_SHADER_GEOMETRY]);
+ modules[pre_stage] = NULL;
+ }
+
+ for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
+ if(modules[i] && !pipeline->shaders[i]) {
+ pipeline->shaders[i] = radv_shader_variant_create(device, modules[i], &nir[i], 1,
+ pipeline->layout,
+ keys ? keys + i : 0, &codes[i],
+ &code_sizes[i]);
+ }
+ }
+
+ if(modules[MESA_SHADER_GEOMETRY]) {
+ void *gs_copy_code = NULL;
+ unsigned gs_copy_code_size = 0;
+ if (!pipeline->gs_copy_shader) {
+ pipeline->gs_copy_shader = radv_create_gs_copy_shader(
+ device, nir[MESA_SHADER_GEOMETRY], &gs_copy_code,
+ &gs_copy_code_size,
+ keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
+ }
+
+ if (pipeline->gs_copy_shader) {
+ void *code[MESA_SHADER_STAGES] = {0};
+ unsigned code_size[MESA_SHADER_STAGES] = {0};
+ struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
+
+ code[MESA_SHADER_GEOMETRY] = gs_copy_code;
+ code_size[MESA_SHADER_GEOMETRY] = gs_copy_code_size;
+ variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
+
+ radv_pipeline_cache_insert_shaders(device, cache,
+ gs_copy_hash,
+ variants,
+ (const void**)code,
+ code_size);
+ }
+ free(gs_copy_code);
+ }
+
+ radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
+ (const void**)codes, code_sizes);
+
+ for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
+ free(codes[i]);
+ if (modules[i] && !modules[i]->nir && !pipeline->device->trace_bo)
+ ralloc_free(nir[i]);
+ }
+
+ if (fs_m.nir)
+ ralloc_free(fs_m.nir);
+}
+
+static VkResult
radv_pipeline_init(struct radv_pipeline *pipeline,
struct radv_device *device,
struct radv_pipeline_cache *cache,
const struct radv_graphics_pipeline_create_info *extra,
const VkAllocationCallbacks *alloc)
{
- struct radv_shader_module fs_m = {0};
VkResult result;
bool has_view_index = false;
pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
+ radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
+
const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
- struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
pStages[stage] = &pCreateInfo->pStages[i];
- modules[stage] = radv_shader_module_from_handle(pStages[stage]->module);
}
- radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
+ struct ac_shader_variant_key keys[MESA_SHADER_STAGES];
+ memset(keys, 0, sizeof(keys));
- if (!modules[MESA_SHADER_FRAGMENT]) {
- nir_builder fs_b;
- nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
- fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
- fs_m.nir = fs_b.shader;
- modules[MESA_SHADER_FRAGMENT] = &fs_m;
- }
-
- if (modules[MESA_SHADER_FRAGMENT]) {
- struct ac_shader_variant_key key = {0};
- key.fs.col_format = pipeline->graphics.blend.spi_shader_col_format;
- if (pCreateInfo->pMultisampleState &&
- pCreateInfo->pMultisampleState->rasterizationSamples > 1)
- key.fs.multisample = true;
-
- if (pipeline->device->physical_device->rad_info.chip_class < VI)
- radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.fs.is_int8, &key.fs.is_int10);
-
- const VkPipelineShaderStageCreateInfo *stage = pStages[MESA_SHADER_FRAGMENT];
-
- pipeline->shaders[MESA_SHADER_FRAGMENT] =
- radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_FRAGMENT],
- stage ? stage->pName : "main",
- MESA_SHADER_FRAGMENT,
- stage ? stage->pSpecializationInfo : NULL,
- pipeline->layout, &key);
- pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_FRAGMENT);
- }
-
- if (fs_m.nir)
- ralloc_free(fs_m.nir);
-
- if (modules[MESA_SHADER_VERTEX]) {
+ if (pStages[MESA_SHADER_VERTEX]) {
bool as_es = false;
bool as_ls = false;
- bool export_prim_id = false;
- if (modules[MESA_SHADER_TESS_CTRL])
+ if (pStages[MESA_SHADER_TESS_CTRL])
as_ls = true;
- else if (modules[MESA_SHADER_GEOMETRY])
+ else if (pStages[MESA_SHADER_GEOMETRY])
as_es = true;
- else if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input)
- export_prim_id = true;
- struct ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, as_es, as_ls, export_prim_id);
- key.has_multiview_view_index = has_view_index;
- pipeline->shaders[MESA_SHADER_VERTEX] =
- radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_VERTEX],
- pStages[MESA_SHADER_VERTEX]->pName,
- MESA_SHADER_VERTEX,
- pStages[MESA_SHADER_VERTEX]->pSpecializationInfo,
- pipeline->layout, &key);
-
- pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_VERTEX);
+ keys[MESA_SHADER_VERTEX] = radv_compute_vs_key(pCreateInfo, as_es, as_ls);
+ keys[MESA_SHADER_VERTEX].has_multiview_view_index = has_view_index;
}
- if (modules[MESA_SHADER_GEOMETRY]) {
- struct ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, false, false, false);
- key.has_multiview_view_index = has_view_index;
+ if (pStages[MESA_SHADER_TESS_EVAL]) {
+ keys[MESA_SHADER_TESS_EVAL].has_multiview_view_index = has_view_index;
+ if (pStages[MESA_SHADER_GEOMETRY])
+ keys[MESA_SHADER_TESS_EVAL].tes.as_es = true;
+ }
- pipeline->shaders[MESA_SHADER_GEOMETRY] =
- radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_GEOMETRY],
- pStages[MESA_SHADER_GEOMETRY]->pName,
- MESA_SHADER_GEOMETRY,
- pStages[MESA_SHADER_GEOMETRY]->pSpecializationInfo,
- pipeline->layout, &key);
+ if (pCreateInfo->pTessellationState)
+ keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = pCreateInfo->pTessellationState->patchControlPoints;
- pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_GEOMETRY);
+ if (pStages[MESA_SHADER_GEOMETRY]) {
+ keys[MESA_SHADER_GEOMETRY] = radv_compute_vs_key(pCreateInfo, false, false);
+ keys[MESA_SHADER_GEOMETRY].has_multiview_view_index = has_view_index;
}
- if (modules[MESA_SHADER_TESS_EVAL]) {
- assert(modules[MESA_SHADER_TESS_CTRL]);
+ if (pCreateInfo->pMultisampleState &&
+ pCreateInfo->pMultisampleState->rasterizationSamples > 1)
+ keys[MESA_SHADER_FRAGMENT].fs.multisample = true;
- radv_tess_pipeline_compile(pipeline,
- cache,
- modules[MESA_SHADER_TESS_CTRL],
- modules[MESA_SHADER_TESS_EVAL],
- pStages[MESA_SHADER_TESS_CTRL]->pName,
- pStages[MESA_SHADER_TESS_EVAL]->pName,
- pStages[MESA_SHADER_TESS_CTRL]->pSpecializationInfo,
- pStages[MESA_SHADER_TESS_EVAL]->pSpecializationInfo,
- pipeline->layout,
- pCreateInfo->pTessellationState->patchControlPoints,
- has_view_index);
- pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_TESS_EVAL) |
- mesa_to_vk_shader_stage(MESA_SHADER_TESS_CTRL);
- }
+ keys[MESA_SHADER_FRAGMENT].fs.col_format = pipeline->graphics.blend.spi_shader_col_format;
+ if (pipeline->device->physical_device->rad_info.chip_class < VI)
+ radv_pipeline_compute_get_int_clamp(pCreateInfo, &keys[MESA_SHADER_FRAGMENT].fs.is_int8, &keys[MESA_SHADER_FRAGMENT].fs.is_int10);
+
+ radv_create_shaders(pipeline, device, cache, keys, pStages);
radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo, extra);
radv_pipeline_init_raster_state(pipeline, pCreateInfo);
!ps->info.fs.writes_sample_mask)
pipeline->graphics.blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
}
-
+
unsigned z_order;
pipeline->graphics.db_shader_control = 0;
if (ps->info.fs.early_fragment_test || !ps->info.fs.writes_memory)
}
}
+ pipeline->graphics.base_ia_multi_vgt_param =
+ S_028AA8_PRIMGROUP_SIZE(pipeline->graphics.primgroup_size - 1) |
+ /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
+ S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == VI ? 2 : 0) |
+ S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
+ S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
+
const VkPipelineVertexInputStateCreateInfo *vi_info =
pCreateInfo->pVertexInputState;
struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
AC_UD_VS_BASE_VERTEX_START_INSTANCE);
if (loc->sgpr_idx != -1) {
- pipeline->graphics.vtx_base_sgpr = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
+ pipeline->graphics.vtx_base_sgpr = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
- if (pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
+ if (radv_get_vertex_shader(pipeline)->info.info.vs.needs_draw_id)
pipeline->graphics.vtx_emit_num = 3;
else
pipeline->graphics.vtx_emit_num = 2;
}
- if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
+
+ pipeline->graphics.vtx_reuse_depth = 30;
+ if (radv_pipeline_has_tess(pipeline) &&
+ pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
+ pipeline->graphics.vtx_reuse_depth = 14;
+ }
+
+ if (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
radv_dump_pipeline_stats(device, pipeline);
}
{
RADV_FROM_HANDLE(radv_device, device, _device);
RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
- RADV_FROM_HANDLE(radv_shader_module, module, pCreateInfo->stage.module);
+ const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
struct radv_pipeline *pipeline;
VkResult result;
pipeline->device = device;
pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
- pipeline->shaders[MESA_SHADER_COMPUTE] =
- radv_pipeline_compile(pipeline, cache, module,
- pCreateInfo->stage.pName,
- MESA_SHADER_COMPUTE,
- pCreateInfo->stage.pSpecializationInfo,
- pipeline->layout, NULL);
+ pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
+ radv_create_shaders(pipeline, device, cache, NULL, pStages);
pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
*pPipeline = radv_pipeline_to_handle(pipeline);
- if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
+ if (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
radv_dump_pipeline_stats(device, pipeline);
}
return VK_SUCCESS;
projects / mesa.git / blobdiff