uint32_t tf_param;
};
-struct radv_gs_state {
- uint32_t vgt_gs_onchip_cntl;
- uint32_t vgt_gs_max_prims_per_subgroup;
- uint32_t vgt_esgs_ring_itemsize;
- uint32_t lds_size;
-};
-
-struct radv_ngg_state {
- uint16_t ngg_emit_size; /* in dwords */
- uint32_t hw_max_esverts;
- uint32_t max_gsprims;
- uint32_t max_out_verts;
- uint32_t prim_amp_factor;
- uint32_t vgt_esgs_ring_itemsize;
- bool max_vert_out_per_gs_instance;
-};
-
bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline)
{
struct radv_shader_variant *variant = NULL;
pipeline->dynamic_state.mask = states;
}
-static struct radv_gs_state
-calculate_gs_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
- const struct radv_pipeline *pipeline)
+static void
+gfx9_get_gs_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
+ const struct radv_pipeline *pipeline,
+ nir_shader **nir,
+ struct radv_shader_info *infos,
+ struct gfx9_gs_info *out)
{
- struct radv_gs_state gs = {0};
- struct radv_shader_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
+ struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
struct radv_es_output_info *es_info;
if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
- es_info = radv_pipeline_has_tess(pipeline) ? &gs_info->tes.es_info : &gs_info->vs.es_info;
+ es_info = nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
else
- es_info = radv_pipeline_has_tess(pipeline) ?
- &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
- &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
+ es_info = nir[MESA_SHADER_TESS_CTRL] ?
+ &infos[MESA_SHADER_TESS_EVAL].tes.es_info :
+ &infos[MESA_SHADER_VERTEX].vs.es_info;
unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
bool uses_adjacency;
uint32_t gs_prims_per_subgroup = gs_prims;
uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
- gs.lds_size = align(esgs_lds_size, 128) / 128;
- gs.vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
+ out->lds_size = align(esgs_lds_size, 128) / 128;
+ out->vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
- gs.vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
- gs.vgt_esgs_ring_itemsize = esgs_itemsize;
+ out->vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
+ out->vgt_esgs_ring_itemsize = esgs_itemsize;
assert(max_prims_per_subgroup <= max_out_prims);
-
- return gs;
}
static void clamp_gsprims_to_esverts(unsigned *max_gsprims, unsigned max_esverts,
}
static unsigned
-radv_get_num_input_vertices(struct radv_pipeline *pipeline)
+radv_get_num_input_vertices(nir_shader **nir)
{
- if (radv_pipeline_has_gs(pipeline)) {
- struct radv_shader_variant *gs =
- radv_get_shader(pipeline, MESA_SHADER_GEOMETRY);
+ if (nir[MESA_SHADER_GEOMETRY]) {
+ nir_shader *gs = nir[MESA_SHADER_GEOMETRY];
return gs->info.gs.vertices_in;
}
- if (radv_pipeline_has_tess(pipeline)) {
- struct radv_shader_variant *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL);
+ if (nir[MESA_SHADER_TESS_CTRL]) {
+ nir_shader *tes = nir[MESA_SHADER_TESS_EVAL];
- if (tes->info.tes.point_mode)
+ if (tes->info.tess.point_mode)
return 1;
- if (tes->info.tes.primitive_mode == GL_ISOLINES)
+ if (tes->info.tess.primitive_mode == GL_ISOLINES)
return 2;
return 3;
}
return 3;
}
-static struct radv_ngg_state
-calculate_ngg_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
- struct radv_pipeline *pipeline)
+static void
+gfx10_get_ngg_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
+ struct radv_pipeline *pipeline,
+ nir_shader **nir,
+ struct radv_shader_info *infos,
+ struct gfx10_ngg_info *ngg)
{
- struct radv_ngg_state ngg = {0};
- struct radv_shader_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
+ struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
struct radv_es_output_info *es_info =
- radv_pipeline_has_tess(pipeline) ? &gs_info->tes.es_info : &gs_info->vs.es_info;
- unsigned gs_type = radv_pipeline_has_gs(pipeline) ? MESA_SHADER_GEOMETRY : MESA_SHADER_VERTEX;
- unsigned max_verts_per_prim = radv_get_num_input_vertices(pipeline);
+ nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
+ unsigned gs_type = nir[MESA_SHADER_GEOMETRY] ? MESA_SHADER_GEOMETRY : MESA_SHADER_VERTEX;
+ unsigned max_verts_per_prim = radv_get_num_input_vertices(nir);
unsigned min_verts_per_prim =
gs_type == MESA_SHADER_GEOMETRY ? max_verts_per_prim : 1;
- unsigned gs_num_invocations = radv_pipeline_has_gs(pipeline) ? MAX2(gs_info->gs.invocations, 1) : 1;
+ unsigned gs_num_invocations = nir[MESA_SHADER_GEOMETRY] ? MAX2(gs_info->gs.invocations, 1) : 1;
bool uses_adjacency;
switch(pCreateInfo->pInputAssemblyState->topology) {
case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
* corresponding to the ES thread of the provoking vertex. All
* ES threads load and export PrimitiveID for their thread.
*/
- if (!radv_pipeline_has_tess(pipeline) &&
- pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.export_prim_id)
+ if (!nir[MESA_SHADER_TESS_CTRL] &&
+ infos[MESA_SHADER_VERTEX].vs.outinfo.export_prim_id)
esvert_lds_size = MAX2(esvert_lds_size, 1);
}
* this check passes, there is enough space for a full primitive without
* vertex reuse.
*/
- ngg.hw_max_esverts = max_esverts - max_verts_per_prim + 1;
- ngg.max_gsprims = max_gsprims;
- ngg.max_out_verts = max_out_vertices;
- ngg.prim_amp_factor = prim_amp_factor;
- ngg.max_vert_out_per_gs_instance = max_vert_out_per_gs_instance;
- ngg.ngg_emit_size = max_gsprims * gsprim_lds_size;
+ ngg->hw_max_esverts = max_esverts - max_verts_per_prim + 1;
+ ngg->max_gsprims = max_gsprims;
+ ngg->max_out_verts = max_out_vertices;
+ ngg->prim_amp_factor = prim_amp_factor;
+ ngg->max_vert_out_per_gs_instance = max_vert_out_per_gs_instance;
+ ngg->ngg_emit_size = max_gsprims * gsprim_lds_size;
+ ngg->esgs_ring_size = 4 * max_esverts * esvert_lds_size;
if (gs_type == MESA_SHADER_GEOMETRY) {
- ngg.vgt_esgs_ring_itemsize = es_info->esgs_itemsize / 4;
+ ngg->vgt_esgs_ring_itemsize = es_info->esgs_itemsize / 4;
} else {
- ngg.vgt_esgs_ring_itemsize = 1;
+ ngg->vgt_esgs_ring_itemsize = 1;
}
- pipeline->graphics.esgs_ring_size = 4 * max_esverts * esvert_lds_size;
-
- assert(ngg.hw_max_esverts >= 24); /* HW limitation */
+ pipeline->graphics.esgs_ring_size = ngg->esgs_ring_size;
- return ngg;
+ assert(ngg->hw_max_esverts >= 24); /* HW limitation */
}
static void
-calculate_gs_ring_sizes(struct radv_pipeline *pipeline, const struct radv_gs_state *gs)
+calculate_gs_ring_sizes(struct radv_pipeline *pipeline,
+ const struct gfx9_gs_info *gs)
{
struct radv_device *device = pipeline->device;
unsigned num_se = device->physical_device->rad_info.max_se;
* issues still:
* * GS primitives in pipeline statistic queries do not get
* updates. See dEQP-VK.query_pool.statistics_query.geometry_shader_primitives
- * * dEQP-VK.clipping.user_defined.clip_cull_distance_dynamic_index.*geom* failures
- * * Interactions with tessellation failing:
- * dEQP-VK.tessellation.geometry_interaction.passthrough.tessellate_isolines_passthrough_geometry_no_change
* * General issues with the last primitive missing/corrupt:
* https://bugs.freedesktop.org/show_bug.cgi?id=111248
*
keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
}
- /* TODO: Implement streamout support for NGG. */
- gl_shader_stage last_xfb_stage = MESA_SHADER_VERTEX;
+ if (!device->physical_device->use_ngg_streamout) {
+ gl_shader_stage last_xfb_stage = MESA_SHADER_VERTEX;
- for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
- if (nir[i])
- last_xfb_stage = i;
- }
+ for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
+ if (nir[i])
+ last_xfb_stage = i;
+ }
- if (nir[last_xfb_stage] &&
- radv_nir_stage_uses_xfb(nir[last_xfb_stage])) {
- if (nir[MESA_SHADER_TESS_CTRL])
- keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
- else
- keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
+ if (nir[last_xfb_stage] &&
+ radv_nir_stage_uses_xfb(nir[last_xfb_stage])) {
+ if (nir[MESA_SHADER_TESS_CTRL])
+ keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
+ else
+ keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
+ }
}
}
keys[MESA_SHADER_FRAGMENT].fs.num_samples = key->num_samples;
}
+static void
+radv_fill_shader_info(struct radv_pipeline *pipeline,
+ struct radv_shader_variant_key *keys,
+ struct radv_shader_info *infos,
+ nir_shader **nir)
+{
+ unsigned active_stages = 0;
+ unsigned filled_stages = 0;
+
+ for (int i = 0; i < MESA_SHADER_STAGES; i++) {
+ if (nir[i])
+ active_stages |= (1 << i);
+ }
+
+ if (nir[MESA_SHADER_FRAGMENT]) {
+ radv_nir_shader_info_init(&infos[MESA_SHADER_FRAGMENT]);
+ radv_nir_shader_info_pass(nir[MESA_SHADER_FRAGMENT],
+ pipeline->layout,
+ &keys[MESA_SHADER_FRAGMENT],
+ &infos[MESA_SHADER_FRAGMENT]);
+
+ /* TODO: These are no longer used as keys we should refactor this */
+ keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id =
+ infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
+ keys[MESA_SHADER_VERTEX].vs_common_out.export_layer_id =
+ infos[MESA_SHADER_FRAGMENT].ps.layer_input;
+ keys[MESA_SHADER_VERTEX].vs_common_out.export_clip_dists =
+ !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
+ keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_prim_id =
+ infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
+ keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_layer_id =
+ infos[MESA_SHADER_FRAGMENT].ps.layer_input;
+ keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_clip_dists =
+ !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
+
+ filled_stages |= (1 << MESA_SHADER_FRAGMENT);
+ }
+
+ if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
+ nir[MESA_SHADER_TESS_CTRL]) {
+ struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
+ struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
+ key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
+
+ radv_nir_shader_info_init(&infos[MESA_SHADER_TESS_CTRL]);
+
+ for (int i = 0; i < 2; i++) {
+ radv_nir_shader_info_pass(combined_nir[i],
+ pipeline->layout, &key,
+ &infos[MESA_SHADER_TESS_CTRL]);
+ }
+
+ keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
+ infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
+ keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
+ util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
+
+ filled_stages |= (1 << MESA_SHADER_VERTEX);
+ filled_stages |= (1 << MESA_SHADER_TESS_CTRL);
+ }
+
+ if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
+ nir[MESA_SHADER_GEOMETRY]) {
+ gl_shader_stage pre_stage = nir[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
+ struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
+
+ radv_nir_shader_info_init(&infos[MESA_SHADER_GEOMETRY]);
+
+ for (int i = 0; i < 2; i++) {
+ radv_nir_shader_info_pass(combined_nir[i],
+ pipeline->layout,
+ &keys[pre_stage],
+ &infos[MESA_SHADER_GEOMETRY]);
+ }
+
+ filled_stages |= (1 << pre_stage);
+ filled_stages |= (1 << MESA_SHADER_GEOMETRY);
+ }
+
+ active_stages ^= filled_stages;
+ while (active_stages) {
+ int i = u_bit_scan(&active_stages);
+
+ if (i == MESA_SHADER_TESS_CTRL) {
+ keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs =
+ util_last_bit64(infos[MESA_SHADER_VERTEX].vs.ls_outputs_written);
+ }
+
+ if (i == MESA_SHADER_TESS_EVAL) {
+ keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
+ infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
+ keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
+ util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
+ }
+
+ radv_nir_shader_info_init(&infos[i]);
+ radv_nir_shader_info_pass(nir[i], pipeline->layout,
+ &keys[i], &infos[i]);
+ }
+}
+
static void
merge_tess_info(struct shader_info *tes_info,
const struct shader_info *tcs_info)
const struct radv_pipeline_key *key,
const VkPipelineShaderStageCreateInfo **pStages,
const VkPipelineCreateFlags flags,
+ const VkGraphicsPipelineCreateInfo *pCreateInfo,
VkPipelineCreationFeedbackEXT *pipeline_feedback,
VkPipelineCreationFeedbackEXT **stage_feedbacks)
{
nir_shader *nir[MESA_SHADER_STAGES] = {0};
struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{{0}}}}};
+ struct radv_shader_info infos[MESA_SHADER_STAGES] = {0};
unsigned char hash[20], gs_copy_hash[20];
bool keep_executable_info = (flags & VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR) || device->keep_shader_info;
radv_fill_shader_keys(device, keys, key, nir);
+ radv_fill_shader_info(pipeline, keys, infos, nir);
+
+ if ((nir[MESA_SHADER_VERTEX] &&
+ keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg) ||
+ (nir[MESA_SHADER_TESS_EVAL] &&
+ keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg)) {
+ struct gfx10_ngg_info *ngg_info;
+
+ if (nir[MESA_SHADER_GEOMETRY])
+ ngg_info = &infos[MESA_SHADER_GEOMETRY].ngg_info;
+ else if (nir[MESA_SHADER_TESS_CTRL])
+ ngg_info = &infos[MESA_SHADER_TESS_EVAL].ngg_info;
+ else
+ ngg_info = &infos[MESA_SHADER_VERTEX].ngg_info;
+
+ gfx10_get_ngg_info(pCreateInfo, pipeline, nir, infos, ngg_info);
+ } else if (nir[MESA_SHADER_GEOMETRY]) {
+ struct gfx9_gs_info *gs_info =
+ &infos[MESA_SHADER_GEOMETRY].gs_ring_info;
+
+ gfx9_get_gs_info(pCreateInfo, pipeline, nir, infos, gs_info);
+ }
+
if (nir[MESA_SHADER_FRAGMENT]) {
if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
radv_start_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT]);
pipeline->shaders[MESA_SHADER_FRAGMENT] =
radv_shader_variant_compile(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
pipeline->layout, keys + MESA_SHADER_FRAGMENT,
+ infos + MESA_SHADER_FRAGMENT,
keep_executable_info, &binaries[MESA_SHADER_FRAGMENT]);
radv_stop_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT], false);
pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_compile(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
pipeline->layout,
- &key, keep_executable_info,
+ &key, &infos[MESA_SHADER_TESS_CTRL], keep_executable_info,
&binaries[MESA_SHADER_TESS_CTRL]);
radv_stop_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL], false);
pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_compile(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
pipeline->layout,
- &keys[pre_stage], keep_executable_info,
+ &keys[pre_stage], &infos[MESA_SHADER_GEOMETRY], keep_executable_info,
&binaries[MESA_SHADER_GEOMETRY]);
radv_stop_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY], false);
pipeline->shaders[i] = radv_shader_variant_compile(device, modules[i], &nir[i], 1,
pipeline->layout,
- keys + i, keep_executable_info,
+ keys + i, infos + i,keep_executable_info,
&binaries[i]);
radv_stop_feedback(stage_feedbacks[i], false);
struct radv_shader_binary *gs_copy_binary = NULL;
if (!pipeline->gs_copy_shader &&
!radv_pipeline_has_ngg(pipeline)) {
+ struct radv_shader_info info = {};
+ struct radv_shader_variant_key key = {};
+
+ key.has_multiview_view_index =
+ keys[MESA_SHADER_GEOMETRY].has_multiview_view_index;
+
+ radv_nir_shader_info_pass(nir[MESA_SHADER_GEOMETRY],
+ pipeline->layout, &key,
+ &info);
+
pipeline->gs_copy_shader = radv_create_gs_copy_shader(
- device, nir[MESA_SHADER_GEOMETRY], &gs_copy_binary,
- keep_executable_info,
+ device, nir[MESA_SHADER_GEOMETRY], &info,
+ &gs_copy_binary, keep_executable_info,
keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
}
radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
struct radeon_cmdbuf *cs,
struct radv_pipeline *pipeline,
- struct radv_shader_variant *shader,
- const struct radv_ngg_state *ngg_state)
+ struct radv_shader_variant *shader)
{
uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
gl_shader_stage es_type =
radv_pipeline_has_tess(pipeline) ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
struct radv_shader_variant *es =
es_type == MESA_SHADER_TESS_EVAL ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX];
+ const struct gfx10_ngg_info *ngg_state = &shader->info.ngg_info;
radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
radeon_emit(cs, va >> 8);
radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf *ctx_cs,
struct radeon_cmdbuf *cs,
struct radv_pipeline *pipeline,
- const struct radv_tessellation_state *tess,
- const struct radv_ngg_state *ngg)
+ const struct radv_tessellation_state *tess)
{
struct radv_shader_variant *vs;
else if (vs->info.vs.as_es)
radv_pipeline_generate_hw_es(cs, pipeline, vs);
else if (vs->info.is_ngg)
- radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, vs, ngg);
+ radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, vs);
else
radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, vs);
}
radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *ctx_cs,
struct radeon_cmdbuf *cs,
struct radv_pipeline *pipeline,
- const struct radv_tessellation_state *tess,
- const struct radv_ngg_state *ngg)
+ const struct radv_tessellation_state *tess)
{
if (!radv_pipeline_has_tess(pipeline))
return;
if (tes) {
if (tes->info.is_ngg) {
- radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, tes, ngg);
+ radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, tes);
} else if (tes->info.tes.as_es)
radv_pipeline_generate_hw_es(cs, pipeline, tes);
else
radv_pipeline_generate_hw_gs(struct radeon_cmdbuf *ctx_cs,
struct radeon_cmdbuf *cs,
struct radv_pipeline *pipeline,
- struct radv_shader_variant *gs,
- const struct radv_gs_state *gs_state)
+ struct radv_shader_variant *gs)
{
+ const struct gfx9_gs_info *gs_state = &gs->info.gs_ring_info;
unsigned gs_max_out_vertices;
uint8_t *num_components;
uint8_t max_stream;
static void
radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *ctx_cs,
struct radeon_cmdbuf *cs,
- struct radv_pipeline *pipeline,
- const struct radv_gs_state *gs_state,
- const struct radv_ngg_state *ngg_state)
+ struct radv_pipeline *pipeline)
{
struct radv_shader_variant *gs;
return;
if (gs->info.is_ngg)
- radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, gs, ngg_state);
+ radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, gs);
else
- radv_pipeline_generate_hw_gs(ctx_cs, cs, pipeline, gs, gs_state);
+ radv_pipeline_generate_hw_gs(ctx_cs, cs, pipeline, gs);
radeon_set_context_reg(ctx_cs, R_028B38_VGT_GS_MAX_VERT_OUT,
gs->info.gs.vertices_out);
static void
gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf *ctx_cs,
struct radv_pipeline *pipeline,
- const struct radv_tessellation_state *tess,
- const struct radv_gs_state *gs_state)
+ const struct radv_tessellation_state *tess)
{
bool break_wave_at_eoi = false;
unsigned primgroup_size;
primgroup_size = tess->num_patches; /* must be a multiple of NUM_PATCHES */
vertgroup_size = 0;
} else if (radv_pipeline_has_gs(pipeline)) {
+ const struct gfx9_gs_info *gs_state =
+ &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs_ring_info;
unsigned vgt_gs_onchip_cntl = gs_state->vgt_gs_onchip_cntl;
primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl);
vertgroup_size = G_028A44_ES_VERTS_PER_SUBGRP(vgt_gs_onchip_cntl);
const struct radv_graphics_pipeline_create_info *extra,
const struct radv_blend_state *blend,
const struct radv_tessellation_state *tess,
- const struct radv_gs_state *gs,
- const struct radv_ngg_state *ngg,
unsigned prim, unsigned gs_out)
{
struct radeon_cmdbuf *ctx_cs = &pipeline->ctx_cs;
radv_pipeline_generate_raster_state(ctx_cs, pipeline, pCreateInfo);
radv_pipeline_generate_multisample_state(ctx_cs, pipeline);
radv_pipeline_generate_vgt_gs_mode(ctx_cs, pipeline);
- radv_pipeline_generate_vertex_shader(ctx_cs, cs, pipeline, tess, ngg);
- radv_pipeline_generate_tess_shaders(ctx_cs, cs, pipeline, tess, ngg);
- radv_pipeline_generate_geometry_shader(ctx_cs, cs, pipeline, gs, ngg);
+ radv_pipeline_generate_vertex_shader(ctx_cs, cs, pipeline, tess);
+ radv_pipeline_generate_tess_shaders(ctx_cs, cs, pipeline, tess);
+ radv_pipeline_generate_geometry_shader(ctx_cs, cs, pipeline);
radv_pipeline_generate_fragment_shader(ctx_cs, cs, pipeline);
radv_pipeline_generate_ps_inputs(ctx_cs, pipeline);
radv_pipeline_generate_vgt_vertex_reuse(ctx_cs, pipeline);
radv_pipeline_generate_binning_state(ctx_cs, pipeline, pCreateInfo);
if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 && !radv_pipeline_has_ngg(pipeline))
- gfx10_pipeline_generate_ge_cntl(ctx_cs, pipeline, tess, gs);
+ gfx10_pipeline_generate_ge_cntl(ctx_cs, pipeline, tess);
radeon_set_context_reg(ctx_cs, R_0286E8_SPI_TMPRING_SIZE,
S_0286E8_WAVES(pipeline->max_waves) |
}
struct radv_pipeline_key key = radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend, has_view_index);
- radv_create_shaders(pipeline, device, cache, &key, pStages, pCreateInfo->flags, pipeline_feedback, stage_feedbacks);
+ radv_create_shaders(pipeline, device, cache, &key, pStages, pCreateInfo->flags, pCreateInfo, pipeline_feedback, stage_feedbacks);
pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
radv_pipeline_init_multisample_state(pipeline, &blend, pCreateInfo);
}
}
- struct radv_ngg_state ngg = {0};
- struct radv_gs_state gs = {0};
+ if (radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
+ struct radv_shader_variant *gs =
+ pipeline->shaders[MESA_SHADER_GEOMETRY];
- if (radv_pipeline_has_ngg(pipeline)) {
- ngg = calculate_ngg_info(pCreateInfo, pipeline);
- } else if (radv_pipeline_has_gs(pipeline)) {
- gs = calculate_gs_info(pCreateInfo, pipeline);
- calculate_gs_ring_sizes(pipeline, &gs);
+ calculate_gs_ring_sizes(pipeline, &gs->info.gs_ring_info);
}
struct radv_tessellation_state tess = {0};
pipeline->streamout_shader = radv_pipeline_get_streamout_shader(pipeline);
result = radv_pipeline_scratch_init(device, pipeline);
- radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend, &tess, &gs, &ngg, prim, gs_out);
+ radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend, &tess, prim, gs_out);
return result;
}
stage_feedbacks[MESA_SHADER_COMPUTE] = &creation_feedback->pPipelineStageCreationFeedbacks[0];
pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
- radv_create_shaders(pipeline, device, cache, &(struct radv_pipeline_key) {0}, pStages, pCreateInfo->flags, pipeline_feedback, stage_feedbacks);
+ radv_create_shaders(pipeline, device, cache, &(struct radv_pipeline_key) {0}, pStages, pCreateInfo->flags, NULL, pipeline_feedback, stage_feedbacks);
pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
projects / mesa.git / blobdiff