#include "spirv/nir_spirv.h"
#include "vk_util.h"
-#include <llvm-c/Core.h>
-#include <llvm-c/TargetMachine.h>
-
#include "sid.h"
#include "ac_binary.h"
#include "ac_llvm_util.h"
#include "util/debug.h"
#include "ac_exp_param.h"
#include "ac_shader_util.h"
-#include "main/menums.h"
struct radv_blend_state {
uint32_t blend_enable_4bit;
uint32_t tf_param;
};
+static const VkPipelineMultisampleStateCreateInfo *
+radv_pipeline_get_multisample_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
+{
+ if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
+ return pCreateInfo->pMultisampleState;
+ return NULL;
+}
+
+static const VkPipelineTessellationStateCreateInfo *
+radv_pipeline_get_tessellation_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
+{
+ for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
+ if (pCreateInfo->pStages[i].stage == VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT ||
+ pCreateInfo->pStages[i].stage == VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) {
+ return pCreateInfo->pTessellationState;
+ }
+ }
+ return NULL;
+}
+
+static const VkPipelineDepthStencilStateCreateInfo *
+radv_pipeline_get_depth_stencil_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
+{
+ RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
+ struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
+
+ if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
+ subpass->depth_stencil_attachment)
+ return pCreateInfo->pDepthStencilState;
+ return NULL;
+}
+
+static const VkPipelineColorBlendStateCreateInfo *
+radv_pipeline_get_color_blend_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
+{
+ RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
+ struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
+
+ if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
+ subpass->has_color_att)
+ return pCreateInfo->pColorBlendState;
+ return NULL;
+}
+
bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline)
{
struct radv_shader_variant *variant = NULL;
return variant->info.is_ngg;
}
+bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline *pipeline)
+{
+ assert(radv_pipeline_has_ngg(pipeline));
+
+ struct radv_shader_variant *variant = NULL;
+ if (pipeline->shaders[MESA_SHADER_GEOMETRY])
+ variant = pipeline->shaders[MESA_SHADER_GEOMETRY];
+ else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
+ variant = pipeline->shaders[MESA_SHADER_TESS_EVAL];
+ else if (pipeline->shaders[MESA_SHADER_VERTEX])
+ variant = pipeline->shaders[MESA_SHADER_VERTEX];
+ else
+ return false;
+ return variant->info.is_ngg_passthrough;
+}
+
bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline)
{
if (!radv_pipeline_has_gs(pipeline))
if(pipeline->cs.buf)
free(pipeline->cs.buf);
- vk_free2(&device->alloc, allocator, pipeline);
+
+ vk_object_base_finish(&pipeline->base);
+ vk_free2(&device->vk.alloc, allocator, pipeline);
}
void radv_DestroyPipeline(
if (device->instance->debug_flags & RADV_DEBUG_NO_NGG)
hash_flags |= RADV_HASH_SHADER_NO_NGG;
- if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
- hash_flags |= RADV_HASH_SHADER_SISCHED;
if (device->physical_device->cs_wave_size == 32)
hash_flags |= RADV_HASH_SHADER_CS_WAVE32;
if (device->physical_device->ps_wave_size == 32)
const VkGraphicsPipelineCreateInfo *pCreateInfo,
const struct radv_graphics_pipeline_create_info *extra)
{
- const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
- const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
+ const VkPipelineColorBlendStateCreateInfo *vkblend = radv_pipeline_get_color_blend_state(pCreateInfo);
+ const VkPipelineMultisampleStateCreateInfo *vkms = radv_pipeline_get_multisample_state(pCreateInfo);
struct radv_blend_state blend = {0};
unsigned mode = V_028808_CB_NORMAL;
int i;
- if (!vkblend)
- return blend;
-
if (extra && extra->custom_blend_mode) {
blend.single_cb_enable = true;
mode = extra->custom_blend_mode;
}
+
blend.cb_color_control = 0;
- if (vkblend->logicOpEnable)
- blend.cb_color_control |= S_028808_ROP3(si_translate_blend_logic_op(vkblend->logicOp));
- else
- blend.cb_color_control |= S_028808_ROP3(V_028808_ROP3_COPY);
+ if (vkblend) {
+ if (vkblend->logicOpEnable)
+ blend.cb_color_control |= S_028808_ROP3(si_translate_blend_logic_op(vkblend->logicOp));
+ else
+ blend.cb_color_control |= S_028808_ROP3(V_028808_ROP3_COPY);
+ }
blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
}
blend.cb_target_mask = 0;
- for (i = 0; i < vkblend->attachmentCount; i++) {
- const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
- unsigned blend_cntl = 0;
- unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
- VkBlendOp eqRGB = att->colorBlendOp;
- VkBlendFactor srcRGB = att->srcColorBlendFactor;
- VkBlendFactor dstRGB = att->dstColorBlendFactor;
- VkBlendOp eqA = att->alphaBlendOp;
- VkBlendFactor srcA = att->srcAlphaBlendFactor;
- VkBlendFactor dstA = att->dstAlphaBlendFactor;
-
- blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
-
- if (!att->colorWriteMask)
- continue;
+ if (vkblend) {
+ for (i = 0; i < vkblend->attachmentCount; i++) {
+ const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
+ unsigned blend_cntl = 0;
+ unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
+ VkBlendOp eqRGB = att->colorBlendOp;
+ VkBlendFactor srcRGB = att->srcColorBlendFactor;
+ VkBlendFactor dstRGB = att->dstColorBlendFactor;
+ VkBlendOp eqA = att->alphaBlendOp;
+ VkBlendFactor srcA = att->srcAlphaBlendFactor;
+ VkBlendFactor dstA = att->dstAlphaBlendFactor;
+
+ blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
+
+ if (!att->colorWriteMask)
+ continue;
- blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
- blend.cb_target_enabled_4bit |= 0xf << (4 * i);
- if (!att->blendEnable) {
- blend.cb_blend_control[i] = blend_cntl;
- continue;
- }
+ blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
+ blend.cb_target_enabled_4bit |= 0xf << (4 * i);
+ if (!att->blendEnable) {
+ blend.cb_blend_control[i] = blend_cntl;
+ continue;
+ }
- if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
- if (i == 0)
- blend.mrt0_is_dual_src = true;
+ if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
+ if (i == 0)
+ blend.mrt0_is_dual_src = true;
- if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
- srcRGB = VK_BLEND_FACTOR_ONE;
- dstRGB = VK_BLEND_FACTOR_ONE;
- }
- if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
- srcA = VK_BLEND_FACTOR_ONE;
- dstA = VK_BLEND_FACTOR_ONE;
- }
+ if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
+ srcRGB = VK_BLEND_FACTOR_ONE;
+ dstRGB = VK_BLEND_FACTOR_ONE;
+ }
+ if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
+ srcA = VK_BLEND_FACTOR_ONE;
+ dstA = VK_BLEND_FACTOR_ONE;
+ }
- radv_blend_check_commutativity(&blend, eqRGB, srcRGB, dstRGB,
- 0x7 << (4 * i));
- radv_blend_check_commutativity(&blend, eqA, srcA, dstA,
- 0x8 << (4 * i));
+ radv_blend_check_commutativity(&blend, eqRGB, srcRGB, dstRGB,
+ 0x7 << (4 * i));
+ radv_blend_check_commutativity(&blend, eqA, srcA, dstA,
+ 0x8 << (4 * i));
- /* Blending optimizations for RB+.
- * These transformations don't change the behavior.
- *
- * First, get rid of DST in the blend factors:
- * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
- */
- si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
- VK_BLEND_FACTOR_DST_COLOR,
- VK_BLEND_FACTOR_SRC_COLOR);
-
- si_blend_remove_dst(&eqA, &srcA, &dstA,
- VK_BLEND_FACTOR_DST_COLOR,
- VK_BLEND_FACTOR_SRC_COLOR);
-
- si_blend_remove_dst(&eqA, &srcA, &dstA,
- VK_BLEND_FACTOR_DST_ALPHA,
- VK_BLEND_FACTOR_SRC_ALPHA);
-
- /* Look up the ideal settings from tables. */
- srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
- dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
- srcA_opt = si_translate_blend_opt_factor(srcA, true);
- dstA_opt = si_translate_blend_opt_factor(dstA, true);
-
- /* Handle interdependencies. */
- if (si_blend_factor_uses_dst(srcRGB))
- dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
- if (si_blend_factor_uses_dst(srcA))
- dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
-
- if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
- (dstRGB == VK_BLEND_FACTOR_ZERO ||
- dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
- dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
- dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
-
- /* Set the final value. */
- blend.sx_mrt_blend_opt[i] =
- S_028760_COLOR_SRC_OPT(srcRGB_opt) |
- S_028760_COLOR_DST_OPT(dstRGB_opt) |
- S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
- S_028760_ALPHA_SRC_OPT(srcA_opt) |
- S_028760_ALPHA_DST_OPT(dstA_opt) |
- S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
- blend_cntl |= S_028780_ENABLE(1);
-
- blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
- blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
- blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
- if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
- blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
- blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
- blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
- blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
- }
- blend.cb_blend_control[i] = blend_cntl;
+ /* Blending optimizations for RB+.
+ * These transformations don't change the behavior.
+ *
+ * First, get rid of DST in the blend factors:
+ * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
+ */
+ si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
+ VK_BLEND_FACTOR_DST_COLOR,
+ VK_BLEND_FACTOR_SRC_COLOR);
+
+ si_blend_remove_dst(&eqA, &srcA, &dstA,
+ VK_BLEND_FACTOR_DST_COLOR,
+ VK_BLEND_FACTOR_SRC_COLOR);
+
+ si_blend_remove_dst(&eqA, &srcA, &dstA,
+ VK_BLEND_FACTOR_DST_ALPHA,
+ VK_BLEND_FACTOR_SRC_ALPHA);
+
+ /* Look up the ideal settings from tables. */
+ srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
+ dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
+ srcA_opt = si_translate_blend_opt_factor(srcA, true);
+ dstA_opt = si_translate_blend_opt_factor(dstA, true);
+
+ /* Handle interdependencies. */
+ if (si_blend_factor_uses_dst(srcRGB))
+ dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
+ if (si_blend_factor_uses_dst(srcA))
+ dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
+
+ if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
+ (dstRGB == VK_BLEND_FACTOR_ZERO ||
+ dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
+ dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
+ dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
+
+ /* Set the final value. */
+ blend.sx_mrt_blend_opt[i] =
+ S_028760_COLOR_SRC_OPT(srcRGB_opt) |
+ S_028760_COLOR_DST_OPT(dstRGB_opt) |
+ S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
+ S_028760_ALPHA_SRC_OPT(srcA_opt) |
+ S_028760_ALPHA_DST_OPT(dstA_opt) |
+ S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
+ blend_cntl |= S_028780_ENABLE(1);
+
+ blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
+ blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
+ blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
+ if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
+ blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
+ blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
+ blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
+ blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
+ }
+ blend.cb_blend_control[i] = blend_cntl;
- blend.blend_enable_4bit |= 0xfu << (i * 4);
+ blend.blend_enable_4bit |= 0xfu << (i * 4);
- if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
- dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
- srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
- dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
- srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
- dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
- blend.need_src_alpha |= 1 << i;
- }
- for (i = vkblend->attachmentCount; i < 8; i++) {
- blend.cb_blend_control[i] = 0;
- blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
+ if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
+ dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
+ srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
+ dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
+ srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
+ dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
+ blend.need_src_alpha |= 1 << i;
+ }
+ for (i = vkblend->attachmentCount; i < 8; i++) {
+ blend.cb_blend_control[i] = 0;
+ blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
+ }
}
if (pipeline->device->physical_device->rad_info.has_rbplus) {
/* RB+ doesn't work with dual source blending, logic op and
* RESOLVE.
*/
- if (blend.mrt0_is_dual_src || vkblend->logicOpEnable ||
+ if (blend.mrt0_is_dual_src ||
+ (vkblend && vkblend->logicOpEnable) ||
mode == V_028808_CB_RESOLVE)
blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
}
}
}
-static uint8_t radv_pipeline_get_ps_iter_samples(const VkPipelineMultisampleStateCreateInfo *vkms)
+static uint8_t radv_pipeline_get_ps_iter_samples(const VkGraphicsPipelineCreateInfo *pCreateInfo)
{
- uint32_t num_samples = vkms->rasterizationSamples;
+ const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
+ RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
+ struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
uint32_t ps_iter_samples = 1;
+ uint32_t num_samples;
+
+ /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
+ *
+ * "If the VK_AMD_mixed_attachment_samples extension is enabled and the
+ * subpass uses color attachments, totalSamples is the number of
+ * samples of the color attachments. Otherwise, totalSamples is the
+ * value of VkPipelineMultisampleStateCreateInfo::rasterizationSamples
+ * specified at pipeline creation time."
+ */
+ if (subpass->has_color_att) {
+ num_samples = subpass->color_sample_count;
+ } else {
+ num_samples = vkms->rasterizationSamples;
+ }
if (vkms->sampleShadingEnable) {
- ps_iter_samples = ceil(vkms->minSampleShading * num_samples);
+ ps_iter_samples = ceilf(vkms->minSampleShading * num_samples);
ps_iter_samples = util_next_power_of_two(ps_iter_samples);
}
return ps_iter_samples;
{
RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
+ const VkPipelineDepthStencilStateCreateInfo *vkds = radv_pipeline_get_depth_stencil_state(pCreateInfo);
+ const VkPipelineColorBlendStateCreateInfo *vkblend = radv_pipeline_get_color_blend_state(pCreateInfo);
unsigned colormask = blend->cb_target_enabled_4bit;
if (!pipeline->device->physical_device->out_of_order_rast_allowed)
return false;
/* Be conservative if a logic operation is enabled with color buffers. */
- if (colormask && pCreateInfo->pColorBlendState->logicOpEnable)
+ if (colormask && vkblend && vkblend->logicOpEnable)
return false;
/* Default depth/stencil invariance when no attachment is bound. */
.zs = true, .pass_set = true
};
- if (pCreateInfo->pDepthStencilState &&
- subpass->depth_stencil_attachment) {
- const VkPipelineDepthStencilStateCreateInfo *vkds =
- pCreateInfo->pDepthStencilState;
+ if (vkds) {
struct radv_render_pass_attachment *attachment =
pass->attachments + subpass->depth_stencil_attachment->attachment;
bool has_stencil = vk_format_is_stencil(attachment->format);
struct radv_blend_state *blend,
const VkGraphicsPipelineCreateInfo *pCreateInfo)
{
- const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
+ const VkPipelineMultisampleStateCreateInfo *vkms = radv_pipeline_get_multisample_state(pCreateInfo);
struct radv_multisample_state *ms = &pipeline->graphics.ms;
unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
bool out_of_order_rast = false;
int ps_iter_samples = 1;
uint32_t mask = 0xffff;
- if (vkms)
+ if (vkms) {
ms->num_samples = vkms->rasterizationSamples;
- else
- ms->num_samples = 1;
- if (vkms)
- ps_iter_samples = radv_pipeline_get_ps_iter_samples(vkms);
- if (vkms && !vkms->sampleShadingEnable && pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.force_persample) {
- ps_iter_samples = ms->num_samples;
+ /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
+ *
+ * "Sample shading is enabled for a graphics pipeline:
+ *
+ * - If the interface of the fragment shader entry point of the
+ * graphics pipeline includes an input variable decorated
+ * with SampleId or SamplePosition. In this case
+ * minSampleShadingFactor takes the value 1.0.
+ * - Else if the sampleShadingEnable member of the
+ * VkPipelineMultisampleStateCreateInfo structure specified
+ * when creating the graphics pipeline is set to VK_TRUE. In
+ * this case minSampleShadingFactor takes the value of
+ * VkPipelineMultisampleStateCreateInfo::minSampleShading.
+ *
+ * Otherwise, sample shading is considered disabled."
+ */
+ if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.force_persample) {
+ ps_iter_samples = ms->num_samples;
+ } else {
+ ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo);
+ }
+ } else {
+ ms->num_samples = 1;
}
const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
S_028A48_VPORT_SCISSOR_ENABLE(1);
+ const VkPipelineRasterizationLineStateCreateInfoEXT *rast_line =
+ vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
+ PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT);
+ if (rast_line) {
+ ms->pa_sc_mode_cntl_0 |= S_028A48_LINE_STIPPLE_ENABLE(rast_line->stippledLineEnable);
+ if (rast_line->lineRasterizationMode == VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT) {
+ /* From the Vulkan spec 1.1.129:
+ *
+ * "When VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT lines
+ * are being rasterized, sample locations may all be
+ * treated as being at the pixel center (this may
+ * affect attribute and depth interpolation)."
+ */
+ ms->num_samples = 1;
+ }
+ }
+
if (ms->num_samples > 1) {
+ RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
+ struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
+ uint32_t z_samples = subpass->depth_stencil_attachment ? subpass->depth_sample_count : ms->num_samples;
unsigned log_samples = util_logbase2(ms->num_samples);
+ unsigned log_z_samples = util_logbase2(z_samples);
unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
- ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
+ ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) |
S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
return RADV_DYNAMIC_DISCARD_RECTANGLE;
case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT:
return RADV_DYNAMIC_SAMPLE_LOCATIONS;
+ case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT:
+ return RADV_DYNAMIC_LINE_STIPPLE;
default:
unreachable("Unhandled dynamic state");
}
PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT))
states &= ~RADV_DYNAMIC_SAMPLE_LOCATIONS;
+ if (!pCreateInfo->pRasterizationState ||
+ !vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
+ PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT))
+ states &= ~RADV_DYNAMIC_LINE_STIPPLE;
+
/* TODO: blend constants & line width. */
return states;
}
}
+ const VkPipelineRasterizationLineStateCreateInfoEXT *rast_line_info =
+ vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
+ PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT);
+ if (needed_states & RADV_DYNAMIC_LINE_STIPPLE) {
+ dynamic->line_stipple.factor = rast_line_info->lineStippleFactor;
+ dynamic->line_stipple.pattern = rast_line_info->lineStipplePattern;
+ }
+
pipeline->dynamic_state.mask = states;
}
radv_optimize_nir(ordered_shaders[i - 1], false, false);
nir_remove_dead_variables(ordered_shaders[i],
- nir_var_shader_out);
+ nir_var_shader_out, NULL);
nir_remove_dead_variables(ordered_shaders[i - 1],
- nir_var_shader_in);
+ nir_var_shader_in, NULL);
bool progress = nir_remove_unused_varyings(ordered_shaders[i],
ordered_shaders[i - 1]);
}
}
+static void
+radv_set_linked_driver_locations(struct radv_pipeline *pipeline, nir_shader **shaders,
+ struct radv_shader_info infos[MESA_SHADER_STAGES])
+{
+ bool has_tess = shaders[MESA_SHADER_TESS_CTRL];
+ bool has_gs = shaders[MESA_SHADER_GEOMETRY];
+
+ if (!has_tess && !has_gs)
+ return;
+
+ unsigned vs_info_idx = MESA_SHADER_VERTEX;
+ unsigned tes_info_idx = MESA_SHADER_TESS_EVAL;
+
+ if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
+ /* These are merged into the next stage */
+ vs_info_idx = has_tess ? MESA_SHADER_TESS_CTRL : MESA_SHADER_GEOMETRY;
+ tes_info_idx = has_gs ? MESA_SHADER_GEOMETRY : MESA_SHADER_TESS_EVAL;
+ }
+
+ if (has_tess) {
+ nir_linked_io_var_info vs2tcs =
+ nir_assign_linked_io_var_locations(shaders[MESA_SHADER_VERTEX], shaders[MESA_SHADER_TESS_CTRL]);
+ nir_linked_io_var_info tcs2tes =
+ nir_assign_linked_io_var_locations(shaders[MESA_SHADER_TESS_CTRL], shaders[MESA_SHADER_TESS_EVAL]);
+
+ infos[vs_info_idx].vs.num_linked_outputs = vs2tcs.num_linked_io_vars;
+ infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_inputs = vs2tcs.num_linked_io_vars;
+ infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_outputs = tcs2tes.num_linked_io_vars;
+ infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_patch_outputs = tcs2tes.num_linked_patch_io_vars;
+ infos[tes_info_idx].tes.num_linked_inputs = tcs2tes.num_linked_io_vars;
+ infos[tes_info_idx].tes.num_linked_patch_inputs = tcs2tes.num_linked_patch_io_vars;
+
+ if (has_gs) {
+ nir_linked_io_var_info tes2gs =
+ nir_assign_linked_io_var_locations(shaders[MESA_SHADER_TESS_EVAL], shaders[MESA_SHADER_GEOMETRY]);
+
+ infos[tes_info_idx].tes.num_linked_outputs = tes2gs.num_linked_io_vars;
+ infos[MESA_SHADER_GEOMETRY].gs.num_linked_inputs = tes2gs.num_linked_io_vars;
+ }
+ } else if (has_gs) {
+ nir_linked_io_var_info vs2gs =
+ nir_assign_linked_io_var_locations(shaders[MESA_SHADER_VERTEX], shaders[MESA_SHADER_GEOMETRY]);
+
+ infos[vs_info_idx].vs.num_linked_outputs = vs2gs.num_linked_io_vars;
+ infos[MESA_SHADER_GEOMETRY].gs.num_linked_inputs = vs2gs.num_linked_io_vars;
+ }
+}
+
static uint32_t
radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo *input_state,
uint32_t attrib_binding)
}
}
- if (pCreateInfo->pTessellationState)
- key.tess_input_vertices = pCreateInfo->pTessellationState->patchControlPoints;
-
+ const VkPipelineTessellationStateCreateInfo *tess =
+ radv_pipeline_get_tessellation_state(pCreateInfo);
+ if (tess)
+ key.tess_input_vertices = tess->patchControlPoints;
- if (pCreateInfo->pMultisampleState &&
- pCreateInfo->pMultisampleState->rasterizationSamples > 1) {
- uint32_t num_samples = pCreateInfo->pMultisampleState->rasterizationSamples;
- uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo->pMultisampleState);
+ const VkPipelineMultisampleStateCreateInfo *vkms =
+ radv_pipeline_get_multisample_state(pCreateInfo);
+ if (vkms && vkms->rasterizationSamples > 1) {
+ uint32_t num_samples = vkms->rasterizationSamples;
+ uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo);
key.num_samples = num_samples;
key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
}
keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
}
- /*
- * Disable NGG with geometry shaders. There are a bunch of
- * issues still:
- * * GS primitives in pipeline statistic queries do not get
- * updates. See dEQP-VK.query_pool.statistics_query.geometry_shader_primitives
- *
- * Furthermore, XGL/AMDVLK also disables this as of 9b632ef.
- */
- if (nir[MESA_SHADER_GEOMETRY]) {
+ if (!device->physical_device->use_ngg_gs) {
+ if (nir[MESA_SHADER_GEOMETRY]) {
+ if (nir[MESA_SHADER_TESS_CTRL])
+ keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
+ else
+ keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
+ }
+ }
+
+ gl_shader_stage last_xfb_stage = MESA_SHADER_VERTEX;
+
+ for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
+ if (nir[i])
+ last_xfb_stage = i;
+ }
+
+ bool uses_xfb = nir[last_xfb_stage] &&
+ radv_nir_stage_uses_xfb(nir[last_xfb_stage]);
+
+ if (!device->physical_device->use_ngg_streamout && uses_xfb) {
if (nir[MESA_SHADER_TESS_CTRL])
keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
else
keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
}
- if (!device->physical_device->use_ngg_streamout) {
- gl_shader_stage last_xfb_stage = MESA_SHADER_VERTEX;
-
- for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
- if (nir[i])
- last_xfb_stage = i;
- }
-
- if (nir[last_xfb_stage] &&
- radv_nir_stage_uses_xfb(nir[last_xfb_stage])) {
- if (nir[MESA_SHADER_TESS_CTRL])
- keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
- else
- keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
+ /* Determine if the pipeline is eligible for the NGG passthrough
+ * mode. It can't be enabled for geometry shaders, for NGG
+ * streamout or for vertex shaders that export the primitive ID
+ * (this is checked later because we don't have the info here.)
+ */
+ if (!nir[MESA_SHADER_GEOMETRY] && !uses_xfb) {
+ if (nir[MESA_SHADER_TESS_CTRL] &&
+ keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg) {
+ keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg_passthrough = true;
+ } else if (nir[MESA_SHADER_VERTEX] &&
+ keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg) {
+ keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg_passthrough = true;
}
}
}
return device->physical_device->ge_wave_size;
}
+static uint8_t
+radv_get_ballot_bit_size(struct radv_device *device,
+ const VkPipelineShaderStageCreateInfo *pStage,
+ gl_shader_stage stage,
+ const struct radv_shader_variant_key *key)
+{
+ if (stage == MESA_SHADER_COMPUTE && key->cs.subgroup_size)
+ return key->cs.subgroup_size;
+ return 64;
+}
+
static void
radv_fill_shader_info(struct radv_pipeline *pipeline,
const VkPipelineShaderStageCreateInfo **pStages,
radv_nir_shader_info_pass(nir[MESA_SHADER_FRAGMENT],
pipeline->layout,
&keys[MESA_SHADER_FRAGMENT],
- &infos[MESA_SHADER_FRAGMENT]);
+ &infos[MESA_SHADER_FRAGMENT],
+ pipeline->device->physical_device->use_aco);
/* TODO: These are no longer used as keys we should refactor this */
keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id =
infos[MESA_SHADER_FRAGMENT].ps.layer_input;
keys[MESA_SHADER_VERTEX].vs_common_out.export_clip_dists =
!!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
+ keys[MESA_SHADER_VERTEX].vs_common_out.export_viewport_index =
+ infos[MESA_SHADER_FRAGMENT].ps.viewport_index_input;
keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_prim_id =
infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_layer_id =
infos[MESA_SHADER_FRAGMENT].ps.layer_input;
keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_clip_dists =
!!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
+ keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_viewport_index =
+ infos[MESA_SHADER_FRAGMENT].ps.viewport_index_input;
+
+ /* NGG passthrough mode can't be enabled for vertex shaders
+ * that export the primitive ID.
+ *
+ * TODO: I should really refactor the keys logic.
+ */
+ if (nir[MESA_SHADER_VERTEX] &&
+ keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id) {
+ keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg_passthrough = false;
+ }
filled_stages |= (1 << MESA_SHADER_FRAGMENT);
}
+ if (nir[MESA_SHADER_TESS_CTRL]) {
+ infos[MESA_SHADER_TESS_CTRL].tcs.tes_inputs_read =
+ nir[MESA_SHADER_TESS_EVAL]->info.inputs_read;
+ infos[MESA_SHADER_TESS_CTRL].tcs.tes_patch_inputs_read =
+ nir[MESA_SHADER_TESS_EVAL]->info.patch_inputs_read;
+ }
+
if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
nir[MESA_SHADER_TESS_CTRL]) {
struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
for (int i = 0; i < 2; i++) {
radv_nir_shader_info_pass(combined_nir[i],
pipeline->layout, &key,
- &infos[MESA_SHADER_TESS_CTRL]);
+ &infos[MESA_SHADER_TESS_CTRL],
+ pipeline->device->physical_device->use_aco);
}
keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
radv_nir_shader_info_pass(combined_nir[i],
pipeline->layout,
&keys[pre_stage],
- &infos[MESA_SHADER_GEOMETRY]);
+ &infos[MESA_SHADER_GEOMETRY],
+ pipeline->device->physical_device->use_aco);
}
filled_stages |= (1 << pre_stage);
radv_nir_shader_info_init(&infos[i]);
radv_nir_shader_info_pass(nir[i], pipeline->layout,
- &keys[i], &infos[i]);
+ &keys[i], &infos[i], pipeline->device->physical_device->use_aco);
}
for (int i = 0; i < MESA_SHADER_STAGES; i++) {
- if (nir[i])
+ if (nir[i]) {
infos[i].wave_size =
radv_get_wave_size(pipeline->device, pStages[i],
i, &keys[i]);
+ infos[i].ballot_bit_size =
+ radv_get_ballot_bit_size(pipeline->device,
+ pStages[i], i,
+ &keys[i]);
+ }
}
}
(cache_hit ? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT : 0);
}
-static
-bool radv_aco_supported_stage(gl_shader_stage stage, bool has_gs, bool has_ts)
-{
- return (stage == MESA_SHADER_VERTEX && !has_gs && !has_ts) ||
- stage == MESA_SHADER_FRAGMENT ||
- stage == MESA_SHADER_COMPUTE;
-}
-
-void radv_create_shaders(struct radv_pipeline *pipeline,
- struct radv_device *device,
- struct radv_pipeline_cache *cache,
- const struct radv_pipeline_key *key,
- const VkPipelineShaderStageCreateInfo **pStages,
- const VkPipelineCreateFlags flags,
- VkPipelineCreationFeedbackEXT *pipeline_feedback,
- VkPipelineCreationFeedbackEXT **stage_feedbacks)
+VkResult radv_create_shaders(struct radv_pipeline *pipeline,
+ struct radv_device *device,
+ struct radv_pipeline_cache *cache,
+ const struct radv_pipeline_key *key,
+ const VkPipelineShaderStageCreateInfo **pStages,
+ const VkPipelineCreateFlags flags,
+ VkPipelineCreationFeedbackEXT *pipeline_feedback,
+ VkPipelineCreationFeedbackEXT **stage_feedbacks)
{
struct radv_shader_module fs_m = {0};
struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
struct radv_shader_info infos[MESA_SHADER_STAGES] = {0};
unsigned char hash[20], gs_copy_hash[20];
bool keep_executable_info = (flags & VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR) || device->keep_shader_info;
+ bool keep_statistic_info = (flags & VK_PIPELINE_CREATE_CAPTURE_STATISTICS_BIT_KHR) ||
+ (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) ||
+ device->keep_shader_info;
radv_start_feedback(pipeline_feedback);
gs_copy_hash[0] ^= 1;
bool found_in_application_cache = true;
- if (modules[MESA_SHADER_GEOMETRY] && !keep_executable_info) {
+ if (modules[MESA_SHADER_GEOMETRY] && !keep_executable_info && !keep_statistic_info) {
struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants,
&found_in_application_cache);
pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
}
- if (!keep_executable_info &&
+ if (!keep_executable_info && !keep_statistic_info &&
radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders,
&found_in_application_cache) &&
(!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
radv_stop_feedback(pipeline_feedback, found_in_application_cache);
- return;
+ return VK_SUCCESS;
+ }
+
+ if (flags & VK_PIPELINE_CREATE_FAIL_ON_PIPELINE_COMPILE_REQUIRED_BIT_EXT) {
+ radv_stop_feedback(pipeline_feedback, found_in_application_cache);
+ return VK_PIPELINE_COMPILE_REQUIRED_EXT;
}
if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
modules[MESA_SHADER_FRAGMENT] = &fs_m;
}
- bool has_gs = modules[MESA_SHADER_GEOMETRY];
- bool has_ts = modules[MESA_SHADER_TESS_CTRL] || modules[MESA_SHADER_TESS_EVAL];
- bool use_aco = device->physical_device->use_aco;
-
for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
const VkPipelineShaderStageCreateInfo *stage = pStages[i];
+ unsigned subgroup_size = 64, ballot_bit_size = 64;
if (!modules[i])
continue;
radv_start_feedback(stage_feedbacks[i]);
- bool aco = use_aco && radv_aco_supported_stage(i, has_gs, has_ts);
+ if (key->compute_subgroup_size) {
+ /* Only compute shaders currently support requiring a
+ * specific subgroup size.
+ */
+ assert(i == MESA_SHADER_COMPUTE);
+ subgroup_size = key->compute_subgroup_size;
+ ballot_bit_size = key->compute_subgroup_size;
+ }
+
nir[i] = radv_shader_compile_to_nir(device, modules[i],
stage ? stage->pName : "main", i,
stage ? stage->pSpecializationInfo : NULL,
- flags, pipeline->layout, aco);
+ flags, pipeline->layout,
+ subgroup_size, ballot_bit_size);
/* We don't want to alter meta shaders IR directly so clone it
* first.
if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
radv_link_shaders(pipeline, nir);
+ radv_set_linked_driver_locations(pipeline, nir, infos);
+
for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
if (nir[i]) {
- NIR_PASS_V(nir[i], nir_lower_non_uniform_access,
- nir_lower_non_uniform_ubo_access |
- nir_lower_non_uniform_ssbo_access |
- nir_lower_non_uniform_texture_access |
- nir_lower_non_uniform_image_access);
-
- bool aco = use_aco && radv_aco_supported_stage(i, has_gs, has_ts);
- if (!aco)
+ /* do this again since information such as outputs_read can be out-of-date */
+ nir_shader_gather_info(nir[i], nir_shader_get_entrypoint(nir[i]));
+
+ if (device->physical_device->use_aco) {
+ NIR_PASS_V(nir[i], nir_lower_non_uniform_access,
+ nir_lower_non_uniform_ubo_access |
+ nir_lower_non_uniform_ssbo_access |
+ nir_lower_non_uniform_texture_access |
+ nir_lower_non_uniform_image_access);
+ } else
NIR_PASS_V(nir[i], nir_lower_bool_to_int32);
}
-
- if (radv_can_dump_shader(device, modules[i], false))
- nir_print_shader(nir[i], stderr);
}
if (nir[MESA_SHADER_FRAGMENT])
radv_lower_fs_io(nir[MESA_SHADER_FRAGMENT]);
+ for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
+ if (radv_can_dump_shader(device, modules[i], false))
+ nir_print_shader(nir[i], stderr);
+ }
+
radv_fill_shader_keys(device, keys, key, nir);
radv_fill_shader_info(pipeline, pStages, keys, infos, nir);
gfx9_get_gs_info(key, pipeline, nir, infos, gs_info);
}
+ if(modules[MESA_SHADER_GEOMETRY]) {
+ struct radv_shader_binary *gs_copy_binary = NULL;
+ if (!pipeline->gs_copy_shader &&
+ !radv_pipeline_has_ngg(pipeline)) {
+ struct radv_shader_info info = {};
+ struct radv_shader_variant_key key = {};
+
+ key.has_multiview_view_index =
+ keys[MESA_SHADER_GEOMETRY].has_multiview_view_index;
+
+ radv_nir_shader_info_pass(nir[MESA_SHADER_GEOMETRY],
+ pipeline->layout, &key,
+ &info, pipeline->device->physical_device->use_aco);
+ info.wave_size = 64; /* Wave32 not supported. */
+ info.ballot_bit_size = 64;
+
+ pipeline->gs_copy_shader = radv_create_gs_copy_shader(
+ device, nir[MESA_SHADER_GEOMETRY], &info,
+ &gs_copy_binary, keep_executable_info, keep_statistic_info,
+ keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
+ }
+
+ if (!keep_executable_info && !keep_statistic_info && pipeline->gs_copy_shader) {
+ struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
+ struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
+
+ binaries[MESA_SHADER_GEOMETRY] = gs_copy_binary;
+ variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
+
+ radv_pipeline_cache_insert_shaders(device, cache,
+ gs_copy_hash,
+ variants,
+ binaries);
+ }
+ free(gs_copy_binary);
+ }
+
if (nir[MESA_SHADER_FRAGMENT]) {
if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
radv_start_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT]);
- bool aco = use_aco && radv_aco_supported_stage(MESA_SHADER_FRAGMENT, has_gs, has_ts);
pipeline->shaders[MESA_SHADER_FRAGMENT] =
radv_shader_variant_compile(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
pipeline->layout, keys + MESA_SHADER_FRAGMENT,
infos + MESA_SHADER_FRAGMENT,
- keep_executable_info, aco,
+ keep_executable_info, keep_statistic_info,
&binaries[MESA_SHADER_FRAGMENT]);
radv_stop_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT], false);
}
-
- /* TODO: These are no longer used as keys we should refactor this */
- keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id =
- pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input;
- keys[MESA_SHADER_VERTEX].vs_common_out.export_layer_id =
- pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.layer_input;
- keys[MESA_SHADER_VERTEX].vs_common_out.export_clip_dists =
- !!pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.num_input_clips_culls;
- keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_prim_id =
- pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input;
- keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_layer_id =
- pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.layer_input;
- keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_clip_dists =
- !!pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.num_input_clips_culls;
}
if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_compile(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
pipeline->layout,
&key, &infos[MESA_SHADER_TESS_CTRL], keep_executable_info,
- false, &binaries[MESA_SHADER_TESS_CTRL]);
+ keep_statistic_info, &binaries[MESA_SHADER_TESS_CTRL]);
radv_stop_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL], false);
}
pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_compile(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
pipeline->layout,
&keys[pre_stage], &infos[MESA_SHADER_GEOMETRY], keep_executable_info,
- false, &binaries[MESA_SHADER_GEOMETRY]);
+ keep_statistic_info, &binaries[MESA_SHADER_GEOMETRY]);
radv_stop_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY], false);
}
radv_start_feedback(stage_feedbacks[i]);
- bool aco = use_aco && radv_aco_supported_stage(i, has_gs, has_ts);
pipeline->shaders[i] = radv_shader_variant_compile(device, modules[i], &nir[i], 1,
pipeline->layout,
- keys + i, infos + i,keep_executable_info,
- aco, &binaries[i]);
+ keys + i, infos + i, keep_executable_info,
+ keep_statistic_info, &binaries[i]);
radv_stop_feedback(stage_feedbacks[i], false);
}
}
- if(modules[MESA_SHADER_GEOMETRY]) {
- struct radv_shader_binary *gs_copy_binary = NULL;
- if (!pipeline->gs_copy_shader &&
- !radv_pipeline_has_ngg(pipeline)) {
- struct radv_shader_info info = {};
- struct radv_shader_variant_key key = {};
-
- key.has_multiview_view_index =
- keys[MESA_SHADER_GEOMETRY].has_multiview_view_index;
-
- radv_nir_shader_info_pass(nir[MESA_SHADER_GEOMETRY],
- pipeline->layout, &key,
- &info);
- info.wave_size = 64; /* Wave32 not supported. */
-
- pipeline->gs_copy_shader = radv_create_gs_copy_shader(
- device, nir[MESA_SHADER_GEOMETRY], &info,
- &gs_copy_binary, keep_executable_info,
- keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
- }
-
- if (!keep_executable_info && pipeline->gs_copy_shader) {
- struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
- struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
-
- binaries[MESA_SHADER_GEOMETRY] = gs_copy_binary;
- variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
-
- radv_pipeline_cache_insert_shaders(device, cache,
- gs_copy_hash,
- variants,
- binaries);
- }
- free(gs_copy_binary);
- }
-
- if (!keep_executable_info) {
+ if (!keep_executable_info && !keep_statistic_info) {
radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
binaries);
}
ralloc_free(fs_m.nir);
radv_stop_feedback(pipeline_feedback, false);
+ return VK_SUCCESS;
}
static uint32_t
unsigned effective_samples = total_samples;
unsigned color_bytes_per_pixel = 0;
- const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
+ const VkPipelineColorBlendStateCreateInfo *vkblend =
+ radv_pipeline_get_color_blend_state(pCreateInfo);
if (vkblend) {
for (unsigned i = 0; i < subpass->color_count; i++) {
if (!vkblend->pAttachments[i].colorWriteMask)
unsigned color_bytes_per_pixel = 0;
unsigned fmask_bytes_per_pixel = 0;
- const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
+ const VkPipelineColorBlendStateCreateInfo *vkblend =
+ radv_pipeline_get_color_blend_state(pCreateInfo);
if (vkblend) {
for (unsigned i = 0; i < subpass->color_count; i++) {
if (!vkblend->pAttachments[i].colorWriteMask)
if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
- const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
+ const VkPipelineColorBlendStateCreateInfo *vkblend =
+ radv_pipeline_get_color_blend_state(pCreateInfo);
unsigned min_bytes_per_pixel = 0;
if (vkblend) {
pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
}
+struct radv_binning_settings
+radv_get_binning_settings(const struct radv_physical_device *pdev)
+{
+ struct radv_binning_settings settings;
+ if (pdev->rad_info.has_dedicated_vram) {
+ if (pdev->rad_info.num_render_backends > 4) {
+ settings.context_states_per_bin = 1;
+ settings.persistent_states_per_bin = 1;
+ } else {
+ settings.context_states_per_bin = 3;
+ settings.persistent_states_per_bin = 8;
+ }
+ settings.fpovs_per_batch = 63;
+ } else {
+ /* The context states are affected by the scissor bug. */
+ settings.context_states_per_bin = 6;
+ /* 32 causes hangs for RAVEN. */
+ settings.persistent_states_per_bin = 16;
+ settings.fpovs_per_batch = 63;
+ }
+
+ if (pdev->rad_info.has_gfx9_scissor_bug)
+ settings.context_states_per_bin = 1;
+
+ return settings;
+}
+
static void
radv_pipeline_generate_binning_state(struct radeon_cmdbuf *ctx_cs,
struct radv_pipeline *pipeline,
unreachable("Unhandled generation for binning bin size calculation");
if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) {
- unsigned context_states_per_bin; /* allowed range: [1, 6] */
- unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
- unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
-
- if (pipeline->device->physical_device->rad_info.has_dedicated_vram) {
- context_states_per_bin = 1;
- persistent_states_per_bin = 1;
- fpovs_per_batch = 63;
- } else {
- /* The context states are affected by the scissor bug. */
- context_states_per_bin = pipeline->device->physical_device->rad_info.has_gfx9_scissor_bug ? 1 : 6;
- /* 32 causes hangs for RAVEN. */
- persistent_states_per_bin = 16;
- fpovs_per_batch = 63;
- }
+ struct radv_binning_settings settings =
+ radv_get_binning_settings(pipeline->device->physical_device);
bool disable_start_of_prim = true;
uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) |
S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) |
- S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin - 1) |
- S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin - 1) |
+ S_028C44_CONTEXT_STATES_PER_BIN(settings.context_states_per_bin - 1) |
+ S_028C44_PERSISTENT_STATES_PER_BIN(settings.persistent_states_per_bin - 1) |
S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim) |
- S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) |
+ S_028C44_FPOVS_PER_BATCH(settings.fpovs_per_batch) |
S_028C44_OPTIMAL_BIN_SELECTION(1);
pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
const VkGraphicsPipelineCreateInfo *pCreateInfo,
const struct radv_graphics_pipeline_create_info *extra)
{
- const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
+ const VkPipelineDepthStencilStateCreateInfo *vkds = radv_pipeline_get_depth_stencil_state(pCreateInfo);
RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
- db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
- db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
- db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
+ db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->resummarize_enable);
+ db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->depth_compress_disable);
+ db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->stencil_compress_disable);
db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
}
radeon_emit(ctx_cs, ms->pa_sc_aa_mask[1]);
radeon_set_context_reg(ctx_cs, R_028804_DB_EQAA, ms->db_eqaa);
+ radeon_set_context_reg(ctx_cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
radeon_set_context_reg(ctx_cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
+ radeon_set_context_reg(ctx_cs, R_028BDC_PA_SC_LINE_CNTL, ms->pa_sc_line_cntl);
+ radeon_set_context_reg(ctx_cs, R_028BE0_PA_SC_AA_CONFIG, ms->pa_sc_aa_config);
/* The exclusion bits can be set to improve rasterization efficiency
* if no sample lies on the pixel boundary (-8 sample offset). It's
radeon_set_context_reg(ctx_cs, R_02882C_PA_SU_PRIM_FILTER_CNTL,
S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
+
+ /* GFX9: Flush DFSM when the AA mode changes. */
+ if (pipeline->device->dfsm_allowed) {
+ radeon_emit(ctx_cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
+ radeon_emit(ctx_cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
+ }
}
static void
radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN,
S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
- S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id));
+ S_028A84_NGG_DISABLE_PROVOK_REUSE(outinfo->export_prim_id));
radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
ngg_state->vgt_esgs_ring_itemsize);
!radv_pipeline_has_gs(pipeline)));
ge_cntl = S_03096C_PRIM_GRP_SIZE(ngg_state->max_gsprims) |
- S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts) |
+ S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
/* Bug workaround for a possible hang with non-tessellation cases.
*
* Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
*/
- if ((pipeline->device->physical_device->rad_info.family == CHIP_NAVI10 ||
- pipeline->device->physical_device->rad_info.family == CHIP_NAVI12 ||
- pipeline->device->physical_device->rad_info.family == CHIP_NAVI14) &&
+ if (pipeline->device->physical_device->rad_info.chip_class == GFX10 &&
!radv_pipeline_has_tess(pipeline) &&
ngg_state->hw_max_esverts != 256) {
ge_cntl &= C_03096C_VERT_GRP_SIZE;
gs->info.gs.vertices_out);
}
-static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade, bool float16)
+static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade,
+ bool explicit, bool float16)
{
uint32_t ps_input_cntl;
if (offset <= AC_EXP_PARAM_OFFSET_31) {
ps_input_cntl = S_028644_OFFSET(offset);
- if (flat_shade)
+ if (flat_shade || explicit)
ps_input_cntl |= S_028644_FLAT_SHADE(1);
+ if (explicit) {
+ /* Force parameter cache to be read in passthrough
+ * mode.
+ */
+ ps_input_cntl |= S_028644_OFFSET(1 << 5);
+ }
if (float16) {
ps_input_cntl |= S_028644_FP16_INTERP_MODE(1) |
S_028644_ATTR0_VALID(1);
if (ps->info.ps.prim_id_input) {
unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
- ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false);
+ ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false);
++ps_offset;
}
}
ps->info.needs_multiview_view_index) {
unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
if (vs_offset != AC_EXP_PARAM_UNDEFINED)
- ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false);
+ ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false);
else
- ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false);
+ ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false, false);
+ ++ps_offset;
+ }
+
+ if (ps->info.ps.viewport_index_input) {
+ unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VIEWPORT];
+ if (vs_offset != AC_EXP_PARAM_UNDEFINED)
+ ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false);
+ else
+ ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false, false);
++ps_offset;
}
vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0];
if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
- ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false);
+ ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false, false);
++ps_offset;
}
vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1];
if (vs_offset != AC_EXP_PARAM_UNDEFINED &&
ps->info.ps.num_input_clips_culls > 4) {
- ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false);
+ ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false, false);
++ps_offset;
}
}
for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.ps.input_mask; ++i) {
unsigned vs_offset;
bool flat_shade;
+ bool explicit;
bool float16;
if (!(ps->info.ps.input_mask & (1u << i)))
continue;
}
flat_shade = !!(ps->info.ps.flat_shaded_mask & (1u << ps_offset));
+ explicit = !!(ps->info.ps.explicit_shaded_mask & (1u << ps_offset));
float16 = !!(ps->info.ps.float16_shaded_mask & (1u << ps_offset));
- ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade, float16);
+ ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade, explicit, float16);
++ps_offset;
}
const struct radv_pipeline *pipeline,
const struct radv_shader_variant *ps)
{
+ unsigned conservative_z_export = V_02880C_EXPORT_ANY_Z;
unsigned z_order;
if (ps->info.ps.early_fragment_test || !ps->info.ps.writes_memory)
z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
else
z_order = V_02880C_LATE_Z;
+ if (ps->info.ps.depth_layout == FRAG_DEPTH_LAYOUT_GREATER)
+ conservative_z_export = V_02880C_EXPORT_GREATER_THAN_Z;
+ else if (ps->info.ps.depth_layout == FRAG_DEPTH_LAYOUT_LESS)
+ conservative_z_export = V_02880C_EXPORT_LESS_THAN_Z;
+
bool disable_rbplus = device->physical_device->rad_info.has_rbplus &&
!device->physical_device->rad_info.rbplus_allowed;
S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.ps.writes_stencil) |
S_02880C_KILL_ENABLE(!!ps->info.ps.can_discard) |
S_02880C_MASK_EXPORT_ENABLE(mask_export_enable) |
+ S_02880C_CONSERVATIVE_Z_EXPORT(conservative_z_export) |
S_02880C_Z_ORDER(z_order) |
S_02880C_DEPTH_BEFORE_SHADER(ps->info.ps.early_fragment_test) |
S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps->info.ps.post_depth_coverage) |
stages |= S_028B54_PRIMGEN_EN(1);
if (pipeline->streamout_shader)
stages |= S_028B54_NGG_WAVE_ID_EN(1);
+ if (radv_pipeline_has_ngg_passthrough(pipeline))
+ stages |= S_028B54_PRIMGEN_PASSTHRU_EN(1);
} else if (radv_pipeline_has_gs(pipeline)) {
stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
}
{
bool break_wave_at_eoi = false;
unsigned primgroup_size;
- unsigned vertgroup_size;
+ unsigned vertgroup_size = 256; /* 256 = disable vertex grouping */
if (radv_pipeline_has_tess(pipeline)) {
primgroup_size = tess->num_patches; /* must be a multiple of NUM_PATCHES */
- vertgroup_size = 0;
} else if (radv_pipeline_has_gs(pipeline)) {
const struct gfx9_gs_info *gs_state =
&pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs_ring_info;
unsigned vgt_gs_onchip_cntl = gs_state->vgt_gs_onchip_cntl;
primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl);
- vertgroup_size = G_028A44_ES_VERTS_PER_SUBGRP(vgt_gs_onchip_cntl);
} else {
primgroup_size = 128; /* recommended without a GS and tess */
- vertgroup_size = 0;
}
if (radv_pipeline_has_tess(pipeline)) {
if (radv_device_use_secure_compile(device->instance)) {
return radv_secure_compile(pipeline, device, &key, pStages, pCreateInfo->flags, pCreateInfo->stageCount);
} else {
- radv_create_shaders(pipeline, device, cache, &key, pStages, pCreateInfo->flags, pipeline_feedback, stage_feedbacks);
+ result = radv_create_shaders(pipeline, device, cache, &key, pStages,
+ pCreateInfo->flags, pipeline_feedback,
+ stage_feedbacks);
+ if (result != VK_SUCCESS)
+ return result;
}
pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
uint32_t gs_out;
uint32_t prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
+ pipeline->graphics.topology = pCreateInfo->pInputAssemblyState->topology;
pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
if (radv_pipeline_has_gs(pipeline)) {
struct radv_pipeline *pipeline;
VkResult result;
- pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
+ pipeline = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*pipeline), 8,
VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
if (pipeline == NULL)
return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
+ vk_object_base_init(&device->vk, &pipeline->base,
+ VK_OBJECT_TYPE_PIPELINE);
+
result = radv_pipeline_init(pipeline, device, cache,
pCreateInfo, extra);
if (result != VK_SUCCESS) {
if (r != VK_SUCCESS) {
result = r;
pPipelines[i] = VK_NULL_HANDLE;
+
+ if (pCreateInfos[i].flags & VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT)
+ break;
}
}
+ for (; i < count; ++i)
+ pPipelines[i] = VK_NULL_HANDLE;
+
return result;
}
struct radv_pipeline *pipeline;
VkResult result;
- pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
+ pipeline = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*pipeline), 8,
VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
if (pipeline == NULL)
return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
+ vk_object_base_init(&device->vk, &pipeline->base,
+ VK_OBJECT_TYPE_PIPELINE);
+
pipeline->device = device;
pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
assert(pipeline->layout);
return result;
} else {
- radv_create_shaders(pipeline, device, cache, &key, pStages, pCreateInfo->flags, pipeline_feedback, stage_feedbacks);
+ result = radv_create_shaders(pipeline, device, cache, &key, pStages,
+ pCreateInfo->flags, pipeline_feedback,
+ stage_feedbacks);
+ if (result != VK_SUCCESS) {
+ radv_pipeline_destroy(device, pipeline, pAllocator);
+ return result;
+ }
}
pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
if (r != VK_SUCCESS) {
result = r;
pPipelines[i] = VK_NULL_HANDLE;
+
+ if (pCreateInfos[i].flags & VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT)
+ break;
}
}
+ for (; i < count; ++i)
+ pPipelines[i] = VK_NULL_HANDLE;
+
return result;
}
}
++s;
+ if (shader->statistics) {
+ for (unsigned i = 0; i < shader->statistics->count; i++) {
+ struct radv_compiler_statistic_info *info = &shader->statistics->infos[i];
+ uint32_t value = shader->statistics->values[i];
+ if (s < end) {
+ desc_copy(s->name, info->name);
+ desc_copy(s->description, info->desc);
+ s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
+ s->value.u64 = value;
+ }
+ ++s;
+ }
+ }
+
if (!pStatistics)
*pStatisticCount = s - pStatistics;
else if (s > end) {
/* backend IR */
if (p < end) {
p->isText = true;
- if (shader->aco_used) {
+ if (pipeline->device->physical_device->use_aco) {
desc_copy(p->name, "ACO IR");
desc_copy(p->description, "The ACO IR after some optimizations");
} else {