radv/ac: add support for indirect access of descriptor sets.

[mesa.git] / src / amd / vulkan / radv_pipeline.c

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index c2dd498b07819e8899ecd101e2099eb943c42d19..8e71d59fae7f2ed1f3a49e9c06490cd453b3cb66 100644 (file)
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -212,6 +212,7 @@ radv_shader_compile_to_nir(struct radv_device *device,
                        .float64 = true,
                        .image_read_without_format = true,
                        .image_write_without_format = true,
+                       .tessellation = true,
                };
                entry_point = spirv_to_nir(spirv, module->size / 4,
                                           spec_entries, num_spec_entries,
@@ -2111,6 +2112,12 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
        calculate_pa_cl_vs_out_cntl(pipeline);
        calculate_ps_inputs(pipeline);
 
+       for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
+               if (pipeline->shaders[i]) {
+                       pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
+               }
+       }
+
        uint32_t stages = 0;
        if (radv_pipeline_has_tess(pipeline)) {
                stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
@@ -2269,6 +2276,7 @@ static VkResult radv_compute_pipeline_create(
                                       pipeline->layout, NULL);
 
 
+       pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
        result = radv_pipeline_scratch_init(device, pipeline);
        if (result != VK_SUCCESS) {
                radv_pipeline_destroy(device, pipeline, pAllocator);