radv: switch on EOP when primitive restart is enabled with triangle strips

[mesa.git] / src / amd / vulkan / radv_pipeline.c

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 304597216924d84af3329dbb9b441abcc3ca6372..92c35b2e5091d38cde5a38893c54b09013444b4e 100644 (file)
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1814,6 +1814,10 @@ radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
                nir_lower_io_arrays_to_elements(ordered_shaders[i],
                                                ordered_shaders[i - 1]);
 
+               if (nir_link_constant_varyings(ordered_shaders[i],
+                                              ordered_shaders[i - 1]))
+                       radv_optimize_nir(ordered_shaders[i - 1], false, false);
+
                nir_remove_dead_variables(ordered_shaders[i],
                                          nir_var_shader_out);
                nir_remove_dead_variables(ordered_shaders[i - 1],
@@ -2701,7 +2705,7 @@ radv_pipeline_generate_raster_state(struct radeon_cmdbuf *cs,
        const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
        const VkConservativeRasterizationModeEXT mode =
                radv_get_conservative_raster_mode(vkraster);
-       uint32_t pa_sc_conservative_rast = 0;
+       uint32_t pa_sc_conservative_rast = S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
 
        radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
                               S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
@@ -2782,6 +2786,15 @@ radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *cs,
 
        radeon_set_context_reg(cs, R_028804_DB_EQAA, ms->db_eqaa);
        radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
+
+       /* The exclusion bits can be set to improve rasterization efficiency
+        * if no sample lies on the pixel boundary (-8 sample offset). It's
+        * currently always TRUE because the driver doesn't support 16 samples.
+        */
+       bool exclusion = pipeline->device->physical_device->rad_info.chip_class >= CIK;
+       radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL,
+                              S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
+                              S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
 }
 
 static void
@@ -3157,8 +3170,10 @@ radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *cs,
 
 static uint32_t
 radv_compute_db_shader_control(const struct radv_device *device,
+                              const struct radv_pipeline *pipeline,
                                const struct radv_shader_variant *ps)
 {
+       const struct radv_multisample_state *ms = &pipeline->graphics.ms;
        unsigned z_order;
        if (ps->info.fs.early_fragment_test || !ps->info.info.ps.writes_memory)
                z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
@@ -3168,10 +3183,16 @@ radv_compute_db_shader_control(const struct radv_device *device,
        bool disable_rbplus = device->physical_device->has_rbplus &&
                              !device->physical_device->rbplus_allowed;
 
+       /* Do not enable the gl_SampleMask fragment shader output if MSAA is
+        * disabled.
+        */
+       bool mask_export_enable = ms->num_samples > 1 &&
+                                 ps->info.info.ps.writes_sample_mask;
+
        return  S_02880C_Z_EXPORT_ENABLE(ps->info.info.ps.writes_z) |
                S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.info.ps.writes_stencil) |
                S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
-               S_02880C_MASK_EXPORT_ENABLE(ps->info.info.ps.writes_sample_mask) |
+               S_02880C_MASK_EXPORT_ENABLE(mask_export_enable) |
                S_02880C_Z_ORDER(z_order) |
                S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
                S_02880C_EXEC_ON_HIER_FAIL(ps->info.info.ps.writes_memory) |
@@ -3197,7 +3218,8 @@ radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf *cs,
        radeon_emit(cs, ps->rsrc2);
 
        radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
-                              radv_compute_db_shader_control(pipeline->device, ps));
+                              radv_compute_db_shader_control(pipeline->device,
+                                                             pipeline, ps));
 
        radeon_set_context_reg(cs, R_0286CC_SPI_PS_INPUT_ENA,
                               ps->config.spi_ps_input_ena);
@@ -3353,14 +3375,8 @@ radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
        else
                ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */
 
-       ia_multi_vgt_param.partial_es_wave = false;
-       if (pipeline->device->has_distributed_tess) {
-               if (radv_pipeline_has_gs(pipeline)) {
-                       if (device->physical_device->rad_info.chip_class <= VI)
-                               ia_multi_vgt_param.partial_es_wave = true;
-               }
-       }
        /* GS requirement. */
+       ia_multi_vgt_param.partial_es_wave = false;
        if (radv_pipeline_has_gs(pipeline) && device->physical_device->rad_info.chip_class <= VI)
                if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
                        ia_multi_vgt_param.partial_es_wave = true;
@@ -3378,8 +3394,7 @@ radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
                    (pipeline->graphics.prim_restart_enable &&
                     (device->physical_device->rad_info.family < CHIP_POLARIS10 ||
                      (prim != V_008958_DI_PT_POINTLIST &&
-                      prim != V_008958_DI_PT_LINESTRIP &&
-                      prim != V_008958_DI_PT_TRISTRIP))))
+                      prim != V_008958_DI_PT_LINESTRIP))))
                        ia_multi_vgt_param.wd_switch_on_eop = true;
        }
 
@@ -3407,6 +3422,9 @@ radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
                /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
                if (device->has_distributed_tess) {
                        if (radv_pipeline_has_gs(pipeline)) {
+                               if (device->physical_device->rad_info.chip_class <= VI)
+                                       ia_multi_vgt_param.partial_es_wave = true;
+
                                if (device->physical_device->rad_info.family == CHIP_TONGA ||
                                    device->physical_device->rad_info.family == CHIP_FIJI ||
                                    device->physical_device->rad_info.family == CHIP_POLARIS10 ||