unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
gs->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in;
unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
- gs_info->gs.max_gsvs_emit_size * 1; // no streams in VK (gs->max_gs_stream + 1);
+ gs_info->gs.max_gsvs_emit_size;
min_esgs_ring_size = align(min_esgs_ring_size, alignment);
esgs_ring_size = align(esgs_ring_size, alignment);
ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
}
+ if (shader_count > 1) {
+ unsigned first = ordered_shaders[shader_count - 1]->info.stage;
+ unsigned last = ordered_shaders[0]->info.stage;
+
+ if (ordered_shaders[0]->info.stage == MESA_SHADER_FRAGMENT &&
+ ordered_shaders[1]->info.has_transform_feedback_varyings)
+ nir_link_xfb_varyings(ordered_shaders[1], ordered_shaders[0]);
+
+ for (int i = 0; i < shader_count; ++i) {
+ nir_variable_mode mask = 0;
+
+ if (ordered_shaders[i]->info.stage != first)
+ mask = mask | nir_var_shader_in;
+
+ if (ordered_shaders[i]->info.stage != last)
+ mask = mask | nir_var_shader_out;
+
+ nir_lower_io_to_scalar_early(ordered_shaders[i], mask);
+ radv_optimize_nir(ordered_shaders[i], false, false);
+ }
+ }
+
for (int i = 1; i < shader_count; ++i) {
nir_lower_io_arrays_to_elements(ordered_shaders[i],
ordered_shaders[i - 1]);
+ if (nir_link_constant_varyings(ordered_shaders[i],
+ ordered_shaders[i - 1]))
+ radv_optimize_nir(ordered_shaders[i - 1], false, false);
+
nir_remove_dead_variables(ordered_shaders[i],
nir_var_shader_out);
nir_remove_dead_variables(ordered_shaders[i - 1],
ac_lower_indirect_derefs(ordered_shaders[i],
pipeline->device->physical_device->rad_info.chip_class);
}
- radv_optimize_nir(ordered_shaders[i], false);
+ radv_optimize_nir(ordered_shaders[i], false, false);
if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
ac_lower_indirect_derefs(ordered_shaders[i - 1],
pipeline->device->physical_device->rad_info.chip_class);
}
- radv_optimize_nir(ordered_shaders[i - 1], false);
+ radv_optimize_nir(ordered_shaders[i - 1], false, false);
}
}
}
modules[MESA_SHADER_FRAGMENT] = &fs_m;
}
- /* Determine first and last stage. */
- unsigned first = MESA_SHADER_STAGES;
- unsigned last = 0;
- for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
- if (!pStages[i])
- continue;
- if (first == MESA_SHADER_STAGES)
- first = i;
- last = i;
- }
-
for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
const VkPipelineShaderStageCreateInfo *stage = pStages[i];
if (nir[i]->info.name) {
nir[i] = nir_shader_clone(NULL, nir[i]);
}
-
- if (first != last) {
- nir_variable_mode mask = 0;
-
- if (i != first)
- mask = mask | nir_var_shader_in;
-
- if (i != last)
- mask = mask | nir_var_shader_out;
-
- if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)) {
- nir_lower_io_to_scalar_early(nir[i], mask);
- radv_optimize_nir(nir[i], false);
- }
- }
}
if (nir[MESA_SHADER_TESS_CTRL]) {
fpovs_per_batch = 63;
break;
case CHIP_RAVEN:
+ case CHIP_RAVEN2:
context_states_per_bin = 6;
persistent_states_per_bin = 32;
fpovs_per_batch = 63;
const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
const VkConservativeRasterizationModeEXT mode =
radv_get_conservative_raster_mode(vkraster);
- uint32_t pa_sc_conservative_rast = 0;
+ uint32_t pa_sc_conservative_rast = S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
radeon_set_context_reg(cs, R_028804_DB_EQAA, ms->db_eqaa);
radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
+
+ /* The exclusion bits can be set to improve rasterization efficiency
+ * if no sample lies on the pixel boundary (-8 sample offset). It's
+ * currently always TRUE because the driver doesn't support 16 samples.
+ */
+ bool exclusion = pipeline->device->physical_device->rad_info.chip_class >= CIK;
+ radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL,
+ S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
+ S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
}
static void
const struct radv_gs_state *gs_state)
{
struct radv_shader_variant *gs;
+ unsigned gs_max_out_vertices;
+ uint8_t *num_components;
+ uint8_t max_stream;
+ unsigned offset;
uint64_t va;
gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
if (!gs)
return;
- uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
+ gs_max_out_vertices = gs->info.gs.vertices_out;
+ max_stream = gs->info.info.gs.max_stream;
+ num_components = gs->info.info.gs.num_stream_output_components;
- radeon_set_context_reg_seq(cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
- radeon_emit(cs, gsvs_itemsize);
- radeon_emit(cs, gsvs_itemsize);
- radeon_emit(cs, gsvs_itemsize);
+ offset = num_components[0] * gs_max_out_vertices;
- radeon_set_context_reg(cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
+ radeon_set_context_reg_seq(cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
+ radeon_emit(cs, offset);
+ if (max_stream >= 1)
+ offset += num_components[1] * gs_max_out_vertices;
+ radeon_emit(cs, offset);
+ if (max_stream >= 2)
+ offset += num_components[2] * gs_max_out_vertices;
+ radeon_emit(cs, offset);
+ if (max_stream >= 3)
+ offset += num_components[3] * gs_max_out_vertices;
+ radeon_set_context_reg(cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
radeon_set_context_reg(cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
- uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
radeon_set_context_reg_seq(cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
- radeon_emit(cs, gs_vert_itemsize >> 2);
- radeon_emit(cs, 0);
- radeon_emit(cs, 0);
- radeon_emit(cs, 0);
+ radeon_emit(cs, num_components[0]);
+ radeon_emit(cs, (max_stream >= 1) ? num_components[1] : 0);
+ radeon_emit(cs, (max_stream >= 2) ? num_components[2] : 0);
+ radeon_emit(cs, (max_stream >= 3) ? num_components[3] : 0);
uint32_t gs_num_invocations = gs->info.gs.invocations;
radeon_set_context_reg(cs, R_028B90_VGT_GS_INSTANCE_CNT,
vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0];
if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
- ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
+ ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false);
++ps_offset;
}
vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1];
if (vs_offset != AC_EXP_PARAM_UNDEFINED &&
ps->info.info.ps.num_input_clips_culls > 4) {
- ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
+ ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false);
++ps_offset;
}
}
static uint32_t
radv_compute_db_shader_control(const struct radv_device *device,
+ const struct radv_pipeline *pipeline,
const struct radv_shader_variant *ps)
{
+ const struct radv_multisample_state *ms = &pipeline->graphics.ms;
unsigned z_order;
if (ps->info.fs.early_fragment_test || !ps->info.info.ps.writes_memory)
z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
bool disable_rbplus = device->physical_device->has_rbplus &&
!device->physical_device->rbplus_allowed;
+ /* Do not enable the gl_SampleMask fragment shader output if MSAA is
+ * disabled.
+ */
+ bool mask_export_enable = ms->num_samples > 1 &&
+ ps->info.info.ps.writes_sample_mask;
+
return S_02880C_Z_EXPORT_ENABLE(ps->info.info.ps.writes_z) |
S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.info.ps.writes_stencil) |
S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
- S_02880C_MASK_EXPORT_ENABLE(ps->info.info.ps.writes_sample_mask) |
+ S_02880C_MASK_EXPORT_ENABLE(mask_export_enable) |
S_02880C_Z_ORDER(z_order) |
S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
S_02880C_EXEC_ON_HIER_FAIL(ps->info.info.ps.writes_memory) |
radeon_emit(cs, ps->rsrc2);
radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
- radv_compute_db_shader_control(pipeline->device, ps));
+ radv_compute_db_shader_control(pipeline->device,
+ pipeline, ps));
radeon_set_context_reg(cs, R_0286CC_SPI_PS_INPUT_ENA,
ps->config.spi_ps_input_ena);
else
ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */
- ia_multi_vgt_param.partial_es_wave = false;
- if (pipeline->device->has_distributed_tess) {
- if (radv_pipeline_has_gs(pipeline)) {
- if (device->physical_device->rad_info.chip_class <= VI)
- ia_multi_vgt_param.partial_es_wave = true;
- }
- }
/* GS requirement. */
+ ia_multi_vgt_param.partial_es_wave = false;
if (radv_pipeline_has_gs(pipeline) && device->physical_device->rad_info.chip_class <= VI)
if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
ia_multi_vgt_param.partial_es_wave = true;
(pipeline->graphics.prim_restart_enable &&
(device->physical_device->rad_info.family < CHIP_POLARIS10 ||
(prim != V_008958_DI_PT_POINTLIST &&
- prim != V_008958_DI_PT_LINESTRIP &&
- prim != V_008958_DI_PT_TRISTRIP))))
+ prim != V_008958_DI_PT_LINESTRIP))))
ia_multi_vgt_param.wd_switch_on_eop = true;
}
/* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
if (device->has_distributed_tess) {
if (radv_pipeline_has_gs(pipeline)) {
+ if (device->physical_device->rad_info.chip_class <= VI)
+ ia_multi_vgt_param.partial_es_wave = true;
+
if (device->physical_device->rad_info.family == CHIP_TONGA ||
device->physical_device->rad_info.family == CHIP_FIJI ||
device->physical_device->rad_info.family == CHIP_POLARIS10 ||
}
}
+static struct radv_shader_variant *
+radv_pipeline_get_streamout_shader(struct radv_pipeline *pipeline)
+{
+ int i;
+
+ for (i = MESA_SHADER_GEOMETRY; i >= MESA_SHADER_VERTEX; i--) {
+ struct radv_shader_variant *shader =
+ radv_get_shader(pipeline, i);
+
+ if (shader && shader->info.info.so.num_outputs > 0)
+ return shader;
+ }
+
+ return NULL;
+}
+
static VkResult
radv_pipeline_init(struct radv_pipeline *pipeline,
struct radv_device *device,
pipeline->graphics.vtx_emit_num = 2;
}
+ /* Find the last vertex shader stage that eventually uses streamout. */
+ pipeline->streamout_shader = radv_pipeline_get_streamout_shader(pipeline);
+
result = radv_pipeline_scratch_init(device, pipeline);
radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend, &tess, &gs, prim, gs_out);
projects / mesa.git / blobdiff