#include "util/debug.h"
#include "ac_exp_param.h"
#include "ac_shader_util.h"
+#include "main/menums.h"
struct radv_blend_state {
+ uint32_t blend_enable_4bit;
+ uint32_t need_src_alpha;
+
uint32_t cb_color_control;
uint32_t cb_target_mask;
+ uint32_t cb_target_enabled_4bit;
uint32_t sx_mrt_blend_opt[8];
uint32_t cb_blend_control[8];
uint32_t spi_shader_col_format;
uint32_t cb_shader_mask;
uint32_t db_alpha_to_mask;
+
+ uint32_t commutative_4bit;
+
+ bool single_cb_enable;
+ bool mrt0_is_dual_src;
+};
+
+struct radv_dsa_order_invariance {
+ /* Whether the final result in Z/S buffers is guaranteed to be
+ * invariant under changes to the order in which fragments arrive.
+ */
+ bool zs;
+
+ /* Whether the set of fragments that pass the combined Z/S test is
+ * guaranteed to be invariant under changes to the order in which
+ * fragments arrive.
+ */
+ bool pass_set;
};
struct radv_tessellation_state {
uint32_t ls_hs_config;
- uint32_t tcs_in_layout;
- uint32_t tcs_out_layout;
- uint32_t tcs_out_offsets;
- uint32_t offchip_layout;
unsigned num_patches;
unsigned lds_size;
uint32_t tf_param;
if (scratch_bytes_per_wave && max_waves < min_waves) {
/* Not really true at this moment, but will be true on first
* execution. Avoid having hanging shaders. */
- return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
+ return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
}
pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
pipeline->max_waves = max_waves;
return VK_SUCCESS;
}
+static uint32_t si_translate_blend_logic_op(VkLogicOp op)
+{
+ switch (op) {
+ case VK_LOGIC_OP_CLEAR:
+ return V_028808_ROP3_CLEAR;
+ case VK_LOGIC_OP_AND:
+ return V_028808_ROP3_AND;
+ case VK_LOGIC_OP_AND_REVERSE:
+ return V_028808_ROP3_AND_REVERSE;
+ case VK_LOGIC_OP_COPY:
+ return V_028808_ROP3_COPY;
+ case VK_LOGIC_OP_AND_INVERTED:
+ return V_028808_ROP3_AND_INVERTED;
+ case VK_LOGIC_OP_NO_OP:
+ return V_028808_ROP3_NO_OP;
+ case VK_LOGIC_OP_XOR:
+ return V_028808_ROP3_XOR;
+ case VK_LOGIC_OP_OR:
+ return V_028808_ROP3_OR;
+ case VK_LOGIC_OP_NOR:
+ return V_028808_ROP3_NOR;
+ case VK_LOGIC_OP_EQUIVALENT:
+ return V_028808_ROP3_EQUIVALENT;
+ case VK_LOGIC_OP_INVERT:
+ return V_028808_ROP3_INVERT;
+ case VK_LOGIC_OP_OR_REVERSE:
+ return V_028808_ROP3_OR_REVERSE;
+ case VK_LOGIC_OP_COPY_INVERTED:
+ return V_028808_ROP3_COPY_INVERTED;
+ case VK_LOGIC_OP_OR_INVERTED:
+ return V_028808_ROP3_OR_INVERTED;
+ case VK_LOGIC_OP_NAND:
+ return V_028808_ROP3_NAND;
+ case VK_LOGIC_OP_SET:
+ return V_028808_ROP3_SET;
+ default:
+ unreachable("Unhandled logic op");
+ }
+}
+
+
static uint32_t si_translate_blend_function(VkBlendOp op)
{
switch (op) {
static void
radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
const VkGraphicsPipelineCreateInfo *pCreateInfo,
- uint32_t blend_enable,
- uint32_t blend_need_alpha,
- bool single_cb_enable,
- bool blend_mrt0_is_dual_src,
struct radv_blend_state *blend)
{
RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
unsigned col_format = 0;
+ unsigned num_targets;
- for (unsigned i = 0; i < (single_cb_enable ? 1 : subpass->color_count); ++i) {
+ for (unsigned i = 0; i < (blend->single_cb_enable ? 1 : subpass->color_count); ++i) {
unsigned cf;
if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
cf = V_028714_SPI_SHADER_ZERO;
} else {
struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
+ bool blend_enable =
+ blend->blend_enable_4bit & (0xfu << (i * 4));
cf = si_choose_spi_color_format(attachment->format,
- blend_enable & (1 << i),
- blend_need_alpha & (1 << i));
+ blend_enable,
+ blend->need_src_alpha & (1 << i));
}
col_format |= cf << (4 * i);
}
+ /* If the i-th target format is set, all previous target formats must
+ * be non-zero to avoid hangs.
+ */
+ num_targets = (util_last_bit(col_format) + 3) / 4;
+ for (unsigned i = 0; i < num_targets; i++) {
+ if (!(col_format & (0xf << (i * 4)))) {
+ col_format |= V_028714_SPI_SHADER_32_R << (i * 4);
+ }
+ }
+
blend->cb_shader_mask = ac_get_cb_shader_mask(col_format);
- if (blend_mrt0_is_dual_src)
+ if (blend->mrt0_is_dual_src)
col_format |= (col_format & 0xf) << 4;
blend->spi_shader_col_format = col_format;
}
return false;
}
+/*
+ * Ordered so that for each i,
+ * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
+ */
+const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS] = {
+ VK_FORMAT_R32_SFLOAT,
+ VK_FORMAT_R32G32_SFLOAT,
+ VK_FORMAT_R8G8B8A8_UNORM,
+ VK_FORMAT_R16G16B16A16_UNORM,
+ VK_FORMAT_R16G16B16A16_SNORM,
+ VK_FORMAT_R16G16B16A16_UINT,
+ VK_FORMAT_R16G16B16A16_SINT,
+ VK_FORMAT_R32G32B32A32_SFLOAT,
+ VK_FORMAT_R8G8B8A8_UINT,
+ VK_FORMAT_R8G8B8A8_SINT,
+ VK_FORMAT_A2R10G10B10_UINT_PACK32,
+ VK_FORMAT_A2R10G10B10_SINT_PACK32,
+};
+
unsigned radv_format_meta_fs_key(VkFormat format)
{
- unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
+ unsigned col_format = si_choose_spi_color_format(format, false, false);
+
+ assert(col_format != V_028714_SPI_SHADER_32_AR);
+ if (col_format >= V_028714_SPI_SHADER_32_AR)
+ --col_format; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
+
+ --col_format; /* Skip V_028714_SPI_SHADER_ZERO */
bool is_int8 = format_is_int8(format);
bool is_int10 = format_is_int10(format);
}
}
+static void
+radv_blend_check_commutativity(struct radv_blend_state *blend,
+ VkBlendOp op, VkBlendFactor src,
+ VkBlendFactor dst, unsigned chanmask)
+{
+ /* Src factor is allowed when it does not depend on Dst. */
+ static const uint32_t src_allowed =
+ (1u << VK_BLEND_FACTOR_ONE) |
+ (1u << VK_BLEND_FACTOR_SRC_COLOR) |
+ (1u << VK_BLEND_FACTOR_SRC_ALPHA) |
+ (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE) |
+ (1u << VK_BLEND_FACTOR_CONSTANT_COLOR) |
+ (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA) |
+ (1u << VK_BLEND_FACTOR_SRC1_COLOR) |
+ (1u << VK_BLEND_FACTOR_SRC1_ALPHA) |
+ (1u << VK_BLEND_FACTOR_ZERO) |
+ (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR) |
+ (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA) |
+ (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR) |
+ (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA) |
+ (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR) |
+ (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA);
+
+ if (dst == VK_BLEND_FACTOR_ONE &&
+ (src_allowed & (1u << src))) {
+ /* Addition is commutative, but floating point addition isn't
+ * associative: subtle changes can be introduced via different
+ * rounding. Be conservative, only enable for min and max.
+ */
+ if (op == VK_BLEND_OP_MAX || op == VK_BLEND_OP_MIN)
+ blend->commutative_4bit |= chanmask;
+ }
+}
+
static struct radv_blend_state
radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
const VkGraphicsPipelineCreateInfo *pCreateInfo,
const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
struct radv_blend_state blend = {0};
unsigned mode = V_028808_CB_NORMAL;
- uint32_t blend_enable = 0, blend_need_alpha = 0;
- bool blend_mrt0_is_dual_src = false;
int i;
- bool single_cb_enable = false;
if (!vkblend)
return blend;
if (extra && extra->custom_blend_mode) {
- single_cb_enable = true;
+ blend.single_cb_enable = true;
mode = extra->custom_blend_mode;
}
blend.cb_color_control = 0;
if (vkblend->logicOpEnable)
- blend.cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
+ blend.cb_color_control |= S_028808_ROP3(si_translate_blend_logic_op(vkblend->logicOp));
else
- blend.cb_color_control |= S_028808_ROP3(0xcc);
+ blend.cb_color_control |= S_028808_ROP3(V_028808_ROP3_COPY);
blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
continue;
blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
+ blend.cb_target_enabled_4bit |= 0xf << (4 * i);
if (!att->blendEnable) {
blend.cb_blend_control[i] = blend_cntl;
continue;
if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
if (i == 0)
- blend_mrt0_is_dual_src = true;
+ blend.mrt0_is_dual_src = true;
if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
srcRGB = VK_BLEND_FACTOR_ONE;
dstA = VK_BLEND_FACTOR_ONE;
}
+ radv_blend_check_commutativity(&blend, eqRGB, srcRGB, dstRGB,
+ 0x7 << (4 * i));
+ radv_blend_check_commutativity(&blend, eqA, srcA, dstA,
+ 0x8 << (4 * i));
+
/* Blending optimizations for RB+.
* These transformations don't change the behavior.
*
}
blend.cb_blend_control[i] = blend_cntl;
- blend_enable |= 1 << i;
+ blend.blend_enable_4bit |= 0xfu << (i * 4);
if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
- blend_need_alpha |= 1 << i;
+ blend.need_src_alpha |= 1 << i;
}
for (i = vkblend->attachmentCount; i < 8; i++) {
blend.cb_blend_control[i] = 0;
blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
}
- /* disable RB+ for now */
- if (pipeline->device->physical_device->has_rbplus)
- blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
+ if (pipeline->device->physical_device->has_rbplus) {
+ /* Disable RB+ blend optimizations for dual source blending. */
+ if (blend.mrt0_is_dual_src) {
+ for (i = 0; i < 8; i++) {
+ blend.sx_mrt_blend_opt[i] =
+ S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
+ S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
+ }
+ }
+
+ /* RB+ doesn't work with dual source blending, logic op and
+ * RESOLVE.
+ */
+ if (blend.mrt0_is_dual_src || vkblend->logicOpEnable ||
+ mode == V_028808_CB_RESOLVE)
+ blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
+ }
if (blend.cb_target_mask)
blend.cb_color_control |= S_028808_MODE(mode);
else
blend.cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
- radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo,
- blend_enable, blend_need_alpha, single_cb_enable, blend_mrt0_is_dual_src,
- &blend);
+ radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo, &blend);
return blend;
}
return ps_iter_samples;
}
+static bool
+radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
+{
+ return pCreateInfo->depthTestEnable &&
+ pCreateInfo->depthWriteEnable &&
+ pCreateInfo->depthCompareOp != VK_COMPARE_OP_NEVER;
+}
+
+static bool
+radv_writes_stencil(const VkStencilOpState *state)
+{
+ return state->writeMask &&
+ (state->failOp != VK_STENCIL_OP_KEEP ||
+ state->passOp != VK_STENCIL_OP_KEEP ||
+ state->depthFailOp != VK_STENCIL_OP_KEEP);
+}
+
+static bool
+radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
+{
+ return pCreateInfo->stencilTestEnable &&
+ (radv_writes_stencil(&pCreateInfo->front) ||
+ radv_writes_stencil(&pCreateInfo->back));
+}
+
+static bool
+radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
+{
+ return radv_is_depth_write_enabled(pCreateInfo) ||
+ radv_is_stencil_write_enabled(pCreateInfo);
+}
+
+static bool
+radv_order_invariant_stencil_op(VkStencilOp op)
+{
+ /* REPLACE is normally order invariant, except when the stencil
+ * reference value is written by the fragment shader. Tracking this
+ * interaction does not seem worth the effort, so be conservative.
+ */
+ return op != VK_STENCIL_OP_INCREMENT_AND_CLAMP &&
+ op != VK_STENCIL_OP_DECREMENT_AND_CLAMP &&
+ op != VK_STENCIL_OP_REPLACE;
+}
+
+static bool
+radv_order_invariant_stencil_state(const VkStencilOpState *state)
+{
+ /* Compute whether, assuming Z writes are disabled, this stencil state
+ * is order invariant in the sense that the set of passing fragments as
+ * well as the final stencil buffer result does not depend on the order
+ * of fragments.
+ */
+ return !state->writeMask ||
+ /* The following assumes that Z writes are disabled. */
+ (state->compareOp == VK_COMPARE_OP_ALWAYS &&
+ radv_order_invariant_stencil_op(state->passOp) &&
+ radv_order_invariant_stencil_op(state->depthFailOp)) ||
+ (state->compareOp == VK_COMPARE_OP_NEVER &&
+ radv_order_invariant_stencil_op(state->failOp));
+}
+
+static bool
+radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline,
+ struct radv_blend_state *blend,
+ const VkGraphicsPipelineCreateInfo *pCreateInfo)
+{
+ RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
+ struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
+ unsigned colormask = blend->cb_target_enabled_4bit;
+
+ if (!pipeline->device->physical_device->out_of_order_rast_allowed)
+ return false;
+
+ /* Be conservative if a logic operation is enabled with color buffers. */
+ if (colormask && pCreateInfo->pColorBlendState->logicOpEnable)
+ return false;
+
+ /* Default depth/stencil invariance when no attachment is bound. */
+ struct radv_dsa_order_invariance dsa_order_invariant = {
+ .zs = true, .pass_set = true
+ };
+
+ if (pCreateInfo->pDepthStencilState &&
+ subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
+ const VkPipelineDepthStencilStateCreateInfo *vkds =
+ pCreateInfo->pDepthStencilState;
+ struct radv_render_pass_attachment *attachment =
+ pass->attachments + subpass->depth_stencil_attachment.attachment;
+ bool has_stencil = vk_format_is_stencil(attachment->format);
+ struct radv_dsa_order_invariance order_invariance[2];
+ struct radv_shader_variant *ps =
+ pipeline->shaders[MESA_SHADER_FRAGMENT];
+
+ /* Compute depth/stencil order invariance in order to know if
+ * it's safe to enable out-of-order.
+ */
+ bool zfunc_is_ordered =
+ vkds->depthCompareOp == VK_COMPARE_OP_NEVER ||
+ vkds->depthCompareOp == VK_COMPARE_OP_LESS ||
+ vkds->depthCompareOp == VK_COMPARE_OP_LESS_OR_EQUAL ||
+ vkds->depthCompareOp == VK_COMPARE_OP_GREATER ||
+ vkds->depthCompareOp == VK_COMPARE_OP_GREATER_OR_EQUAL;
+
+ bool nozwrite_and_order_invariant_stencil =
+ !radv_is_ds_write_enabled(vkds) ||
+ (!radv_is_depth_write_enabled(vkds) &&
+ radv_order_invariant_stencil_state(&vkds->front) &&
+ radv_order_invariant_stencil_state(&vkds->back));
+
+ order_invariance[1].zs =
+ nozwrite_and_order_invariant_stencil ||
+ (!radv_is_stencil_write_enabled(vkds) &&
+ zfunc_is_ordered);
+ order_invariance[0].zs =
+ !radv_is_depth_write_enabled(vkds) || zfunc_is_ordered;
+
+ order_invariance[1].pass_set =
+ nozwrite_and_order_invariant_stencil ||
+ (!radv_is_stencil_write_enabled(vkds) &&
+ (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
+ vkds->depthCompareOp == VK_COMPARE_OP_NEVER));
+ order_invariance[0].pass_set =
+ !radv_is_depth_write_enabled(vkds) ||
+ (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
+ vkds->depthCompareOp == VK_COMPARE_OP_NEVER);
+
+ dsa_order_invariant = order_invariance[has_stencil];
+ if (!dsa_order_invariant.zs)
+ return false;
+
+ /* The set of PS invocations is always order invariant,
+ * except when early Z/S tests are requested.
+ */
+ if (ps &&
+ ps->info.info.ps.writes_memory &&
+ ps->info.fs.early_fragment_test &&
+ !dsa_order_invariant.pass_set)
+ return false;
+
+ /* Determine if out-of-order rasterization should be disabled
+ * when occlusion queries are used.
+ */
+ pipeline->graphics.disable_out_of_order_rast_for_occlusion =
+ !dsa_order_invariant.pass_set;
+ }
+
+ /* No color buffers are enabled for writing. */
+ if (!colormask)
+ return true;
+
+ unsigned blendmask = colormask & blend->blend_enable_4bit;
+
+ if (blendmask) {
+ /* Only commutative blending. */
+ if (blendmask & ~blend->commutative_4bit)
+ return false;
+
+ if (!dsa_order_invariant.pass_set)
+ return false;
+ }
+
+ if (colormask & ~blendmask)
+ return false;
+
+ return true;
+}
+
static void
radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
+ struct radv_blend_state *blend,
const VkGraphicsPipelineCreateInfo *pCreateInfo)
{
const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
struct radv_multisample_state *ms = &pipeline->graphics.ms;
unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
+ bool out_of_order_rast = false;
int ps_iter_samples = 1;
uint32_t mask = 0xffff;
ps_iter_samples = ms->num_samples;
}
+ const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
+ vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
+ if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
+ /* Out-of-order rasterization is explicitly enabled by the
+ * application.
+ */
+ out_of_order_rast = true;
+ } else {
+ /* Determine if the driver can enable out-of-order
+ * rasterization internally.
+ */
+ out_of_order_rast =
+ radv_pipeline_out_of_order_rast(pipeline, blend, pCreateInfo);
+ }
+
ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
ms->pa_sc_aa_config = 0;
ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
- S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
+ S_028804_INCOHERENT_EQAA_READS(1) |
+ S_028804_INTERPOLATE_COMP_Z(1) |
+ S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
ms->pa_sc_mode_cntl_1 =
S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
+ S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
+ S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
/* always 1: */
S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
}
- const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
- vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
- if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
- ms->pa_sc_mode_cntl_1 |= S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(1) |
- S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7);
- }
-
if (vkms && vkms->pSampleMask) {
mask = vkms->pSampleMask[0] & 0xffff;
}
unsigned num_se = device->physical_device->rad_info.max_se;
unsigned wave_size = 64;
unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
- unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
+ /* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16.
+ * On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
+ */
+ unsigned gs_vertex_reuse =
+ (device->physical_device->rad_info.chip_class >= VI ? 32 : 16) * num_se;
unsigned alignment = 256 * num_se;
/* The maximum size is 63.999 MB per SE. */
unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
gs->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in;
unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
- gs_info->gs.max_gsvs_emit_size * 1; // no streams in VK (gs->max_gs_stream + 1);
+ gs_info->gs.max_gsvs_emit_size;
min_esgs_ring_size = align(min_esgs_ring_size, alignment);
esgs_ring_size = align(esgs_ring_size, alignment);
static void si_multiwave_lds_size_workaround(struct radv_device *device,
unsigned *lds_size)
{
+ /* If tessellation is all offchip and on-chip GS isn't used, this
+ * workaround is not needed.
+ */
+ return;
+
/* SPI barrier management bug:
* Make sure we have at least 4k of LDS in use to avoid the bug.
* It applies to workgroup sizes of more than one wavefront.
}
struct radv_shader_variant *
-radv_get_vertex_shader(struct radv_pipeline *pipeline)
-{
- if (pipeline->shaders[MESA_SHADER_VERTEX])
- return pipeline->shaders[MESA_SHADER_VERTEX];
- if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
- return pipeline->shaders[MESA_SHADER_TESS_CTRL];
- return pipeline->shaders[MESA_SHADER_GEOMETRY];
-}
-
-static struct radv_shader_variant *
-radv_get_tess_eval_shader(struct radv_pipeline *pipeline)
-{
- if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
- return pipeline->shaders[MESA_SHADER_TESS_EVAL];
- return pipeline->shaders[MESA_SHADER_GEOMETRY];
+radv_get_shader(struct radv_pipeline *pipeline,
+ gl_shader_stage stage)
+{
+ if (stage == MESA_SHADER_VERTEX) {
+ if (pipeline->shaders[MESA_SHADER_VERTEX])
+ return pipeline->shaders[MESA_SHADER_VERTEX];
+ if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
+ return pipeline->shaders[MESA_SHADER_TESS_CTRL];
+ if (pipeline->shaders[MESA_SHADER_GEOMETRY])
+ return pipeline->shaders[MESA_SHADER_GEOMETRY];
+ } else if (stage == MESA_SHADER_TESS_EVAL) {
+ if (!radv_pipeline_has_tess(pipeline))
+ return NULL;
+ if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
+ return pipeline->shaders[MESA_SHADER_TESS_EVAL];
+ if (pipeline->shaders[MESA_SHADER_GEOMETRY])
+ return pipeline->shaders[MESA_SHADER_GEOMETRY];
+ }
+ return pipeline->shaders[stage];
}
static struct radv_tessellation_state
calculate_tess_state(struct radv_pipeline *pipeline,
const VkGraphicsPipelineCreateInfo *pCreateInfo)
{
- unsigned num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
- unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
- unsigned num_tcs_patch_outputs;
- unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
- unsigned input_patch_size, output_patch_size, output_patch0_offset;
- unsigned lds_size, hardware_lds_size;
- unsigned perpatch_output_offset;
+ unsigned num_tcs_input_cp;
+ unsigned num_tcs_output_cp;
+ unsigned lds_size;
unsigned num_patches;
struct radv_tessellation_state tess = {0};
- /* This calculates how shader inputs and outputs among VS, TCS, and TES
- * are laid out in LDS. */
- num_tcs_inputs = util_last_bit64(radv_get_vertex_shader(pipeline)->info.vs.outputs_written);
-
- num_tcs_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written); //tcs->outputs_written
+ num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
- num_tcs_patch_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.patch_outputs_written);
+ num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
- /* Ensure that we only need one wave per SIMD so we don't need to check
- * resource usage. Also ensures that the number of tcs in and out
- * vertices per threadgroup are at most 256.
- */
- input_vertex_size = num_tcs_inputs * 16;
- output_vertex_size = num_tcs_outputs * 16;
-
- input_patch_size = num_tcs_input_cp * input_vertex_size;
-
- pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
- output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
- /* Ensure that we only need one wave per SIMD so we don't need to check
- * resource usage. Also ensures that the number of tcs in and out
- * vertices per threadgroup are at most 256.
- */
- num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
-
- /* Make sure that the data fits in LDS. This assumes the shaders only
- * use LDS for the inputs and outputs.
- */
- hardware_lds_size = pipeline->device->physical_device->rad_info.chip_class >= CIK ? 65536 : 32768;
- num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
-
- /* Make sure the output data fits in the offchip buffer */
- num_patches = MIN2(num_patches,
- (pipeline->device->tess_offchip_block_dw_size * 4) /
- output_patch_size);
-
- /* Not necessary for correctness, but improves performance. The
- * specific value is taken from the proprietary driver.
- */
- num_patches = MIN2(num_patches, 40);
-
- /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
- if (pipeline->device->physical_device->rad_info.chip_class == SI) {
- unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
- num_patches = MIN2(num_patches, one_wave);
- }
-
- output_patch0_offset = input_patch_size * num_patches;
- perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
-
- lds_size = output_patch0_offset + output_patch_size * num_patches;
+ lds_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.lds_size;
if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
assert(lds_size <= 65536);
tess.lds_size = lds_size;
- tess.tcs_in_layout = (input_patch_size / 4) |
- ((input_vertex_size / 4) << 13);
- tess.tcs_out_layout = (output_patch_size / 4) |
- ((output_vertex_size / 4) << 13);
- tess.tcs_out_offsets = (output_patch0_offset / 16) |
- ((perpatch_output_offset / 16) << 16);
- tess.offchip_layout = (pervertex_output_patch_size * num_patches << 16) |
- num_patches;
-
tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
tess.num_patches = num_patches;
- struct radv_shader_variant *tes = radv_get_tess_eval_shader(pipeline);
+ struct radv_shader_variant *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL);
unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
switch (tes->info.tes.primitive_mode) {
ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
}
+ if (shader_count > 1) {
+ unsigned first = ordered_shaders[shader_count - 1]->info.stage;
+ unsigned last = ordered_shaders[0]->info.stage;
+
+ if (ordered_shaders[0]->info.stage == MESA_SHADER_FRAGMENT &&
+ ordered_shaders[1]->info.has_transform_feedback_varyings)
+ nir_link_xfb_varyings(ordered_shaders[1], ordered_shaders[0]);
+
+ for (int i = 0; i < shader_count; ++i) {
+ nir_variable_mode mask = 0;
+
+ if (ordered_shaders[i]->info.stage != first)
+ mask = mask | nir_var_shader_in;
+
+ if (ordered_shaders[i]->info.stage != last)
+ mask = mask | nir_var_shader_out;
+
+ nir_lower_io_to_scalar_early(ordered_shaders[i], mask);
+ radv_optimize_nir(ordered_shaders[i], false, false);
+ }
+ }
+
for (int i = 1; i < shader_count; ++i) {
nir_lower_io_arrays_to_elements(ordered_shaders[i],
ordered_shaders[i - 1]);
+ if (nir_link_constant_varyings(ordered_shaders[i],
+ ordered_shaders[i - 1]))
+ radv_optimize_nir(ordered_shaders[i - 1], false, false);
+
nir_remove_dead_variables(ordered_shaders[i],
nir_var_shader_out);
nir_remove_dead_variables(ordered_shaders[i - 1],
ac_lower_indirect_derefs(ordered_shaders[i],
pipeline->device->physical_device->rad_info.chip_class);
}
- radv_optimize_nir(ordered_shaders[i]);
+ radv_optimize_nir(ordered_shaders[i], false, false);
if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
ac_lower_indirect_derefs(ordered_shaders[i - 1],
pipeline->device->physical_device->rad_info.chip_class);
}
- radv_optimize_nir(ordered_shaders[i - 1]);
+ radv_optimize_nir(ordered_shaders[i - 1], false, false);
}
}
}
{
const VkPipelineVertexInputStateCreateInfo *input_state =
pCreateInfo->pVertexInputState;
+ const VkPipelineVertexInputDivisorStateCreateInfoEXT *divisor_state =
+ vk_find_struct_const(input_state->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
+
struct radv_pipeline_key key;
memset(&key, 0, sizeof(key));
+ if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
+ key.optimisations_disabled = 1;
+
key.has_multiview_view_index = has_view_index;
uint32_t binding_input_rate = 0;
+ uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
- if (input_state->pVertexBindingDescriptions[i].inputRate)
- binding_input_rate |= 1u << input_state->pVertexBindingDescriptions[i].binding;
+ if (input_state->pVertexBindingDescriptions[i].inputRate) {
+ unsigned binding = input_state->pVertexBindingDescriptions[i].binding;
+ binding_input_rate |= 1u << binding;
+ instance_rate_divisors[binding] = 1;
+ }
+ }
+ if (divisor_state) {
+ for (unsigned i = 0; i < divisor_state->vertexBindingDivisorCount; ++i) {
+ instance_rate_divisors[divisor_state->pVertexBindingDivisors[i].binding] =
+ divisor_state->pVertexBindingDivisors[i].divisor;
+ }
}
for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
- unsigned binding;
- binding = input_state->pVertexAttributeDescriptions[i].binding;
- if (binding_input_rate & (1u << binding))
- key.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location;
+ unsigned location = input_state->pVertexAttributeDescriptions[i].location;
+ unsigned binding = input_state->pVertexAttributeDescriptions[i].binding;
+ if (binding_input_rate & (1u << binding)) {
+ key.instance_rate_inputs |= 1u << location;
+ key.instance_rate_divisors[location] = instance_rate_divisors[binding];
+ }
+
+ if (pipeline->device->physical_device->rad_info.chip_class <= VI &&
+ pipeline->device->physical_device->rad_info.family != CHIP_STONEY) {
+ VkFormat format = input_state->pVertexAttributeDescriptions[i].format;
+ uint64_t adjust;
+ switch(format) {
+ case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
+ case VK_FORMAT_A2B10G10R10_SNORM_PACK32:
+ adjust = RADV_ALPHA_ADJUST_SNORM;
+ break;
+ case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
+ case VK_FORMAT_A2B10G10R10_SSCALED_PACK32:
+ adjust = RADV_ALPHA_ADJUST_SSCALED;
+ break;
+ case VK_FORMAT_A2R10G10B10_SINT_PACK32:
+ case VK_FORMAT_A2B10G10R10_SINT_PACK32:
+ adjust = RADV_ALPHA_ADJUST_SINT;
+ break;
+ default:
+ adjust = 0;
+ break;
+ }
+ key.vertex_alpha_adjust |= adjust << (2 * location);
+ }
}
if (pCreateInfo->pTessellationState)
pCreateInfo->pMultisampleState->rasterizationSamples > 1) {
uint32_t num_samples = pCreateInfo->pMultisampleState->rasterizationSamples;
uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo->pMultisampleState);
- key.multisample = true;
- key.log2_num_samples = util_logbase2(num_samples);
+ key.num_samples = num_samples;
key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
}
}
static void
-radv_fill_shader_keys(struct ac_shader_variant_key *keys,
+radv_fill_shader_keys(struct radv_shader_variant_key *keys,
const struct radv_pipeline_key *key,
nir_shader **nir)
{
keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
+ keys[MESA_SHADER_VERTEX].vs.alpha_adjust = key->vertex_alpha_adjust;
+ for (unsigned i = 0; i < MAX_VERTEX_ATTRIBS; ++i)
+ keys[MESA_SHADER_VERTEX].vs.instance_rate_divisors[i] = key->instance_rate_divisors[i];
if (nir[MESA_SHADER_TESS_CTRL]) {
keys[MESA_SHADER_VERTEX].vs.as_ls = true;
+ keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = 0;
keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
for(int i = 0; i < MESA_SHADER_STAGES; ++i)
keys[i].has_multiview_view_index = key->has_multiview_view_index;
- keys[MESA_SHADER_FRAGMENT].fs.multisample = key->multisample;
keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
- keys[MESA_SHADER_FRAGMENT].fs.log2_num_samples = key->log2_num_samples;
+ keys[MESA_SHADER_FRAGMENT].fs.num_samples = key->num_samples;
}
static void
void radv_create_shaders(struct radv_pipeline *pipeline,
struct radv_device *device,
struct radv_pipeline_cache *cache,
- struct radv_pipeline_key key,
- const VkPipelineShaderStageCreateInfo **pStages)
+ const struct radv_pipeline_key *key,
+ const VkPipelineShaderStageCreateInfo **pStages,
+ const VkPipelineCreateFlags flags)
{
struct radv_shader_module fs_m = {0};
struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
nir_shader *nir[MESA_SHADER_STAGES] = {0};
void *codes[MESA_SHADER_STAGES] = {0};
unsigned code_sizes[MESA_SHADER_STAGES] = {0};
- struct ac_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{0}}}};
+ struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{0}}}};
unsigned char hash[20], gs_copy_hash[20];
for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
_mesa_sha1_compute(modules[i]->nir->info.name,
strlen(modules[i]->nir->info.name),
modules[i]->sha1);
+
+ pipeline->active_stages |= mesa_to_vk_shader_stage(i);
}
}
- radv_hash_shaders(hash, pStages, pipeline->layout, &key, get_hash_flags(device));
+ radv_hash_shaders(hash, pStages, pipeline->layout, key, get_hash_flags(device));
memcpy(gs_copy_hash, hash, 20);
gs_copy_hash[0] ^= 1;
if (radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders) &&
(!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
- for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
- if (pipeline->shaders[i])
- pipeline->active_stages |= mesa_to_vk_shader_stage(i);
- }
return;
}
modules[MESA_SHADER_FRAGMENT] = &fs_m;
}
- /* Determine first and last stage. */
- unsigned first = MESA_SHADER_STAGES;
- unsigned last = 0;
- for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
- if (!pStages[i])
- continue;
- if (first == MESA_SHADER_STAGES)
- first = i;
- last = i;
- }
-
for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
const VkPipelineShaderStageCreateInfo *stage = pStages[i];
nir[i] = radv_shader_compile_to_nir(device, modules[i],
stage ? stage->pName : "main", i,
- stage ? stage->pSpecializationInfo : NULL);
- pipeline->active_stages |= mesa_to_vk_shader_stage(i);
+ stage ? stage->pSpecializationInfo : NULL,
+ flags);
/* We don't want to alter meta shaders IR directly so clone it
* first.
if (nir[i]->info.name) {
nir[i] = nir_shader_clone(NULL, nir[i]);
}
-
- if (first != last) {
- nir_variable_mode mask = 0;
-
- if (i != first)
- mask = mask | nir_var_shader_in;
-
- if (i != last)
- mask = mask | nir_var_shader_out;
-
- nir_lower_io_to_scalar_early(nir[i], mask);
- radv_optimize_nir(nir[i]);
- }
}
if (nir[MESA_SHADER_TESS_CTRL]) {
- nir_lower_tes_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out);
+ nir_lower_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out, NULL);
merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
}
- radv_link_shaders(pipeline, nir);
+ if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
+ radv_link_shaders(pipeline, nir);
for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
- if (modules[i] && radv_can_dump_shader(device, modules[i]))
+ if (radv_can_dump_shader(device, modules[i], false))
nir_print_shader(nir[i], stderr);
}
- radv_fill_shader_keys(keys, &key, nir);
+ radv_fill_shader_keys(keys, key, nir);
if (nir[MESA_SHADER_FRAGMENT]) {
if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
/* TODO: These are no longer used as keys we should refactor this */
keys[MESA_SHADER_VERTEX].vs.export_prim_id =
pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input;
+ keys[MESA_SHADER_VERTEX].vs.export_layer_id =
+ pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.layer_input;
keys[MESA_SHADER_TESS_EVAL].tes.export_prim_id =
pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input;
+ keys[MESA_SHADER_TESS_EVAL].tes.export_layer_id =
+ pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.layer_input;
}
if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
- struct ac_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
+ struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_create(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
pipeline->layout,
&code_sizes[MESA_SHADER_TESS_CTRL]);
}
modules[MESA_SHADER_VERTEX] = NULL;
+ keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
+ keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.outputs_written);
}
if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
if(modules[i] && !pipeline->shaders[i]) {
+ if (i == MESA_SHADER_TESS_CTRL) {
+ keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.ls_outputs_written);
+ }
+ if (i == MESA_SHADER_TESS_EVAL) {
+ keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
+ keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.outputs_written);
+ }
pipeline->shaders[i] = radv_shader_variant_create(device, modules[i], &nir[i], 1,
pipeline->layout,
keys + i, &codes[i],
for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
free(codes[i]);
- if (modules[i]) {
+ if (nir[i]) {
if (!pipeline->device->keep_shader_info)
ralloc_free(nir[i]);
pipeline->device->physical_device->rad_info.max_se);
unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
- unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_mode_cntl_1);
+ unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
unsigned effective_samples = total_samples;
unsigned color_bytes_per_pixel = 0;
}
const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
- while(color_entry->bpp <= color_bytes_per_pixel)
+ while(color_entry[1].bpp <= color_bytes_per_pixel)
++color_entry;
extent = color_entry->extent;
unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
- while(ds_entry->bpp <= ds_bytes_per_pixel)
+ while(ds_entry[1].bpp <= ds_bytes_per_pixel)
++ds_entry;
extent.width = MIN2(extent.width, ds_entry->extent.width);
}
static void
-radv_pipeline_generate_binning_state(struct radeon_winsys_cs *cs,
+radv_pipeline_generate_binning_state(struct radeon_cmdbuf *cs,
struct radv_pipeline *pipeline,
const VkGraphicsPipelineCreateInfo *pCreateInfo)
{
switch (pipeline->device->physical_device->rad_info.family) {
case CHIP_VEGA10:
+ case CHIP_VEGA12:
+ case CHIP_VEGA20:
context_states_per_bin = 1;
persistent_states_per_bin = 1;
fpovs_per_batch = 63;
break;
case CHIP_RAVEN:
+ case CHIP_RAVEN2:
context_states_per_bin = 6;
persistent_states_per_bin = 32;
fpovs_per_batch = 63;
static void
-radv_pipeline_generate_depth_stencil_state(struct radeon_winsys_cs *cs,
+radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *cs,
struct radv_pipeline *pipeline,
const VkGraphicsPipelineCreateInfo *pCreateInfo,
const struct radv_graphics_pipeline_create_info *extra)
const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
+ struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
struct radv_render_pass_attachment *attachment = NULL;
uint32_t db_depth_control = 0, db_stencil_control = 0;
uint32_t db_render_control = 0, db_render_override2 = 0;
+ uint32_t db_render_override = 0;
if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED)
attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
}
+ db_render_override |= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
+ S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
+
+ if (pipeline->device->enabled_extensions.EXT_depth_range_unrestricted &&
+ !pCreateInfo->pRasterizationState->depthClampEnable &&
+ ps->info.info.ps.writes_z) {
+ /* From VK_EXT_depth_range_unrestricted spec:
+ *
+ * "The behavior described in Primitive Clipping still applies.
+ * If depth clamping is disabled the depth values are still
+ * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
+ * depth clamping is enabled the above equation is ignored and
+ * the depth values are instead clamped to the VkViewport
+ * minDepth and maxDepth values, which in the case of this
+ * extension can be outside of the 0.0 to 1.0 range."
+ */
+ db_render_override |= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
+ }
+
radeon_set_context_reg(cs, R_028800_DB_DEPTH_CONTROL, db_depth_control);
radeon_set_context_reg(cs, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
radeon_set_context_reg(cs, R_028000_DB_RENDER_CONTROL, db_render_control);
+ radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2);
}
static void
-radv_pipeline_generate_blend_state(struct radeon_winsys_cs *cs,
+radv_pipeline_generate_blend_state(struct radeon_cmdbuf *cs,
struct radv_pipeline *pipeline,
const struct radv_blend_state *blend)
{
radeon_set_context_reg_seq(cs, R_028760_SX_MRT0_BLEND_OPT, 8);
radeon_emit_array(cs, blend->sx_mrt_blend_opt, 8);
-
- radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
- radeon_emit(cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
- radeon_emit(cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
- radeon_emit(cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
}
radeon_set_context_reg(cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
radeon_set_context_reg(cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
+
+ pipeline->graphics.col_format = blend->spi_shader_col_format;
+ pipeline->graphics.cb_target_mask = blend->cb_target_mask;
}
+static const VkConservativeRasterizationModeEXT
+radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo *pCreateInfo)
+{
+ const VkPipelineRasterizationConservativeStateCreateInfoEXT *conservative_raster =
+ vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT);
+
+ if (!conservative_raster)
+ return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT;
+ return conservative_raster->conservativeRasterizationMode;
+}
static void
-radv_pipeline_generate_raster_state(struct radeon_winsys_cs *cs,
+radv_pipeline_generate_raster_state(struct radeon_cmdbuf *cs,
+ struct radv_pipeline *pipeline,
const VkGraphicsPipelineCreateInfo *pCreateInfo)
{
const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
+ const VkConservativeRasterizationModeEXT mode =
+ radv_get_conservative_raster_mode(vkraster);
+ uint32_t pa_sc_conservative_rast = S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
- S_028810_PS_UCP_MODE(3) |
S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0));
+
+ /* Conservative rasterization. */
+ if (mode != VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT) {
+ struct radv_multisample_state *ms = &pipeline->graphics.ms;
+
+ ms->pa_sc_aa_config |= S_028BE0_AA_MASK_CENTROID_DTMN(1);
+ ms->db_eqaa |= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
+ S_028804_OVERRASTERIZATION_AMOUNT(4);
+
+ pa_sc_conservative_rast = S_028C4C_PREZ_AA_MASK_ENABLE(1) |
+ S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
+ S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
+
+ if (mode == VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT) {
+ pa_sc_conservative_rast |=
+ S_028C4C_OVER_RAST_ENABLE(1) |
+ S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
+ S_028C4C_UNDER_RAST_ENABLE(0) |
+ S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
+ S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
+ } else {
+ assert(mode == VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT);
+ pa_sc_conservative_rast |=
+ S_028C4C_OVER_RAST_ENABLE(0) |
+ S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
+ S_028C4C_UNDER_RAST_ENABLE(1) |
+ S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
+ S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
+ }
+ }
+
+ radeon_set_context_reg(cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
+ pa_sc_conservative_rast);
}
static void
-radv_pipeline_generate_multisample_state(struct radeon_winsys_cs *cs,
+radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *cs,
struct radv_pipeline *pipeline)
{
struct radv_multisample_state *ms = &pipeline->graphics.ms;
radeon_set_context_reg(cs, R_028804_DB_EQAA, ms->db_eqaa);
radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
- if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
- uint32_t offset;
- struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
- uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_FRAGMENT];
- if (loc->sgpr_idx == -1)
- return;
- assert(loc->num_sgprs == 1);
- assert(!loc->indirect);
- switch (pipeline->graphics.ms.num_samples) {
- default:
- offset = 0;
- break;
- case 2:
- offset = 1;
- break;
- case 4:
- offset = 3;
- break;
- case 8:
- offset = 7;
- break;
- case 16:
- offset = 15;
- break;
- }
-
- radeon_set_sh_reg(cs, base_reg + loc->sgpr_idx * 4, offset);
- }
+ /* The exclusion bits can be set to improve rasterization efficiency
+ * if no sample lies on the pixel boundary (-8 sample offset). It's
+ * currently always TRUE because the driver doesn't support 16 samples.
+ */
+ bool exclusion = pipeline->device->physical_device->rad_info.chip_class >= CIK;
+ radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL,
+ S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
+ S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
}
static void
-radv_pipeline_generate_vgt_gs_mode(struct radeon_winsys_cs *cs,
+radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *cs,
const struct radv_pipeline *pipeline)
{
const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
}
static void
-radv_pipeline_generate_hw_vs(struct radeon_winsys_cs *cs,
+radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *cs,
struct radv_pipeline *pipeline,
struct radv_shader_variant *shader)
{
radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
radeon_emit(cs, va >> 8);
- radeon_emit(cs, va >> 40);
+ radeon_emit(cs, S_00B124_MEM_BASE(va >> 40));
radeon_emit(cs, shader->rsrc1);
radeon_emit(cs, shader->rsrc2);
}
static void
-radv_pipeline_generate_hw_es(struct radeon_winsys_cs *cs,
+radv_pipeline_generate_hw_es(struct radeon_cmdbuf *cs,
struct radv_pipeline *pipeline,
struct radv_shader_variant *shader)
{
radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
radeon_emit(cs, va >> 8);
- radeon_emit(cs, va >> 40);
+ radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
radeon_emit(cs, shader->rsrc1);
radeon_emit(cs, shader->rsrc2);
}
static void
-radv_pipeline_generate_hw_ls(struct radeon_winsys_cs *cs,
+radv_pipeline_generate_hw_ls(struct radeon_cmdbuf *cs,
struct radv_pipeline *pipeline,
struct radv_shader_variant *shader,
const struct radv_tessellation_state *tess)
radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
radeon_emit(cs, va >> 8);
- radeon_emit(cs, va >> 40);
+ radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
rsrc2 |= S_00B52C_LDS_SIZE(tess->lds_size);
if (pipeline->device->physical_device->rad_info.chip_class == CIK &&
}
static void
-radv_pipeline_generate_hw_hs(struct radeon_winsys_cs *cs,
+radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs,
struct radv_pipeline *pipeline,
struct radv_shader_variant *shader,
const struct radv_tessellation_state *tess)
if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
radeon_emit(cs, va >> 8);
- radeon_emit(cs, va >> 40);
+ radeon_emit(cs, S_00B414_MEM_BASE(va >> 40));
radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
radeon_emit(cs, shader->rsrc1);
} else {
radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
radeon_emit(cs, va >> 8);
- radeon_emit(cs, va >> 40);
+ radeon_emit(cs, S_00B424_MEM_BASE(va >> 40));
radeon_emit(cs, shader->rsrc1);
radeon_emit(cs, shader->rsrc2);
}
}
static void
-radv_pipeline_generate_vertex_shader(struct radeon_winsys_cs *cs,
+radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf *cs,
struct radv_pipeline *pipeline,
const struct radv_tessellation_state *tess)
{
}
static void
-radv_pipeline_generate_tess_shaders(struct radeon_winsys_cs *cs,
+radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *cs,
struct radv_pipeline *pipeline,
const struct radv_tessellation_state *tess)
{
else
radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
tess->ls_hs_config);
-
- struct radv_userdata_info *loc;
-
- loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
- if (loc->sgpr_idx != -1) {
- uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_CTRL];
- assert(loc->num_sgprs == 4);
- assert(!loc->indirect);
- radeon_set_sh_reg_seq(cs, base_reg + loc->sgpr_idx * 4, 4);
- radeon_emit(cs, tess->offchip_layout);
- radeon_emit(cs, tess->tcs_out_offsets);
- radeon_emit(cs, tess->tcs_out_layout);
- radeon_emit(cs, tess->tcs_in_layout);
- }
-
- loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
- if (loc->sgpr_idx != -1) {
- uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_EVAL];
- assert(loc->num_sgprs == 1);
- assert(!loc->indirect);
-
- radeon_set_sh_reg(cs, base_reg + loc->sgpr_idx * 4,
- tess->offchip_layout);
- }
-
- loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
- if (loc->sgpr_idx != -1) {
- uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_VERTEX];
- assert(loc->num_sgprs == 1);
- assert(!loc->indirect);
-
- radeon_set_sh_reg(cs, base_reg + loc->sgpr_idx * 4,
- tess->tcs_in_layout);
- }
}
static void
-radv_pipeline_generate_geometry_shader(struct radeon_winsys_cs *cs,
+radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *cs,
struct radv_pipeline *pipeline,
const struct radv_gs_state *gs_state)
{
struct radv_shader_variant *gs;
+ unsigned gs_max_out_vertices;
+ uint8_t *num_components;
+ uint8_t max_stream;
+ unsigned offset;
uint64_t va;
gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
if (!gs)
return;
- uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
+ gs_max_out_vertices = gs->info.gs.vertices_out;
+ max_stream = gs->info.info.gs.max_stream;
+ num_components = gs->info.info.gs.num_stream_output_components;
- radeon_set_context_reg_seq(cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
- radeon_emit(cs, gsvs_itemsize);
- radeon_emit(cs, gsvs_itemsize);
- radeon_emit(cs, gsvs_itemsize);
+ offset = num_components[0] * gs_max_out_vertices;
- radeon_set_context_reg(cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
+ radeon_set_context_reg_seq(cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
+ radeon_emit(cs, offset);
+ if (max_stream >= 1)
+ offset += num_components[1] * gs_max_out_vertices;
+ radeon_emit(cs, offset);
+ if (max_stream >= 2)
+ offset += num_components[2] * gs_max_out_vertices;
+ radeon_emit(cs, offset);
+ if (max_stream >= 3)
+ offset += num_components[3] * gs_max_out_vertices;
+ radeon_set_context_reg(cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
radeon_set_context_reg(cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
- uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
radeon_set_context_reg_seq(cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
- radeon_emit(cs, gs_vert_itemsize >> 2);
- radeon_emit(cs, 0);
- radeon_emit(cs, 0);
- radeon_emit(cs, 0);
+ radeon_emit(cs, num_components[0]);
+ radeon_emit(cs, (max_stream >= 1) ? num_components[1] : 0);
+ radeon_emit(cs, (max_stream >= 2) ? num_components[2] : 0);
+ radeon_emit(cs, (max_stream >= 3) ? num_components[3] : 0);
uint32_t gs_num_invocations = gs->info.gs.invocations;
radeon_set_context_reg(cs, R_028B90_VGT_GS_INSTANCE_CNT,
if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
radeon_emit(cs, va >> 8);
- radeon_emit(cs, va >> 40);
+ radeon_emit(cs, S_00B214_MEM_BASE(va >> 40));
radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
radeon_emit(cs, gs->rsrc1);
} else {
radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
radeon_emit(cs, va >> 8);
- radeon_emit(cs, va >> 40);
+ radeon_emit(cs, S_00B224_MEM_BASE(va >> 40));
radeon_emit(cs, gs->rsrc1);
radeon_emit(cs, gs->rsrc2);
}
radv_pipeline_generate_hw_vs(cs, pipeline, pipeline->gs_copy_shader);
-
- struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_GEOMETRY,
- AC_UD_GS_VS_RING_STRIDE_ENTRIES);
- if (loc->sgpr_idx != -1) {
- uint32_t stride = gs->info.gs.max_gsvs_emit_size;
- uint32_t num_entries = 64;
- bool is_vi = pipeline->device->physical_device->rad_info.chip_class >= VI;
-
- if (is_vi)
- num_entries *= stride;
-
- stride = S_008F04_STRIDE(stride);
- radeon_set_sh_reg_seq(cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
- radeon_emit(cs, stride);
- radeon_emit(cs, num_entries);
- }
}
static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade)
}
static void
-radv_pipeline_generate_ps_inputs(struct radeon_winsys_cs *cs,
+radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *cs,
struct radv_pipeline *pipeline)
{
struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
ps_offset++;
}
+ if (ps->info.info.ps.num_input_clips_culls) {
+ unsigned vs_offset;
+
+ vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0];
+ if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
+ ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false);
+ ++ps_offset;
+ }
+
+ vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1];
+ if (vs_offset != AC_EXP_PARAM_UNDEFINED &&
+ ps->info.info.ps.num_input_clips_culls > 4) {
+ ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false);
+ ++ps_offset;
+ }
+ }
+
for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
unsigned vs_offset;
bool flat_shade;
static uint32_t
radv_compute_db_shader_control(const struct radv_device *device,
+ const struct radv_pipeline *pipeline,
const struct radv_shader_variant *ps)
{
+ const struct radv_multisample_state *ms = &pipeline->graphics.ms;
unsigned z_order;
if (ps->info.fs.early_fragment_test || !ps->info.info.ps.writes_memory)
z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
else
z_order = V_02880C_LATE_Z;
+ bool disable_rbplus = device->physical_device->has_rbplus &&
+ !device->physical_device->rbplus_allowed;
+
+ /* Do not enable the gl_SampleMask fragment shader output if MSAA is
+ * disabled.
+ */
+ bool mask_export_enable = ms->num_samples > 1 &&
+ ps->info.info.ps.writes_sample_mask;
+
return S_02880C_Z_EXPORT_ENABLE(ps->info.info.ps.writes_z) |
S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.info.ps.writes_stencil) |
S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
- S_02880C_MASK_EXPORT_ENABLE(ps->info.info.ps.writes_sample_mask) |
+ S_02880C_MASK_EXPORT_ENABLE(mask_export_enable) |
S_02880C_Z_ORDER(z_order) |
S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
S_02880C_EXEC_ON_HIER_FAIL(ps->info.info.ps.writes_memory) |
S_02880C_EXEC_ON_NOOP(ps->info.info.ps.writes_memory) |
- S_02880C_DUAL_QUAD_DISABLE(!!device->physical_device->has_rbplus);
+ S_02880C_DUAL_QUAD_DISABLE(disable_rbplus);
}
static void
-radv_pipeline_generate_fragment_shader(struct radeon_winsys_cs *cs,
+radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf *cs,
struct radv_pipeline *pipeline)
{
struct radv_shader_variant *ps;
radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
radeon_emit(cs, va >> 8);
- radeon_emit(cs, va >> 40);
+ radeon_emit(cs, S_00B024_MEM_BASE(va >> 40));
radeon_emit(cs, ps->rsrc1);
radeon_emit(cs, ps->rsrc2);
radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
- radv_compute_db_shader_control(pipeline->device, ps));
+ radv_compute_db_shader_control(pipeline->device,
+ pipeline, ps));
radeon_set_context_reg(cs, R_0286CC_SPI_PS_INPUT_ENA,
ps->config.spi_ps_input_ena);
}
static void
-radv_pipeline_generate_vgt_vertex_reuse(struct radeon_winsys_cs *cs,
+radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf *cs,
struct radv_pipeline *pipeline)
{
if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10)
unsigned vtx_reuse_depth = 30;
if (radv_pipeline_has_tess(pipeline) &&
- radv_get_tess_eval_shader(pipeline)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
+ radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
vtx_reuse_depth = 14;
}
radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
radv_pipeline_generate_depth_stencil_state(&pipeline->cs, pipeline, pCreateInfo, extra);
radv_pipeline_generate_blend_state(&pipeline->cs, pipeline, blend);
- radv_pipeline_generate_raster_state(&pipeline->cs, pCreateInfo);
+ radv_pipeline_generate_raster_state(&pipeline->cs, pipeline, pCreateInfo);
radv_pipeline_generate_multisample_state(&pipeline->cs, pipeline);
radv_pipeline_generate_vgt_gs_mode(&pipeline->cs, pipeline);
radv_pipeline_generate_vertex_shader(&pipeline->cs, pipeline, tess);
else
ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */
- ia_multi_vgt_param.partial_es_wave = false;
- if (pipeline->device->has_distributed_tess) {
- if (radv_pipeline_has_gs(pipeline)) {
- if (device->physical_device->rad_info.chip_class <= VI)
- ia_multi_vgt_param.partial_es_wave = true;
- }
- }
/* GS requirement. */
- if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
- ia_multi_vgt_param.partial_es_wave = true;
+ ia_multi_vgt_param.partial_es_wave = false;
+ if (radv_pipeline_has_gs(pipeline) && device->physical_device->rad_info.chip_class <= VI)
+ if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
+ ia_multi_vgt_param.partial_es_wave = true;
ia_multi_vgt_param.wd_switch_on_eop = false;
if (device->physical_device->rad_info.chip_class >= CIK) {
(pipeline->graphics.prim_restart_enable &&
(device->physical_device->rad_info.family < CHIP_POLARIS10 ||
(prim != V_008958_DI_PT_POINTLIST &&
- prim != V_008958_DI_PT_LINESTRIP &&
- prim != V_008958_DI_PT_TRISTRIP))))
+ prim != V_008958_DI_PT_LINESTRIP))))
ia_multi_vgt_param.wd_switch_on_eop = true;
}
if (radv_pipeline_has_tess(pipeline)) {
/* SWITCH_ON_EOI must be set if PrimID is used. */
if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.uses_prim_id ||
- radv_get_tess_eval_shader(pipeline)->info.info.uses_prim_id)
+ radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.info.uses_prim_id)
ia_multi_vgt_param.ia_switch_on_eoi = true;
}
/* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
if (device->has_distributed_tess) {
if (radv_pipeline_has_gs(pipeline)) {
+ if (device->physical_device->rad_info.chip_class <= VI)
+ ia_multi_vgt_param.partial_es_wave = true;
+
if (device->physical_device->rad_info.family == CHIP_TONGA ||
device->physical_device->rad_info.family == CHIP_FIJI ||
device->physical_device->rad_info.family == CHIP_POLARIS10 ||
device->physical_device->rad_info.family == CHIP_POLARIS11 ||
- device->physical_device->rad_info.family == CHIP_POLARIS12)
+ device->physical_device->rad_info.family == CHIP_POLARIS12 ||
+ device->physical_device->rad_info.family == CHIP_VEGAM)
ia_multi_vgt_param.partial_vs_wave = true;
} else {
ia_multi_vgt_param.partial_vs_wave = true;
}
}
+ /* Workaround for a VGT hang when strip primitive types are used with
+ * primitive restart.
+ */
+ if (pipeline->graphics.prim_restart_enable &&
+ (prim == V_008958_DI_PT_LINESTRIP ||
+ prim == V_008958_DI_PT_TRISTRIP ||
+ prim == V_008958_DI_PT_LINESTRIP_ADJ ||
+ prim == V_008958_DI_PT_TRISTRIP_ADJ)) {
+ ia_multi_vgt_param.partial_vs_wave = true;
+ }
+
ia_multi_vgt_param.base =
S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
/* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
}
}
+static struct radv_shader_variant *
+radv_pipeline_get_streamout_shader(struct radv_pipeline *pipeline)
+{
+ int i;
+
+ for (i = MESA_SHADER_GEOMETRY; i >= MESA_SHADER_VERTEX; i--) {
+ struct radv_shader_variant *shader =
+ radv_get_shader(pipeline, i);
+
+ if (shader && shader->info.info.so.num_outputs > 0)
+ return shader;
+ }
+
+ return NULL;
+}
+
static VkResult
radv_pipeline_init(struct radv_pipeline *pipeline,
struct radv_device *device,
pStages[stage] = &pCreateInfo->pStages[i];
}
- radv_create_shaders(pipeline, device, cache,
- radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend, has_view_index),
- pStages);
+ struct radv_pipeline_key key = radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend, has_view_index);
+ radv_create_shaders(pipeline, device, cache, &key, pStages, pCreateInfo->flags);
pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
- radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
+ radv_pipeline_init_multisample_state(pipeline, &blend, pCreateInfo);
uint32_t gs_out;
uint32_t prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
if (loc->sgpr_idx != -1) {
pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
- if (radv_get_vertex_shader(pipeline)->info.info.vs.needs_draw_id)
+ if (radv_get_shader(pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id)
pipeline->graphics.vtx_emit_num = 3;
else
pipeline->graphics.vtx_emit_num = 2;
}
+ /* Find the last vertex shader stage that eventually uses streamout. */
+ pipeline->streamout_shader = radv_pipeline_get_streamout_shader(pipeline);
+
result = radv_pipeline_scratch_init(device, pipeline);
radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend, &tess, &gs, prim, gs_out);
pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
if (pipeline == NULL)
- return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
+ return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
result = radv_pipeline_init(pipeline, device, cache,
pCreateInfo, extra, pAllocator);
radeon_set_sh_reg_seq(&pipeline->cs, R_00B830_COMPUTE_PGM_LO, 2);
radeon_emit(&pipeline->cs, va >> 8);
- radeon_emit(&pipeline->cs, va >> 40);
+ radeon_emit(&pipeline->cs, S_00B834_DATA(va >> 40));
radeon_set_sh_reg_seq(&pipeline->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
radeon_emit(&pipeline->cs, compute_shader->rsrc1);
pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
if (pipeline == NULL)
- return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
+ return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
pipeline->device = device;
pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
assert(pipeline->layout);
pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
- radv_create_shaders(pipeline, device, cache, (struct radv_pipeline_key) {0}, pStages);
+ radv_create_shaders(pipeline, device, cache, &(struct radv_pipeline_key) {0}, pStages, pCreateInfo->flags);
pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
projects / mesa.git / blobdiff