return hash_flags;
}
-static struct radv_shader_variant *
-radv_pipeline_compile(struct radv_pipeline *pipeline,
- struct radv_pipeline_cache *cache,
- struct radv_shader_module *module,
- const char *entrypoint,
- gl_shader_stage stage,
- const VkSpecializationInfo *spec_info,
- struct radv_pipeline_layout *layout,
- const struct ac_shader_variant_key *key)
-{
- unsigned char sha1[20];
- unsigned char gs_copy_sha1[20];
- struct radv_shader_variant *variant;
- nir_shader *nir;
- void *code = NULL;
- unsigned code_size = 0;
- unsigned hash_flags = get_hash_flags(pipeline->device);
- if (module->nir)
- _mesa_sha1_compute(module->nir->info.name,
- strlen(module->nir->info.name),
- module->sha1);
-
- radv_hash_shader(sha1, module, entrypoint, spec_info, layout, key, hash_flags);
- if (stage == MESA_SHADER_GEOMETRY)
- radv_hash_shader(gs_copy_sha1, module, entrypoint, spec_info,
- layout, key, hash_flags | RADV_HASH_SHADER_IS_GEOM_COPY_SHADER);
-
- variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
- cache,
- sha1);
-
- if (stage == MESA_SHADER_GEOMETRY) {
- pipeline->gs_copy_shader =
- radv_create_shader_variant_from_pipeline_cache(
- pipeline->device,
- cache,
- gs_copy_sha1);
- }
-
- if (variant &&
- (stage != MESA_SHADER_GEOMETRY || pipeline->gs_copy_shader))
- return variant;
-
- nir = radv_shader_compile_to_nir(pipeline->device,
- module, entrypoint, stage,
- spec_info);
- if (nir == NULL)
- return NULL;
-
- if (!variant) {
- variant = radv_shader_variant_create(pipeline->device, module, nir,
- layout, key, &code,
- &code_size);
- }
-
- if (stage == MESA_SHADER_GEOMETRY && !pipeline->gs_copy_shader) {
- void *gs_copy_code = NULL;
- unsigned gs_copy_code_size = 0;
- pipeline->gs_copy_shader = radv_create_gs_copy_shader(
- pipeline->device, nir, &gs_copy_code,
- &gs_copy_code_size, key->has_multiview_view_index);
-
- if (pipeline->gs_copy_shader) {
- pipeline->gs_copy_shader =
- radv_pipeline_cache_insert_shader(pipeline->device,
- cache,
- gs_copy_sha1,
- pipeline->gs_copy_shader,
- gs_copy_code,
- gs_copy_code_size);
- }
-
- free(gs_copy_code);
- }
- if (!module->nir && !pipeline->device->trace_bo)
- ralloc_free(nir);
-
- if (variant)
- variant = radv_pipeline_cache_insert_shader(pipeline->device,
- cache, sha1,
- variant, code,
- code_size);
-
- if (code)
- free(code);
- return variant;
-}
-
-static struct ac_shader_variant_key
-radv_compute_tes_key(bool as_es, bool export_prim_id)
-{
- struct ac_shader_variant_key key;
- memset(&key, 0, sizeof(key));
- key.tes.as_es = as_es;
- /* export prim id only happens when no geom shader */
- if (!as_es)
- key.tes.export_prim_id = export_prim_id;
- return key;
-}
-
-static struct ac_shader_variant_key
-radv_compute_tcs_key(unsigned primitive_mode, unsigned input_vertices)
-{
- struct ac_shader_variant_key key;
- memset(&key, 0, sizeof(key));
- key.tcs.primitive_mode = primitive_mode;
- key.tcs.input_vertices = input_vertices;
- return key;
-}
-
-static void
-radv_tess_pipeline_compile(struct radv_pipeline *pipeline,
- struct radv_pipeline_cache *cache,
- struct radv_shader_module *tcs_module,
- struct radv_shader_module *tes_module,
- const char *tcs_entrypoint,
- const char *tes_entrypoint,
- const VkSpecializationInfo *tcs_spec_info,
- const VkSpecializationInfo *tes_spec_info,
- struct radv_pipeline_layout *layout,
- unsigned input_vertices,
- bool has_view_index)
-{
- unsigned char tcs_sha1[20], tes_sha1[20];
- struct radv_shader_variant *tes_variant = NULL, *tcs_variant = NULL;
- nir_shader *tes_nir, *tcs_nir;
- void *tes_code = NULL, *tcs_code = NULL;
- unsigned tes_code_size = 0, tcs_code_size = 0;
- struct ac_shader_variant_key tes_key;
- struct ac_shader_variant_key tcs_key;
- unsigned hash_flags = get_hash_flags(pipeline->device);
-
- tes_key = radv_compute_tes_key(radv_pipeline_has_gs(pipeline),
- pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input);
- tes_key.has_multiview_view_index = has_view_index;
- if (tes_module->nir)
- _mesa_sha1_compute(tes_module->nir->info.name,
- strlen(tes_module->nir->info.name),
- tes_module->sha1);
- radv_hash_shader(tes_sha1, tes_module, tes_entrypoint, tes_spec_info, layout, &tes_key, hash_flags);
-
- tes_variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
- cache,
- tes_sha1);
-
- if (tes_variant) {
- tcs_key = radv_compute_tcs_key(tes_variant->info.tes.primitive_mode, input_vertices);
-
- if (tcs_module->nir)
- _mesa_sha1_compute(tcs_module->nir->info.name,
- strlen(tcs_module->nir->info.name),
- tcs_module->sha1);
-
- radv_hash_shader(tcs_sha1, tcs_module, tcs_entrypoint, tcs_spec_info, layout, &tcs_key, hash_flags);
-
- tcs_variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
- cache,
- tcs_sha1);
- }
-
- if (tcs_variant && tes_variant) {
- pipeline->shaders[MESA_SHADER_TESS_CTRL] = tcs_variant;
- pipeline->shaders[MESA_SHADER_TESS_EVAL] = tes_variant;
- return;
- }
-
- tes_nir = radv_shader_compile_to_nir(pipeline->device,
- tes_module, tes_entrypoint, MESA_SHADER_TESS_EVAL,
- tes_spec_info);
- if (tes_nir == NULL)
- return;
-
- tcs_nir = radv_shader_compile_to_nir(pipeline->device,
- tcs_module, tcs_entrypoint, MESA_SHADER_TESS_CTRL,
- tcs_spec_info);
- if (tcs_nir == NULL)
- return;
-
- nir_lower_tes_patch_vertices(tes_nir,
- tcs_nir->info.tess.tcs_vertices_out);
-
- tes_variant = radv_shader_variant_create(pipeline->device, tes_module, tes_nir,
- layout, &tes_key, &tes_code,
- &tes_code_size);
-
- tcs_key = radv_compute_tcs_key(tes_nir->info.tess.primitive_mode, input_vertices);
- if (tcs_module->nir)
- _mesa_sha1_compute(tcs_module->nir->info.name,
- strlen(tcs_module->nir->info.name),
- tcs_module->sha1);
-
- radv_hash_shader(tcs_sha1, tcs_module, tcs_entrypoint, tcs_spec_info, layout, &tcs_key, hash_flags);
-
- tcs_variant = radv_shader_variant_create(pipeline->device, tcs_module, tcs_nir,
- layout, &tcs_key, &tcs_code,
- &tcs_code_size);
-
- if (!tes_module->nir && !pipeline->device->trace_bo)
- ralloc_free(tes_nir);
-
- if (!tcs_module->nir && !pipeline->device->trace_bo)
- ralloc_free(tcs_nir);
-
- if (tes_variant)
- tes_variant = radv_pipeline_cache_insert_shader(pipeline->device, cache, tes_sha1, tes_variant,
- tes_code, tes_code_size);
-
- if (tcs_variant)
- tcs_variant = radv_pipeline_cache_insert_shader(pipeline->device, cache, tcs_sha1, tcs_variant,
- tcs_code, tcs_code_size);
-
- if (tes_code)
- free(tes_code);
- if (tcs_code)
- free(tcs_code);
- pipeline->shaders[MESA_SHADER_TESS_CTRL] = tcs_variant;
- pipeline->shaders[MESA_SHADER_TESS_EVAL] = tes_variant;
- return;
-}
-
static VkResult
radv_pipeline_scratch_init(struct radv_device *device,
struct radv_pipeline *pipeline)
return key;
}
+
+static void calculate_gfx9_gs_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
+ struct radv_pipeline *pipeline)
+{
+ struct ac_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
+ struct ac_es_output_info *es_info = radv_pipeline_has_tess(pipeline) ?
+ &gs_info->tes.es_info : &gs_info->vs.es_info;
+ unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
+ bool uses_adjacency;
+ switch(pCreateInfo->pInputAssemblyState->topology) {
+ case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
+ case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
+ case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
+ case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
+ uses_adjacency = false;
+ break;
+ default:
+ uses_adjacency = false;
+ break;
+ }
+
+ /* All these are in dwords: */
+ /* We can't allow using the whole LDS, because GS waves compete with
+ * other shader stages for LDS space. */
+ const unsigned max_lds_size = 8 * 1024;
+ const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
+ unsigned esgs_lds_size;
+
+ /* All these are per subgroup: */
+ const unsigned max_out_prims = 32 * 1024;
+ const unsigned max_es_verts = 255;
+ const unsigned ideal_gs_prims = 64;
+ unsigned max_gs_prims, gs_prims;
+ unsigned min_es_verts, es_verts, worst_case_es_verts;
+
+ if (uses_adjacency || gs_num_invocations > 1)
+ max_gs_prims = 127 / gs_num_invocations;
+ else
+ max_gs_prims = 255;
+
+ /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
+ * Make sure we don't go over the maximum value.
+ */
+ if (gs_info->gs.vertices_out > 0) {
+ max_gs_prims = MIN2(max_gs_prims,
+ max_out_prims /
+ (gs_info->gs.vertices_out * gs_num_invocations));
+ }
+ assert(max_gs_prims > 0);
+
+ /* If the primitive has adjacency, halve the number of vertices
+ * that will be reused in multiple primitives.
+ */
+ min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
+
+ gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
+ worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
+
+ /* Compute ESGS LDS size based on the worst case number of ES vertices
+ * needed to create the target number of GS prims per subgroup.
+ */
+ esgs_lds_size = esgs_itemsize * worst_case_es_verts;
+
+ /* If total LDS usage is too big, refactor partitions based on ratio
+ * of ESGS item sizes.
+ */
+ if (esgs_lds_size > max_lds_size) {
+ /* Our target GS Prims Per Subgroup was too large. Calculate
+ * the maximum number of GS Prims Per Subgroup that will fit
+ * into LDS, capped by the maximum that the hardware can support.
+ */
+ gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
+ max_gs_prims);
+ assert(gs_prims > 0);
+ worst_case_es_verts = MIN2(min_es_verts * gs_prims,
+ max_es_verts);
+
+ esgs_lds_size = esgs_itemsize * worst_case_es_verts;
+ assert(esgs_lds_size <= max_lds_size);
+ }
+
+ /* Now calculate remaining ESGS information. */
+ if (esgs_lds_size)
+ es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
+ else
+ es_verts = max_es_verts;
+
+ /* Vertices for adjacency primitives are not always reused, so restore
+ * it for ES_VERTS_PER_SUBGRP.
+ */
+ min_es_verts = gs_info->gs.vertices_in;
+
+ /* For normal primitives, the VGT only checks if they are past the ES
+ * verts per subgroup after allocating a full GS primitive and if they
+ * are, kick off a new subgroup. But if those additional ES verts are
+ * unique (e.g. not reused) we need to make sure there is enough LDS
+ * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
+ */
+ es_verts -= min_es_verts - 1;
+
+ uint32_t es_verts_per_subgroup = es_verts;
+ uint32_t gs_prims_per_subgroup = gs_prims;
+ uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
+ uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
+ pipeline->graphics.gs.lds_size = align(esgs_lds_size, 128) / 128;
+ pipeline->graphics.gs.vgt_gs_onchip_cntl =
+ S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
+ S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
+ S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
+ pipeline->graphics.gs.vgt_gs_max_prims_per_subgroup =
+ S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
+ pipeline->graphics.gs.vgt_esgs_ring_itemsize = esgs_itemsize;
+ assert(max_prims_per_subgroup <= max_out_prims);
+}
+
static void
calculate_gs_ring_sizes(struct radv_pipeline *pipeline)
{
/* The maximum size is 63.999 MB per SE. */
unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
struct ac_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
- struct ac_es_output_info *es_info = radv_pipeline_has_tess(pipeline) ?
- &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
- &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
+ struct ac_es_output_info *es_info;
+ if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
+ es_info = radv_pipeline_has_tess(pipeline) ? &gs_info->tes.es_info : &gs_info->vs.es_info;
+ else
+ es_info = radv_pipeline_has_tess(pipeline) ?
+ &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
+ &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
/* Calculate the minimum size. */
unsigned min_esgs_ring_size = align(es_info->esgs_itemsize * gs_vertex_reuse *
esgs_ring_size = align(esgs_ring_size, alignment);
gsvs_ring_size = align(gsvs_ring_size, alignment);
- pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
+ if (pipeline->device->physical_device->rad_info.chip_class <= VI)
+ pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
+
pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
}
*lds_size = MAX2(*lds_size, 8);
}
+struct radv_shader_variant *
+radv_get_vertex_shader(struct radv_pipeline *pipeline)
+{
+ if (pipeline->shaders[MESA_SHADER_VERTEX])
+ return pipeline->shaders[MESA_SHADER_VERTEX];
+ if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
+ return pipeline->shaders[MESA_SHADER_TESS_CTRL];
+ return pipeline->shaders[MESA_SHADER_GEOMETRY];
+}
+
+static struct radv_shader_variant *
+radv_get_tess_eval_shader(struct radv_pipeline *pipeline)
+{
+ if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
+ return pipeline->shaders[MESA_SHADER_TESS_EVAL];
+ return pipeline->shaders[MESA_SHADER_GEOMETRY];
+}
+
static void
calculate_tess_state(struct radv_pipeline *pipeline,
const VkGraphicsPipelineCreateInfo *pCreateInfo)
/* This calculates how shader inputs and outputs among VS, TCS, and TES
* are laid out in LDS. */
- num_tcs_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outputs_written);
+ num_tcs_inputs = util_last_bit64(radv_get_vertex_shader(pipeline)->info.vs.outputs_written);
num_tcs_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written); //tcs->outputs_written
num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
tess->num_patches = num_patches;
tess->num_tcs_input_cp = num_tcs_input_cp;
- struct radv_shader_variant *tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
+ struct radv_shader_variant *tes = radv_get_tess_eval_shader(pipeline);
unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
switch (tes->info.tes.primitive_mode) {
[V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
};
-static uint32_t si_vgt_gs_mode(struct radv_shader_variant *gs)
+static uint32_t si_vgt_gs_mode(struct radv_shader_variant *gs,
+ enum chip_class chip_class)
{
unsigned gs_max_vert_out = gs->info.gs.vertices_out;
unsigned cut_mode;
return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
S_028A40_CUT_MODE(cut_mode)|
- S_028A40_ES_WRITE_OPTIMIZE(1) |
- S_028A40_GS_WRITE_OPTIMIZE(1);
+ S_028A40_ES_WRITE_OPTIMIZE(chip_class <= VI) |
+ S_028A40_GS_WRITE_OPTIMIZE(1) |
+ S_028A40_ONCHIP(chip_class >= GFX9 ? 1 : 0);
}
-static void calculate_vgt_gs_mode(struct radv_pipeline *pipeline)
+static struct ac_vs_output_info *get_vs_output_info(struct radv_pipeline *pipeline)
{
- struct radv_shader_variant *vs;
- vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
+ if (radv_pipeline_has_gs(pipeline))
+ return &pipeline->gs_copy_shader->info.vs.outinfo;
+ else if (radv_pipeline_has_tess(pipeline))
+ return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
+ else
+ return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
+}
- struct ac_vs_output_info *outinfo = &vs->info.vs.outinfo;
+static void calculate_vgt_gs_mode(struct radv_pipeline *pipeline)
+{
+ struct ac_vs_output_info *outinfo = get_vs_output_info(pipeline);
pipeline->graphics.vgt_primitiveid_en = false;
pipeline->graphics.vgt_gs_mode = 0;
if (radv_pipeline_has_gs(pipeline)) {
- pipeline->graphics.vgt_gs_mode = si_vgt_gs_mode(pipeline->shaders[MESA_SHADER_GEOMETRY]);
+ pipeline->graphics.vgt_gs_mode = si_vgt_gs_mode(pipeline->shaders[MESA_SHADER_GEOMETRY],
+ pipeline->device->physical_device->rad_info.chip_class);
} else if (outinfo->export_prim_id) {
pipeline->graphics.vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
pipeline->graphics.vgt_primitiveid_en = true;
static void calculate_pa_cl_vs_out_cntl(struct radv_pipeline *pipeline)
{
- struct radv_shader_variant *vs;
- vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
-
- struct ac_vs_output_info *outinfo = &vs->info.vs.outinfo;
+ struct ac_vs_output_info *outinfo = get_vs_output_info(pipeline);
unsigned clip_dist_mask, cull_dist_mask, total_mask;
clip_dist_mask = outinfo->clip_dist_mask;
static void calculate_ps_inputs(struct radv_pipeline *pipeline)
{
- struct radv_shader_variant *ps, *vs;
- struct ac_vs_output_info *outinfo;
+ struct radv_shader_variant *ps;
+ struct ac_vs_output_info *outinfo = get_vs_output_info(pipeline);
ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
- vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
-
- outinfo = &vs->info.vs.outinfo;
unsigned ps_offset = 0;
pipeline->graphics.ps_input_cntl_num = ps_offset;
}
+static void
+radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
+{
+ nir_shader* ordered_shaders[MESA_SHADER_STAGES];
+ int shader_count = 0;
+
+ if(shaders[MESA_SHADER_FRAGMENT]) {
+ ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
+ }
+ if(shaders[MESA_SHADER_GEOMETRY]) {
+ ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
+ }
+ if(shaders[MESA_SHADER_TESS_EVAL]) {
+ ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
+ }
+ if(shaders[MESA_SHADER_TESS_CTRL]) {
+ ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
+ }
+ if(shaders[MESA_SHADER_VERTEX]) {
+ ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
+ }
+
+ for (int i = 1; i < shader_count; ++i) {
+ nir_remove_dead_variables(ordered_shaders[i],
+ nir_var_shader_out);
+ nir_remove_dead_variables(ordered_shaders[i - 1],
+ nir_var_shader_in);
+
+ bool progress = nir_remove_unused_varyings(ordered_shaders[i],
+ ordered_shaders[i - 1]);
+
+ if (progress) {
+ nir_lower_global_vars_to_local(ordered_shaders[i]);
+ radv_optimize_nir(ordered_shaders[i]);
+ nir_lower_global_vars_to_local(ordered_shaders[i - 1]);
+ radv_optimize_nir(ordered_shaders[i - 1]);
+ }
+ }
+}
+
static
void radv_create_shaders(struct radv_pipeline *pipeline,
struct radv_device *device,
gs_copy_hash[0] ^= 1;
if (modules[MESA_SHADER_GEOMETRY]) {
- pipeline->gs_copy_shader =
- radv_create_shader_variant_from_pipeline_cache(
- pipeline->device,
- cache,
- gs_copy_hash);
+ struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
+ radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants);
+ pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
}
if (radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders) &&
- (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader))
+ (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
+ for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
+ if (pipeline->shaders[i])
+ pipeline->active_stages |= mesa_to_vk_shader_stage(i);
+ }
return;
+ }
- if (!modules[MESA_SHADER_FRAGMENT]) {
+ if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
nir_builder fs_b;
nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
nir_lower_tes_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out);
}
+ radv_link_shaders(pipeline, nir);
+
if (nir[MESA_SHADER_FRAGMENT]) {
pipeline->shaders[MESA_SHADER_FRAGMENT] =
- radv_shader_variant_create(device, modules[MESA_SHADER_FRAGMENT], nir[MESA_SHADER_FRAGMENT],
+ radv_shader_variant_create(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
pipeline->layout, keys ? keys + MESA_SHADER_FRAGMENT : 0,
&codes[MESA_SHADER_FRAGMENT], &code_sizes[MESA_SHADER_FRAGMENT]);
keys[MESA_SHADER_TESS_EVAL].tes.export_prim_id =
pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input;
}
+ }
+
+ if (device->physical_device->rad_info.chip_class >= GFX9 &&
+ modules[MESA_SHADER_TESS_CTRL] && !pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
+ struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
+ struct ac_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
+ key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
+ pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_create(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
+ pipeline->layout,
+ &key, &codes[MESA_SHADER_TESS_CTRL],
+ &code_sizes[MESA_SHADER_TESS_CTRL]);
+ modules[MESA_SHADER_VERTEX] = NULL;
+ }
- pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_FRAGMENT);
+ if (device->physical_device->rad_info.chip_class >= GFX9 &&
+ modules[MESA_SHADER_GEOMETRY] && !pipeline->shaders[MESA_SHADER_GEOMETRY]) {
+ gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
+ struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
+ pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_create(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
+ pipeline->layout,
+ &keys[pre_stage] , &codes[MESA_SHADER_GEOMETRY],
+ &code_sizes[MESA_SHADER_GEOMETRY]);
+ modules[pre_stage] = NULL;
}
for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
if(modules[i] && !pipeline->shaders[i]) {
- pipeline->shaders[i] = radv_shader_variant_create(device, modules[i], nir[i],
+ pipeline->shaders[i] = radv_shader_variant_create(device, modules[i], &nir[i], 1,
pipeline->layout,
keys ? keys + i : 0, &codes[i],
&code_sizes[i]);
-
- pipeline->active_stages |= mesa_to_vk_shader_stage(i);
}
}
}
if (pipeline->gs_copy_shader) {
- pipeline->gs_copy_shader =
- radv_pipeline_cache_insert_shader(device, cache,
- gs_copy_hash,
- pipeline->gs_copy_shader,
- gs_copy_code,
- gs_copy_code_size);
+ void *code[MESA_SHADER_STAGES] = {0};
+ unsigned code_size[MESA_SHADER_STAGES] = {0};
+ struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
+
+ code[MESA_SHADER_GEOMETRY] = gs_copy_code;
+ code_size[MESA_SHADER_GEOMETRY] = gs_copy_code_size;
+ variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
+
+ radv_pipeline_cache_insert_shaders(device, cache,
+ gs_copy_hash,
+ variants,
+ (const void**)code,
+ code_size);
}
free(gs_copy_code);
}
for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
free(codes[i]);
- if (modules[i] && !modules[i]->nir)
+ if (modules[i] && !modules[i]->nir && !pipeline->device->trace_bo)
ralloc_free(nir[i]);
}
pipeline->graphics.vgt_shader_stages_en = stages;
- if (radv_pipeline_has_gs(pipeline))
+ if (radv_pipeline_has_gs(pipeline)) {
calculate_gs_ring_sizes(pipeline);
+ if (device->physical_device->rad_info.chip_class >= GFX9)
+ calculate_gfx9_gs_info(pCreateInfo, pipeline);
+ }
if (radv_pipeline_has_tess(pipeline)) {
if (pipeline->graphics.prim == V_008958_DI_PT_PATCH) {
if (radv_pipeline_has_tess(pipeline)) {
/* SWITCH_ON_EOI must be set if PrimID is used. */
if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.uses_prim_id ||
- pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.uses_prim_id)
+ radv_get_tess_eval_shader(pipeline)->info.tes.uses_prim_id)
pipeline->graphics.ia_switch_on_eoi = true;
}
struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
AC_UD_VS_BASE_VERTEX_START_INSTANCE);
if (loc->sgpr_idx != -1) {
- pipeline->graphics.vtx_base_sgpr = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
+ pipeline->graphics.vtx_base_sgpr = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
- if (pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
+ if (radv_get_vertex_shader(pipeline)->info.info.vs.needs_draw_id)
pipeline->graphics.vtx_emit_num = 3;
else
pipeline->graphics.vtx_emit_num = 2;
pipeline->graphics.vtx_reuse_depth = 30;
if (radv_pipeline_has_tess(pipeline) &&
- pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
+ radv_get_tess_eval_shader(pipeline)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
pipeline->graphics.vtx_reuse_depth = 14;
}
projects / mesa.git / blobdiff