amd/common: Always initialize gfx9 mipmap offset/pitch.

[mesa.git] / src / amd / vulkan / radv_pipeline_cache.c

diff --git a/src/amd/vulkan/radv_pipeline_cache.c b/src/amd/vulkan/radv_pipeline_cache.c
index db7afe5a48cb0942a2206def67bc2e1a48cf3aec..bbddbbc2579c0f3eb47e9a873c0bab137c8f1fe3 100644 (file)
--- a/src/amd/vulkan/radv_pipeline_cache.c
+++ b/src/amd/vulkan/radv_pipeline_cache.c
@@ -243,6 +243,67 @@ radv_is_cache_disabled(struct radv_device *device)
        return (device->instance->debug_flags & RADV_DEBUG_NO_CACHE);
 }
 
+/*
+ * Secure compiles cannot open files so we get the parent process to load the
+ * cache entry for us.
+ */
+static struct cache_entry *
+radv_sc_read_from_disk_cache(struct radv_device *device, uint8_t *disk_sha1)
+{
+       struct cache_entry *entry;
+       unsigned process = device->sc_state->secure_compile_thread_counter;
+       enum radv_secure_compile_type sc_type = RADV_SC_TYPE_READ_DISK_CACHE;
+
+       write(device->sc_state->secure_compile_processes[process].fd_secure_output,
+             &sc_type, sizeof(enum radv_secure_compile_type));
+       write(device->sc_state->secure_compile_processes[process].fd_secure_output,
+             disk_sha1, sizeof(uint8_t) * 20);
+
+       uint8_t found_cache_entry;
+       if (!radv_sc_read(device->sc_state->secure_compile_processes[process].fd_secure_input,
+                         &found_cache_entry, sizeof(uint8_t), true))
+               return NULL;
+
+       if (found_cache_entry) {
+               size_t entry_size;
+               if (!radv_sc_read(device->sc_state->secure_compile_processes[process].fd_secure_input,
+                                 &entry_size, sizeof(size_t), true))
+                       return NULL;
+
+               entry = malloc(entry_size);
+               if (!radv_sc_read(device->sc_state->secure_compile_processes[process].fd_secure_input,
+                                 entry, entry_size, true))
+                       return NULL;
+
+               return entry;
+       }
+
+       return NULL;
+}
+
+/*
+ * Secure compiles cannot open files so we get the parent process to write to
+ * the disk cache for us.
+ */
+static void
+radv_sc_write_to_disk_cache(struct radv_device *device, uint8_t *disk_sha1,
+                           struct cache_entry *entry)
+{
+       unsigned process = device->sc_state->secure_compile_thread_counter;
+       enum radv_secure_compile_type sc_type = RADV_SC_TYPE_WRITE_DISK_CACHE;
+
+       write(device->sc_state->secure_compile_processes[process].fd_secure_output,
+             &sc_type, sizeof(enum radv_secure_compile_type));
+       write(device->sc_state->secure_compile_processes[process].fd_secure_output,
+             disk_sha1, sizeof(uint8_t) * 20);
+
+       uint32_t size = entry_size(entry);
+       write(device->sc_state->secure_compile_processes[process].fd_secure_output,
+             &size, sizeof(uint32_t));
+       write(device->sc_state->secure_compile_processes[process].fd_secure_output,
+             entry, size);
+}
+
 bool
 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
                                                struct radv_pipeline_cache *cache,
@@ -275,9 +336,15 @@ radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
                uint8_t disk_sha1[20];
                disk_cache_compute_key(device->physical_device->disk_cache,
                                       sha1, 20, disk_sha1);
-               entry = (struct cache_entry *)
-                       disk_cache_get(device->physical_device->disk_cache,
-                                      disk_sha1, NULL);
+
+               if (radv_device_use_secure_compile(device->instance)) {
+                       entry = radv_sc_read_from_disk_cache(device, disk_sha1);
+               } else {
+                       entry = (struct cache_entry *)
+                               disk_cache_get(device->physical_device->disk_cache,
+                                              disk_sha1, NULL);
+               }
+
                if (!entry) {
                        pthread_mutex_unlock(&cache->mutex);
                        return false;
@@ -295,7 +362,9 @@ radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
                        free(entry);
                        entry = new_entry;
 
-                       radv_pipeline_cache_add_entry(cache, new_entry);
+                       if (!(device->instance->debug_flags & RADV_DEBUG_NO_MEMORY_CACHE) ||
+                           cache != device->mem_cache)
+                               radv_pipeline_cache_add_entry(cache, new_entry);
                }
        }
 
@@ -314,11 +383,17 @@ radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
 
        }
 
-       for (int i = 0; i < MESA_SHADER_STAGES; ++i)
-               if (entry->variants[i])
-                       p_atomic_inc(&entry->variants[i]->ref_count);
-
        memcpy(variants, entry->variants, sizeof(entry->variants));
+
+       if (device->instance->debug_flags & RADV_DEBUG_NO_MEMORY_CACHE &&
+           cache == device->mem_cache)
+               vk_free(&cache->alloc, entry);
+       else {
+               for (int i = 0; i < MESA_SHADER_STAGES; ++i)
+                       if (entry->variants[i])
+                               p_atomic_inc(&entry->variants[i]->ref_count);
+       }
+
        pthread_mutex_unlock(&cache->mutex);
        return true;
 }
@@ -394,8 +469,24 @@ radv_pipeline_cache_insert_shaders(struct radv_device *device,
                uint8_t disk_sha1[20];
                disk_cache_compute_key(device->physical_device->disk_cache, sha1, 20,
                               disk_sha1);
-               disk_cache_put(device->physical_device->disk_cache,
-                              disk_sha1, entry, entry_size(entry), NULL);
+
+               /* Write the cache item out to the parent of this forked
+                * process.
+                */
+               if (radv_device_use_secure_compile(device->instance)) {
+                       radv_sc_write_to_disk_cache(device, disk_sha1, entry);
+               } else {
+                       disk_cache_put(device->physical_device->disk_cache,
+                                      disk_sha1, entry, entry_size(entry),
+                                      NULL);
+               }
+       }
+
+       if (device->instance->debug_flags & RADV_DEBUG_NO_MEMORY_CACHE &&
+           cache == device->mem_cache) {
+               vk_free2(&cache->alloc, NULL, entry);
+               pthread_mutex_unlock(&cache->mutex);
+               return;
        }
 
        /* We delay setting the variant so we have reproducible disk cache