radv/gfx10: implement a GE bug workaround

[mesa.git] / src / amd / vulkan / radv_private.h

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index df9d2030a3ad7e2f84e80780887b3fd4067c2f62..143c09811c8fe4c952666cbb8af47b00b4a0ff61 100644 (file)
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -60,9 +60,10 @@
 #include "ac_surface.h"
 #include "ac_llvm_build.h"
 #include "ac_llvm_util.h"
+#include "radv_constants.h"
 #include "radv_descriptor_set.h"
 #include "radv_extensions.h"
-#include "radv_cs.h"
+#include "sid.h"
 
 #include <llvm-c/TargetMachine.h>
 
@@ -94,40 +95,6 @@ struct gfx10_format {
 
 #include "gfx10_format_table.h"
 
-#define ATI_VENDOR_ID 0x1002
-
-#define MAX_VBS         32
-#define MAX_VERTEX_ATTRIBS 32
-#define MAX_RTS          8
-#define MAX_VIEWPORTS   16
-#define MAX_SCISSORS    16
-#define MAX_DISCARD_RECTANGLES 4
-#define MAX_SAMPLE_LOCATIONS 32
-#define MAX_PUSH_CONSTANTS_SIZE 128
-#define MAX_PUSH_DESCRIPTORS 32
-#define MAX_DYNAMIC_UNIFORM_BUFFERS 16
-#define MAX_DYNAMIC_STORAGE_BUFFERS 8
-#define MAX_DYNAMIC_BUFFERS (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
-#define MAX_SAMPLES_LOG2 4
-#define NUM_META_FS_KEYS 12
-#define RADV_MAX_DRM_DEVICES 8
-#define MAX_VIEWS        8
-#define MAX_SO_STREAMS 4
-#define MAX_SO_BUFFERS 4
-#define MAX_SO_OUTPUTS 64
-#define MAX_INLINE_UNIFORM_BLOCK_SIZE (4ull * 1024 * 1024)
-#define MAX_INLINE_UNIFORM_BLOCK_COUNT 64
-
-#define NUM_DEPTH_CLEAR_PIPELINES 3
-
-/*
- * This is the point we switch from using CP to compute shader
- * for certain buffer operations.
- */
-#define RADV_BUFFER_OPS_CS_THRESHOLD 4096
-
-#define RADV_BUFFER_UPDATE_THRESHOLD 1024
-
 enum radv_mem_heap {
        RADV_MEM_HEAP_VRAM,
        RADV_MEM_HEAP_VRAM_CPU_ACCESS,
@@ -317,6 +284,7 @@ struct radv_physical_device {
        bool has_clear_state;
        bool cpdma_prefetch_writes_memory;
        bool has_scissor_bug;
+       bool has_tc_compat_zrange_bug;
 
        bool has_out_of_order_rast;
        bool out_of_order_rast_allowed;
@@ -333,6 +301,9 @@ struct radv_physical_device {
        /* Whether DISABLE_CONSTANT_ENCODE_REG is supported. */
        bool has_dcc_constant_encode;
 
+       /* Number of threads per wave. */
+       uint8_t cs_wave_size;
+
        /* This is the drivers on-disk cache used as a fallback as opposed to
         * the pipeline cache defined by apps.
         */
@@ -1244,7 +1215,7 @@ void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
                                enum chip_class chip_class,
                                bool is_mec,
                                unsigned event, unsigned event_flags,
-                               unsigned data_sel,
+                               unsigned dst_sel, unsigned data_sel,
                                uint64_t va,
                                uint32_t new_fence,
                                uint64_t gfx9_eop_bug_va);
@@ -1390,6 +1361,8 @@ struct radv_shader_module;
 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
 #define RADV_HASH_SHADER_SISCHED             (1 << 1)
 #define RADV_HASH_SHADER_UNSAFE_MATH         (1 << 2)
+#define RADV_HASH_SHADER_NO_NGG              (1 << 3)
+
 void
 radv_hash_shaders(unsigned char *hash,
                  const VkPipelineShaderStageCreateInfo **stages,
@@ -1449,6 +1422,11 @@ struct radv_ia_multi_vgt_param_helpers {
        bool partial_vs_wave;
 };
 
+struct radv_binning_state {
+       uint32_t pa_sc_binner_cntl_0;
+       uint32_t db_dfsm_control;
+};
+
 #define SI_GS_PER_ES 128
 
 struct radv_pipeline {
@@ -1475,6 +1453,7 @@ struct radv_pipeline {
        union {
                struct {
                        struct radv_multisample_state ms;
+                       struct radv_binning_state binning;
                        uint32_t spi_baryc_cntl;
                        bool prim_restart_enable;
                        unsigned esgs_ring_size;
@@ -1510,6 +1489,10 @@ static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
        return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
 }
 
+bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline);
+
+bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline);
+
 struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
                                                 gl_shader_stage stage,
                                                 int idx);
@@ -2131,6 +2114,7 @@ void radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
                             const struct radv_nir_compiler_options *options);
 
 unsigned radv_nir_get_max_workgroup_size(enum chip_class chip_class,
+                                        gl_shader_stage stage,
                                         const struct nir_shader *nir);
 
 /* radv_shader_info.h */
@@ -2146,6 +2130,30 @@ struct radeon_winsys_sem;
 
 uint64_t radv_get_current_time(void);
 
+static inline uint32_t
+si_conv_gl_prim_to_vertices(unsigned gl_prim)
+{
+       switch (gl_prim) {
+       case 0: /* GL_POINTS */
+               return 1;
+       case 1: /* GL_LINES */
+       case 3: /* GL_LINE_STRIP */
+               return 2;
+       case 4: /* GL_TRIANGLES */
+       case 5: /* GL_TRIANGLE_STRIP */
+               return 3;
+       case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
+               return 4;
+       case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
+               return 6;
+       case 7: /* GL_QUADS */
+               return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
+       default:
+               assert(0);
+               return 0;
+       }
+}
+
 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType)                \
                                                                \
        static inline struct __radv_type *                      \