radv: Add logic for multisample format descriptions.

[mesa.git] / src / amd / vulkan / radv_private.h

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index b9a1f7e3b7c51b7b14a04f4ad15abad768450cb4..248a5ec0ac7ce38d105ce9c8b297b51522aa6c15 100644 (file)
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -48,6 +48,7 @@
 #include "compiler/shader_enums.h"
 #include "util/macros.h"
 #include "util/list.h"
+#include "util/xmlconfig.h"
 #include "main/macros.h"
 #include "vk_alloc.h"
 #include "vk_debug_report.h"
@@ -102,6 +103,8 @@ typedef uint32_t xcb_window_t;
 #define MAX_SO_STREAMS 4
 #define MAX_SO_BUFFERS 4
 #define MAX_SO_OUTPUTS 64
+#define MAX_INLINE_UNIFORM_BLOCK_SIZE (4ull * 1024 * 1024)
+#define MAX_INLINE_UNIFORM_BLOCK_COUNT 64
 
 #define NUM_DEPTH_CLEAR_PIPELINES 3
 
@@ -285,7 +288,6 @@ struct radv_physical_device {
 
        struct radeon_winsys *ws;
        struct radeon_info rad_info;
-       char                                        path[20];
        char                                        name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
        uint8_t                                     driver_uuid[VK_UUID_SIZE];
        uint8_t                                     device_uuid[VK_UUID_SIZE];
@@ -307,6 +309,9 @@ struct radv_physical_device {
        /* Whether DCC should be enabled for MSAA textures. */
        bool dcc_msaa_allowed;
 
+       /* Whether LOAD_CONTEXT_REG packets are supported. */
+       bool has_load_ctx_reg_pkt;
+
        /* This is the drivers on-disk cache used as a fallback as opposed to
         * the pipeline cache defined by apps.
         */
@@ -335,6 +340,9 @@ struct radv_instance {
        struct vk_debug_report_instance             debug_report_callbacks;
 
        struct radv_instance_extension_table enabled_extensions;
+
+       struct driOptionCache dri_options;
+       struct driOptionCache available_dri_options;
 };
 
 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
@@ -363,7 +371,12 @@ struct radv_pipeline_cache {
 struct radv_pipeline_key {
        uint32_t instance_rate_inputs;
        uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
+       uint8_t vertex_attribute_formats[MAX_VERTEX_ATTRIBS];
+       uint32_t vertex_attribute_bindings[MAX_VERTEX_ATTRIBS];
+       uint32_t vertex_attribute_offsets[MAX_VERTEX_ATTRIBS];
+       uint32_t vertex_attribute_strides[MAX_VERTEX_ATTRIBS];
        uint64_t vertex_alpha_adjust;
+       uint32_t vertex_post_shuffle;
        unsigned tess_input_vertices;
        uint32_t col_format;
        uint32_t is_int8;
@@ -389,7 +402,8 @@ bool
 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
                                                struct radv_pipeline_cache *cache,
                                                const unsigned char *sha1,
-                                               struct radv_shader_variant **variants);
+                                               struct radv_shader_variant **variants,
+                                               bool *found_in_application_cache);
 
 void
 radv_pipeline_cache_insert_shaders(struct radv_device *device,
@@ -1056,6 +1070,8 @@ struct radv_cmd_state {
        /* Conditional rendering info. */
        int predication_type; /* -1: disabled, 0: normal, 1: inverted */
        uint64_t predication_va;
+
+       bool context_roll_without_scissor_emitted;
 };
 
 struct radv_cmd_pool {
@@ -1115,8 +1131,7 @@ struct radv_cmd_buffer {
 
        VkResult record_result;
 
-       uint32_t gfx9_fence_offset;
-       struct radeon_winsys_bo *gfx9_fence_bo;
+       uint64_t gfx9_fence_va;
        uint32_t gfx9_fence_idx;
        uint64_t gfx9_eop_bug_va;
 
@@ -1151,7 +1166,6 @@ void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
                                unsigned event, unsigned event_flags,
                                unsigned data_sel,
                                uint64_t va,
-                               uint32_t old_fence,
                                uint32_t new_fence,
                                uint64_t gfx9_eop_bug_va);
 
@@ -1184,8 +1198,7 @@ radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
                             void **ptr);
 void
 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
-                           const struct radv_subpass *subpass,
-                           bool transitions);
+                           const struct radv_subpass *subpass);
 bool
 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
                            unsigned size, unsigned alignmnet,
@@ -1336,11 +1349,7 @@ struct radv_prim_vertex_count {
 };
 
 struct radv_vertex_elements_info {
-       uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
        uint32_t format_size[MAX_VERTEX_ATTRIBS];
-       uint32_t binding[MAX_VERTEX_ATTRIBS];
-       uint32_t offset[MAX_VERTEX_ATTRIBS];
-       uint32_t count;
 };
 
 struct radv_ia_multi_vgt_param_helpers {
@@ -1366,10 +1375,13 @@ struct radv_pipeline {
        VkShaderStageFlags                           active_stages;
 
        struct radeon_cmdbuf                      cs;
+       uint32_t                                  ctx_cs_hash;
+       struct radeon_cmdbuf                      ctx_cs;
 
        struct radv_vertex_elements_info             vertex_elements;
 
        uint32_t                                     binding_stride[MAX_VBS];
+       uint8_t                                      num_vertex_bindings;
 
        uint32_t user_data_0[MESA_SHADER_STAGES];
        union {
@@ -1461,6 +1473,7 @@ bool radv_format_pack_clear_color(VkFormat format,
 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
 bool radv_dcc_formats_compatible(VkFormat format1,
                                  VkFormat format2);
+bool radv_device_supports_etc(struct radv_physical_device *physical_device);
 
 struct radv_fmask_info {
        uint64_t offset;
@@ -1815,16 +1828,22 @@ struct radv_subpass_attachment {
 };
 
 struct radv_subpass {
+       uint32_t                                     attachment_count;
+       struct radv_subpass_attachment *             attachments;
+
        uint32_t                                     input_count;
        uint32_t                                     color_count;
        struct radv_subpass_attachment *             input_attachments;
        struct radv_subpass_attachment *             color_attachments;
        struct radv_subpass_attachment *             resolve_attachments;
-       struct radv_subpass_attachment               depth_stencil_attachment;
+       struct radv_subpass_attachment *             depth_stencil_attachment;
 
        /** Subpass has at least one resolve attachment */
        bool                                         has_resolve;
 
+       /** Subpass has at least one color attachment */
+       bool                                         has_color_att;
+
        struct radv_subpass_barrier                  start_barrier;
 
        uint32_t                                     view_mask;
@@ -1838,7 +1857,9 @@ struct radv_render_pass_attachment {
        VkAttachmentLoadOp                           stencil_load_op;
        VkImageLayout                                initial_layout;
        VkImageLayout                                final_layout;
-       uint32_t                                     view_mask;
+
+       /* The subpass id in which the attachment will be used last. */
+       uint32_t                                     last_subpass_idx;
 };
 
 struct radv_render_pass {
@@ -1888,7 +1909,7 @@ void
 radv_update_descriptor_set_with_template(struct radv_device *device,
                                          struct radv_cmd_buffer *cmd_buffer,
                                          struct radv_descriptor_set *set,
-                                         VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
+                                         VkDescriptorUpdateTemplate descriptorUpdateTemplate,
                                          const void *pData);
 
 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
@@ -1933,6 +1954,9 @@ void radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
                             int nir_count,
                             const struct radv_nir_compiler_options *options);
 
+unsigned radv_nir_get_max_workgroup_size(enum chip_class chip_class,
+                                        const struct nir_shader *nir);
+
 /* radv_shader_info.h */
 struct radv_shader_info;
 
@@ -1940,8 +1964,12 @@ void radv_nir_shader_info_pass(const struct nir_shader *nir,
                               const struct radv_nir_compiler_options *options,
                               struct radv_shader_info *info);
 
+void radv_nir_shader_info_init(struct radv_shader_info *info);
+
 struct radeon_winsys_sem;
 
+uint64_t radv_get_current_time(void);
+
 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType)                \
                                                                \
        static inline struct __radv_type *                      \
@@ -1985,7 +2013,7 @@ RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
-RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
+RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplate)
 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)