#include "compiler/shader_enums.h"
#include "util/macros.h"
#include "util/list.h"
+#include "util/xmlconfig.h"
#include "main/macros.h"
#include "vk_alloc.h"
#include "vk_debug_report.h"
#define MAX_SO_STREAMS 4
#define MAX_SO_BUFFERS 4
#define MAX_SO_OUTPUTS 64
+#define MAX_INLINE_UNIFORM_BLOCK_SIZE (4ull * 1024 * 1024)
+#define MAX_INLINE_UNIFORM_BLOCK_COUNT 64
#define NUM_DEPTH_CLEAR_PIPELINES 3
/* Whether DCC should be enabled for MSAA textures. */
bool dcc_msaa_allowed;
+ /* Whether LOAD_CONTEXT_REG packets are supported. */
+ bool has_load_ctx_reg_pkt;
+
/* This is the drivers on-disk cache used as a fallback as opposed to
* the pipeline cache defined by apps.
*/
struct vk_debug_report_instance debug_report_callbacks;
struct radv_instance_extension_table enabled_extensions;
+
+ struct driOptionCache dri_options;
+ struct driOptionCache available_dri_options;
};
VkResult radv_init_wsi(struct radv_physical_device *physical_device);
struct radv_pipeline_key {
uint32_t instance_rate_inputs;
uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
+ uint8_t vertex_attribute_formats[MAX_VERTEX_ATTRIBS];
+ uint32_t vertex_attribute_bindings[MAX_VERTEX_ATTRIBS];
+ uint32_t vertex_attribute_offsets[MAX_VERTEX_ATTRIBS];
+ uint32_t vertex_attribute_strides[MAX_VERTEX_ATTRIBS];
uint64_t vertex_alpha_adjust;
+ uint32_t vertex_post_shuffle;
unsigned tess_input_vertices;
uint32_t col_format;
uint32_t is_int8;
radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
struct radv_pipeline_cache *cache,
const unsigned char *sha1,
- struct radv_shader_variant **variants);
+ struct radv_shader_variant **variants,
+ bool *found_in_application_cache);
void
radv_pipeline_cache_insert_shaders(struct radv_device *device,
};
struct radv_vertex_elements_info {
- uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
uint32_t format_size[MAX_VERTEX_ATTRIBS];
- uint32_t binding[MAX_VERTEX_ATTRIBS];
- uint32_t offset[MAX_VERTEX_ATTRIBS];
- uint32_t count;
};
struct radv_ia_multi_vgt_param_helpers {
struct radv_vertex_elements_info vertex_elements;
uint32_t binding_stride[MAX_VBS];
+ uint8_t num_vertex_bindings;
uint32_t user_data_0[MESA_SHADER_STAGES];
union {
bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
bool radv_dcc_formats_compatible(VkFormat format1,
VkFormat format2);
+bool radv_device_supports_etc(struct radv_physical_device *physical_device);
struct radv_fmask_info {
uint64_t offset;
};
struct radv_subpass {
+ uint32_t attachment_count;
+ struct radv_subpass_attachment * attachments;
+
uint32_t input_count;
uint32_t color_count;
struct radv_subpass_attachment * input_attachments;
struct radv_subpass_attachment * color_attachments;
struct radv_subpass_attachment * resolve_attachments;
- struct radv_subpass_attachment depth_stencil_attachment;
+ struct radv_subpass_attachment * depth_stencil_attachment;
/** Subpass has at least one resolve attachment */
bool has_resolve;
+ /** Subpass has at least one color attachment */
+ bool has_color_att;
+
struct radv_subpass_barrier start_barrier;
uint32_t view_mask;
VkAttachmentLoadOp stencil_load_op;
VkImageLayout initial_layout;
VkImageLayout final_layout;
+
+ /* The subpass id in which the attachment will be used last. */
+ uint32_t last_subpass_idx;
};
struct radv_render_pass {
const struct radv_nir_compiler_options *options,
struct radv_shader_info *info);
+void radv_nir_shader_info_init(struct radv_shader_info *info);
+
struct radeon_winsys_sem;
+uint64_t radv_get_current_time(void);
+
#define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
\
static inline struct __radv_type * \