radv: add has_scissor_bug for Vega10 and Raven

[mesa.git] / src / amd / vulkan / radv_private.h

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index db8ea895e3a5c50e3e16b4dc9d2793ed5043bcf7..2d7d9591872309d12bc3b84d065cf27970011b63 100644 (file)
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -272,6 +272,8 @@ struct radv_physical_device {
        bool has_rbplus; /* if RB+ register exist */
        bool rbplus_allowed; /* if RB+ is allowed */
        bool has_clear_state;
+       bool cpdma_prefetch_writes_memory;
+       bool has_scissor_bug;
 
        /* This is the drivers on-disk cache used as a fallback as opposed to
         * the pipeline cache defined by apps.
@@ -583,6 +585,7 @@ struct radv_device {
 
        bool llvm_supports_spill;
        bool has_distributed_tess;
+       bool pbb_allowed;
        bool dfsm_allowed;
        uint32_t tess_offchip_block_dw_size;
        uint32_t scratch_waves;
@@ -1165,6 +1168,11 @@ struct radv_vs_state {
        uint32_t vgt_reuse_off;
 };
 
+struct radv_binning_state {
+       uint32_t pa_sc_binner_cntl_0;
+       uint32_t db_dfsm_control;
+};
+
 #define SI_GS_PER_ES 128
 
 struct radv_pipeline {
@@ -1193,6 +1201,7 @@ struct radv_pipeline {
                        struct radv_tessellation_state tess;
                        struct radv_gs_state gs;
                        struct radv_vs_state vs;
+                       struct radv_binning_state bin;
                        uint32_t db_shader_control;
                        uint32_t shader_z_format;
                        unsigned prim;
@@ -1355,6 +1364,10 @@ bool radv_layout_can_fast_clear(const struct radv_image *image,
                                VkImageLayout layout,
                                unsigned queue_mask);
 
+bool radv_layout_dcc_compressed(const struct radv_image *image,
+                               VkImageLayout layout,
+                               unsigned queue_mask);
+
 static inline bool
 radv_vi_dcc_enabled(const struct radv_image *image, unsigned level)
 {
@@ -1497,8 +1510,6 @@ struct radv_color_buffer_info {
        uint32_t cb_dcc_control;
        uint32_t cb_color_cmask_slice;
        uint32_t cb_color_fmask_slice;
-       uint32_t cb_clear_value0;
-       uint32_t cb_clear_value1;
 };
 
 struct radv_ds_buffer_info {