radv: Add LLVM version to the device name string
[mesa.git] / src / amd / vulkan / radv_private.h
index cfbdfeb99093c2e9655773bd58b7d8dd6b1a9d1a..3edfda6b122996986f5c3d8f4ad7e2b9557aa681 100644 (file)
@@ -106,11 +106,6 @@ enum radv_mem_type {
        RADV_MEM_TYPE_COUNT
 };
 
-enum radv_mem_flags_bits {
-       /* enable implicit synchronization when accessing the underlying bo */
-       RADV_MEM_IMPLICIT_SYNC = 1 << 0,
-};
-
 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
 
 static inline uint32_t
@@ -266,7 +261,7 @@ struct radv_physical_device {
        struct radeon_winsys *ws;
        struct radeon_info rad_info;
        char                                        path[20];
-       const char *                                name;
+       char                                        name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
        uint8_t                                     driver_uuid[VK_UUID_SIZE];
        uint8_t                                     device_uuid[VK_UUID_SIZE];
        uint8_t                                     cache_uuid[VK_UUID_SIZE];
@@ -506,7 +501,7 @@ struct radv_queue {
        struct radv_device *                         device;
        struct radeon_winsys_ctx                    *hw_ctx;
        enum radeon_ctx_priority                     priority;
-       int queue_family_index;
+       uint32_t queue_family_index;
        int queue_idx;
 
        uint32_t scratch_size;
@@ -701,8 +696,8 @@ enum radv_cmd_dirty_bits {
        RADV_CMD_DIRTY_PIPELINE                          = 1 << 9,
        RADV_CMD_DIRTY_INDEX_BUFFER                      = 1 << 10,
        RADV_CMD_DIRTY_FRAMEBUFFER                       = 1 << 11,
+       RADV_CMD_DIRTY_VERTEX_BUFFER                     = 1 << 12,
 };
-typedef uint32_t radv_cmd_dirty_mask_t;
 
 enum radv_cmd_flush_bits {
        RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
@@ -809,10 +804,14 @@ struct radv_attachment_state {
 };
 
 struct radv_cmd_state {
-       bool                                          vb_dirty;
+       /* Vertex descriptors */
+       bool                                          vb_prefetch_dirty;
+       uint64_t                                      vb_va;
+       unsigned                                      vb_size;
+
        bool                                          push_descriptors_dirty;
        bool predicating;
-       radv_cmd_dirty_mask_t                         dirty;
+       uint32_t                                      dirty;
 
        struct radv_pipeline *                        pipeline;
        struct radv_pipeline *                        emitted_pipeline;
@@ -958,8 +957,7 @@ bool
 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
                            unsigned size, unsigned alignmnet,
                            const void *data, unsigned *out_offset);
-void
-radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer);
+
 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
@@ -985,11 +983,6 @@ void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
 bool radv_get_memory_fd(struct radv_device *device,
                        struct radv_device_memory *memory,
                        int *pFD);
-VkResult radv_alloc_memory(VkDevice _device,
-                          const VkMemoryAllocateInfo* pAllocateInfo,
-                          const VkAllocationCallbacks* pAllocator,
-                          enum radv_mem_flags_bits flags,
-                          VkDeviceMemory* pMem);
 
 /*
  * Takes x,y,z as exact numbers of invocations, instead of blocks.
@@ -1110,6 +1103,13 @@ struct radv_vertex_elements_info {
        uint32_t count;
 };
 
+struct radv_vs_state {
+       uint32_t pa_cl_vs_out_cntl;
+       uint32_t spi_shader_pos_format;
+       uint32_t spi_vs_out_config;
+       uint32_t vgt_reuse_off;
+};
+
 #define SI_GS_PER_ES 128
 
 struct radv_pipeline {
@@ -1128,6 +1128,7 @@ struct radv_pipeline {
 
        uint32_t                                     binding_stride[MAX_VBS];
 
+       uint32_t user_data_0[MESA_SHADER_STAGES];
        union {
                struct {
                        struct radv_blend_state blend;
@@ -1136,6 +1137,7 @@ struct radv_pipeline {
                        struct radv_multisample_state ms;
                        struct radv_tessellation_state tess;
                        struct radv_gs_state gs;
+                       struct radv_vs_state vs;
                        uint32_t db_shader_control;
                        uint32_t shader_z_format;
                        unsigned prim;
@@ -1149,7 +1151,6 @@ struct radv_pipeline {
                        unsigned gsvs_ring_size;
                        uint32_t ps_input_cntl[32];
                        uint32_t ps_input_cntl_num;
-                       uint32_t pa_cl_vs_out_cntl;
                        uint32_t vgt_shader_stages_en;
                        uint32_t vtx_base_sgpr;
                        uint32_t base_ia_multi_vgt_param;
@@ -1349,14 +1350,12 @@ struct radv_image_view {
        uint32_t level_count;
        VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
 
-       uint32_t descriptor[8];
-       uint32_t fmask_descriptor[8];
+       uint32_t descriptor[16];
 
        /* Descriptor for use as a storage image as opposed to a sampled image.
         * This has a few differences for cube maps (e.g. type).
         */
-       uint32_t storage_descriptor[8];
-       uint32_t storage_fmask_descriptor[8];
+       uint32_t storage_descriptor[16];
 };
 
 struct radv_image_create_info {
@@ -1446,8 +1445,6 @@ struct radv_color_buffer_info {
        uint32_t cb_color_fmask_slice;
        uint32_t cb_clear_value0;
        uint32_t cb_clear_value1;
-       uint32_t micro_tile_mode;
-       uint32_t gfx9_epitch;
 };
 
 struct radv_ds_buffer_info {