RADV_MEM_TYPE_COUNT
};
-enum radv_mem_flags_bits {
- /* enable implicit synchronization when accessing the underlying bo */
- RADV_MEM_IMPLICIT_SYNC = 1 << 0,
-};
-
#define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
static inline uint32_t
struct radeon_winsys *ws;
struct radeon_info rad_info;
char path[20];
- const char * name;
+ char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
uint8_t driver_uuid[VK_UUID_SIZE];
uint8_t device_uuid[VK_UUID_SIZE];
uint8_t cache_uuid[VK_UUID_SIZE];
struct radv_device * device;
struct radeon_winsys_ctx *hw_ctx;
enum radeon_ctx_priority priority;
- int queue_family_index;
+ uint32_t queue_family_index;
int queue_idx;
uint32_t scratch_size;
RADV_CMD_DIRTY_PIPELINE = 1 << 9,
RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 11,
+ RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 12,
};
-typedef uint32_t radv_cmd_dirty_mask_t;
enum radv_cmd_flush_bits {
RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
};
struct radv_cmd_state {
- bool vb_dirty;
+ /* Vertex descriptors */
+ bool vb_prefetch_dirty;
+ uint64_t vb_va;
+ unsigned vb_size;
+
bool push_descriptors_dirty;
bool predicating;
- radv_cmd_dirty_mask_t dirty;
+ uint32_t dirty;
struct radv_pipeline * pipeline;
struct radv_pipeline * emitted_pipeline;
radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
unsigned size, unsigned alignmnet,
const void *data, unsigned *out_offset);
-void
-radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer);
+
void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
bool radv_get_memory_fd(struct radv_device *device,
struct radv_device_memory *memory,
int *pFD);
-VkResult radv_alloc_memory(VkDevice _device,
- const VkMemoryAllocateInfo* pAllocateInfo,
- const VkAllocationCallbacks* pAllocator,
- enum radv_mem_flags_bits flags,
- VkDeviceMemory* pMem);
/*
* Takes x,y,z as exact numbers of invocations, instead of blocks.
uint32_t count;
};
+struct radv_vs_state {
+ uint32_t pa_cl_vs_out_cntl;
+ uint32_t spi_shader_pos_format;
+ uint32_t spi_vs_out_config;
+ uint32_t vgt_reuse_off;
+};
+
#define SI_GS_PER_ES 128
struct radv_pipeline {
uint32_t binding_stride[MAX_VBS];
+ uint32_t user_data_0[MESA_SHADER_STAGES];
union {
struct {
struct radv_blend_state blend;
struct radv_multisample_state ms;
struct radv_tessellation_state tess;
struct radv_gs_state gs;
+ struct radv_vs_state vs;
uint32_t db_shader_control;
uint32_t shader_z_format;
unsigned prim;
unsigned gsvs_ring_size;
uint32_t ps_input_cntl[32];
uint32_t ps_input_cntl_num;
- uint32_t pa_cl_vs_out_cntl;
uint32_t vgt_shader_stages_en;
uint32_t vtx_base_sgpr;
uint32_t base_ia_multi_vgt_param;
uint32_t level_count;
VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
- uint32_t descriptor[8];
- uint32_t fmask_descriptor[8];
+ uint32_t descriptor[16];
/* Descriptor for use as a storage image as opposed to a sampled image.
* This has a few differences for cube maps (e.g. type).
*/
- uint32_t storage_descriptor[8];
- uint32_t storage_fmask_descriptor[8];
+ uint32_t storage_descriptor[16];
};
struct radv_image_create_info {
uint32_t cb_color_fmask_slice;
uint32_t cb_clear_value0;
uint32_t cb_clear_value1;
- uint32_t micro_tile_mode;
- uint32_t gfx9_epitch;
};
struct radv_ds_buffer_info {