radv/pipeline: start calculating tess stage.

[mesa.git] / src / amd / vulkan / radv_private.h

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index ab3e881579535fa134c595b8e6a0be4e82140caf..3f92d59ac9769f1045b828af9d826357e05f334f 100644 (file)
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -459,12 +459,15 @@ struct radv_queue {
        uint32_t compute_scratch_size;
        uint32_t esgs_ring_size;
        uint32_t gsvs_ring_size;
+       bool has_tess_rings;
 
        struct radeon_winsys_bo *scratch_bo;
        struct radeon_winsys_bo *descriptor_bo;
        struct radeon_winsys_bo *compute_scratch_bo;
        struct radeon_winsys_bo *esgs_ring_bo;
        struct radeon_winsys_bo *gsvs_ring_bo;
+       struct radeon_winsys_bo *tess_factor_ring_bo;
+       struct radeon_winsys_bo *tess_offchip_ring_bo;
        struct radeon_winsys_cs *initial_preamble_cs;
        struct radeon_winsys_cs *continue_preamble_cs;
 };
@@ -487,6 +490,8 @@ struct radv_device {
        uint64_t debug_flags;
 
        bool llvm_supports_spill;
+       bool has_distributed_tess;
+       uint32_t tess_offchip_block_dw_size;
        uint32_t scratch_waves;
 
        uint32_t gs_table_depth;
@@ -508,6 +513,9 @@ struct radv_device {
        uint32_t                                     *trace_id_ptr;
 
        struct radv_physical_device                  *physical_device;
+
+       /* Backup in-memory cache to be used if the app doesn't provide one */
+       struct radv_pipeline_cache *                mem_cache;
 };
 
 struct radv_device_memory {
@@ -530,7 +538,6 @@ struct radv_descriptor_set {
        const struct radv_descriptor_set_layout *layout;
        uint32_t size;
 
-       struct radv_buffer_view *buffer_views;
        struct radeon_winsys_bo *bo;
        uint64_t va;
        uint32_t *mapped_ptr;
@@ -555,6 +562,7 @@ struct radv_buffer {
        VkDeviceSize                                 size;
 
        VkBufferUsageFlags                           usage;
+       VkBufferCreateFlags                          flags;
 
        /* Set when bound */
        struct radeon_winsys_bo *                      bo;
@@ -728,7 +736,7 @@ struct radv_cmd_buffer {
        uint32_t queue_family_index;
 
        uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
-       uint32_t dynamic_buffers[16 * MAX_DYNAMIC_BUFFERS];
+       uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
        VkShaderStageFlags push_constant_stages;
 
        struct radv_cmd_buffer_upload upload;
@@ -739,6 +747,7 @@ struct radv_cmd_buffer {
        uint32_t compute_scratch_size_needed;
        uint32_t esgs_ring_size_needed;
        uint32_t gsvs_ring_size_needed;
+       bool tess_rings_needed;
 
        int ring_offsets_idx; /* just used for verification */
 };
@@ -755,9 +764,11 @@ void cik_create_gfx_config(struct radv_device *device);
 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
                       int count, const VkViewport *viewports);
 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
-                      int count, const VkRect2D *scissors);
+                      int count, const VkRect2D *scissors,
+                      const VkViewport *viewports, bool can_use_guardband);
 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
-                                  bool instanced_or_indirect_draw, uint32_t draw_vertex_count);
+                                  bool instanced_draw, bool indirect_draw,
+                                  uint32_t draw_vertex_count);
 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
                             enum chip_class chip_class,
                             bool is_mec,
@@ -902,7 +913,6 @@ unsigned radv_format_meta_fs_key(VkFormat format);
 
 struct radv_raster_state {
        uint32_t pa_cl_clip_cntl;
-       uint32_t pa_cl_vs_out_cntl;
        uint32_t spi_interp_control;
        uint32_t pa_su_point_size;
        uint32_t pa_su_point_minmax;
@@ -926,6 +936,18 @@ struct radv_prim_vertex_count {
        uint8_t incr;
 };
 
+struct radv_tessellation_state {
+       uint32_t ls_hs_config;
+       uint32_t tcs_in_layout;
+       uint32_t tcs_out_layout;
+       uint32_t tcs_out_offsets;
+       uint32_t offchip_layout;
+       unsigned num_patches;
+       unsigned lds_size;
+       unsigned num_tcs_input_cp;
+       uint32_t tf_param;
+};
+
 struct radv_pipeline {
        struct radv_device *                          device;
        uint32_t                                     dynamic_state_mask;
@@ -952,12 +974,21 @@ struct radv_pipeline {
                        struct radv_depth_stencil_state ds;
                        struct radv_raster_state raster;
                        struct radv_multisample_state ms;
+                       struct radv_tessellation_state tess;
+                       uint32_t db_shader_control;
+                       uint32_t shader_z_format;
                        unsigned prim;
                        unsigned gs_out;
+                       uint32_t vgt_gs_mode;
                        bool prim_restart_enable;
                        unsigned esgs_ring_size;
                        unsigned gsvs_ring_size;
+                       uint32_t ps_input_cntl[32];
+                       uint32_t ps_input_cntl_num;
+                       uint32_t pa_cl_vs_out_cntl;
+                       uint32_t vgt_shader_stages_en;
                        struct radv_prim_vertex_count prim_vertex_count;
+                       bool can_use_guardband;
                } graphics;
        };
 
@@ -970,6 +1001,11 @@ static inline bool radv_pipeline_has_gs(struct radv_pipeline *pipeline)
        return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
 }
 
+static inline bool radv_pipeline_has_tess(struct radv_pipeline *pipeline)
+{
+       return pipeline->shaders[MESA_SHADER_TESS_EVAL] ? true : false;
+}
+
 struct radv_graphics_pipeline_create_info {
        bool use_rectlist;
        bool db_depth_clear;
@@ -1060,6 +1096,7 @@ struct radv_image {
        uint32_t samples; /**< VkImageCreateInfo::samples */
        VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
        VkImageTiling tiling; /** VkImageCreateInfo::tiling */
+       VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
 
        VkDeviceSize size;
        uint32_t alignment;