radv: configure VGT_VERTEX_REUSE at pipeline creation

[mesa.git] / src / amd / vulkan / radv_private.h

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 73a9a328be3c1a806c46c682028328d01db81d62..4d2b2c696bf5e03aac84283b9f929308675f43d7 100644 (file)
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -197,8 +197,6 @@ radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
                        memcpy((dest), (src), (count) * sizeof(*(src))); \
                })
 
-#define zero(x) (memset(&(x), 0, sizeof(x)))
-
 /* Whenever we generate an error, pass it through this function. Useful for
  * debugging, where we can break on it. Only call at error site, not when
  * propagating errors. Might be useful to plug in a stack trace here.
@@ -398,7 +396,6 @@ struct radv_meta_state {
                VkPipeline pipeline;
        } itob;
        struct {
-               VkRenderPass render_pass;
                VkPipelineLayout                          img_p_layout;
                VkDescriptorSetLayout                     img_ds_layout;
                VkPipeline pipeline;
@@ -748,10 +745,6 @@ struct radv_dynamic_state {
 
 extern const struct radv_dynamic_state default_dynamic_state;
 
-void radv_dynamic_state_copy(struct radv_dynamic_state *dest,
-                            const struct radv_dynamic_state *src,
-                            uint32_t copy_mask);
-
 const char *
 radv_get_debug_option_name(int id);
 
@@ -1016,9 +1009,6 @@ unsigned radv_format_meta_fs_key(VkFormat format);
 struct radv_raster_state {
        uint32_t pa_cl_clip_cntl;
        uint32_t spi_interp_control;
-       uint32_t pa_su_point_size;
-       uint32_t pa_su_point_minmax;
-       uint32_t pa_su_line_cntl;
        uint32_t pa_su_vtx_cntl;
        uint32_t pa_su_sc_mode_cntl;
 };
@@ -1105,6 +1095,7 @@ struct radv_pipeline {
                        bool ia_switch_on_eoi;
                        bool partial_vs_wave;
                        uint8_t vtx_emit_num;
+                       uint32_t vtx_reuse_depth;
                        struct radv_prim_vertex_count prim_vertex_count;
                        bool can_use_guardband;
                } graphics;
@@ -1225,6 +1216,7 @@ struct radv_image {
        VkDeviceSize offset;
        uint32_t dcc_offset;
        uint32_t htile_offset;
+       bool tc_compatible_htile;
        struct radeon_surf surface;
 
        struct radv_fmask_info fmask;
@@ -1253,6 +1245,17 @@ bool radv_layout_can_fast_clear(const struct radv_image *image,
                                VkImageLayout layout,
                                unsigned queue_mask);
 
+static inline bool
+radv_vi_dcc_enabled(const struct radv_image *image, unsigned level)
+{
+       return image->surface.dcc_size && level < image->surface.num_dcc_levels;
+}
+
+static inline bool
+radv_htile_enabled(const struct radv_image *image, unsigned level)
+{
+       return image->surface.htile_size && level == 0;
+}
 
 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);