radv: handle primitive id input into fragment shader with no geom shader

[mesa.git] / src / amd / vulkan / radv_private.h

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 1a45734780bbfe98c317e53f75ca59c4fa2f8f6b..630448d3b2a3f8934b2b9277de2c4247146db79e 100644 (file)
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -47,8 +47,8 @@
 #include "compiler/shader_enums.h"
 #include "util/macros.h"
 #include "util/list.h"
-#include "util/vk_alloc.h"
 #include "main/macros.h"
+#include "vk_alloc.h"
 
 #include "radv_radeon_winsys.h"
 #include "ac_binary.h"
@@ -273,6 +273,9 @@ struct radv_physical_device {
        int local_fd;
        struct wsi_device                       wsi_device;
        struct radv_extensions                      extensions;
+
+       bool has_rbplus; /* if RB+ register exist */
+       bool rbplus_allowed; /* if RB+ is allowed */
 };
 
 struct radv_instance {
@@ -285,6 +288,7 @@ struct radv_instance {
        struct radv_physical_device                 physicalDevices[RADV_MAX_DRM_DEVICES];
 
        uint64_t debug_flags;
+       uint64_t perftest_flags;
 };
 
 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
@@ -747,7 +751,6 @@ struct radv_attachment_state {
 struct radv_cmd_state {
        uint32_t                                      vb_dirty;
        radv_cmd_dirty_mask_t                         dirty;
-       bool                                          vertex_descriptors_dirty;
        bool                                          push_descriptors_dirty;
 
        struct radv_pipeline *                        pipeline;
@@ -762,9 +765,9 @@ struct radv_cmd_state {
        struct radv_descriptor_set *                  descriptors[MAX_SETS];
        struct radv_attachment_state *                attachments;
        VkRect2D                                     render_area;
-       struct radv_buffer *                         index_buffer;
        uint32_t                                     index_type;
-       uint32_t                                     index_offset;
+       uint64_t                                     index_va;
+       uint32_t                                     max_index_count;
        int32_t                                      last_primitive_reset_en;
        uint32_t                                     last_primitive_reset_index;
        enum radv_cmd_flush_bits                     flush_bits;
@@ -822,6 +825,9 @@ struct radv_cmd_buffer {
        bool record_fail;
 
        int ring_offsets_idx; /* just used for verification */
+       uint32_t gfx9_fence_offset;
+       struct radeon_winsys_bo *gfx9_fence_bo;
+       uint32_t gfx9_fence_idx;
 };
 
 struct radv_image;
@@ -854,13 +860,10 @@ void si_emit_wait_fence(struct radeon_winsys_cs *cs,
                        uint64_t va, uint32_t ref,
                        uint32_t mask);
 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
-                            enum chip_class chip_class,
-                            bool is_mec,
-                            enum radv_cmd_flush_bits flush_bits);
-void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
-                            enum chip_class chip_class,
-                            bool is_mec,
-                            enum radv_cmd_flush_bits flush_bits);
+                           enum chip_class chip_class,
+                           uint32_t *fence_ptr, uint64_t va,
+                           bool is_mec,
+                           enum radv_cmd_flush_bits flush_bits);
 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
                           uint64_t src_va, uint64_t dest_va,
@@ -1068,6 +1071,7 @@ struct radv_pipeline {
                        unsigned prim;
                        unsigned gs_out;
                        uint32_t vgt_gs_mode;
+                       bool vgt_primitiveid_en;
                        bool prim_restart_enable;
                        unsigned esgs_ring_size;
                        unsigned gsvs_ring_size;
@@ -1075,6 +1079,8 @@ struct radv_pipeline {
                        uint32_t ps_input_cntl_num;
                        uint32_t pa_cl_vs_out_cntl;
                        uint32_t vgt_shader_stages_en;
+                       uint32_t vtx_base_sgpr;
+                       uint8_t vtx_emit_num;
                        struct radv_prim_vertex_count prim_vertex_count;
                        bool can_use_guardband;
                } graphics;
@@ -1094,6 +1100,11 @@ static inline bool radv_pipeline_has_tess(struct radv_pipeline *pipeline)
        return pipeline->shaders[MESA_SHADER_TESS_EVAL] ? true : false;
 }
 
+uint32_t radv_shader_stage_to_user_data_0(gl_shader_stage stage, bool has_gs, bool has_tess);
+struct ac_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
+                                              gl_shader_stage stage,
+                                              int idx);
+
 struct radv_graphics_pipeline_create_info {
        bool use_rectlist;
        bool db_depth_clear;
@@ -1346,12 +1357,14 @@ struct radv_color_buffer_info {
        uint32_t cb_color_view;
        uint32_t cb_color_info;
        uint32_t cb_color_attrib;
+       uint32_t cb_color_attrib2;
        uint32_t cb_dcc_control;
        uint32_t cb_color_cmask_slice;
        uint32_t cb_color_fmask_slice;
        uint32_t cb_clear_value0;
        uint32_t cb_clear_value1;
        uint32_t micro_tile_mode;
+       uint32_t gfx9_epitch;
 };
 
 struct radv_ds_buffer_info {
@@ -1368,6 +1381,8 @@ struct radv_ds_buffer_info {
        uint32_t db_depth_slice;
        uint32_t db_htile_surface;
        uint32_t pa_su_poly_offset_db_fmt_cntl;
+       uint32_t db_z_info2;
+       uint32_t db_stencil_info2;
        float offset_scale;
 };