#include "util/macros.h"
#include "util/list.h"
#include "util/xmlconfig.h"
-#include "main/macros.h"
#include "vk_alloc.h"
#include "vk_debug_report.h"
#include "gfx10_format_table.h"
-enum radv_mem_heap {
- RADV_MEM_HEAP_VRAM,
- RADV_MEM_HEAP_VRAM_CPU_ACCESS,
- RADV_MEM_HEAP_GTT,
- RADV_MEM_HEAP_COUNT
-};
-
-enum radv_mem_type {
- RADV_MEM_TYPE_VRAM,
- RADV_MEM_TYPE_GTT_WRITE_COMBINE,
- RADV_MEM_TYPE_VRAM_CPU_ACCESS,
- RADV_MEM_TYPE_GTT_CACHED,
- RADV_MEM_TYPE_VRAM_UNCACHED,
- RADV_MEM_TYPE_GTT_WRITE_COMBINE_VRAM_UNCACHED,
- RADV_MEM_TYPE_VRAM_CPU_ACCESS_UNCACHED,
- RADV_MEM_TYPE_GTT_CACHED_VRAM_UNCACHED,
- RADV_MEM_TYPE_COUNT
-};
-
enum radv_secure_compile_type {
RADV_SC_TYPE_INIT_SUCCESS,
RADV_SC_TYPE_INIT_FAILURE,
struct radv_physical_device {
VK_LOADER_DATA _loader_data;
+ /* Link in radv_instance::physical_devices */
+ struct list_head link;
+
struct radv_instance * instance;
struct radeon_winsys *ws;
/* Whether to enable NGG. */
bool use_ngg;
+ /* Whether to enable NGG GS. */
+ bool use_ngg_gs;
+
/* Whether to enable NGG streamout. */
bool use_ngg_streamout;
struct disk_cache * disk_cache;
VkPhysicalDeviceMemoryProperties memory_properties;
- enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
+ enum radeon_bo_domain memory_domains[VK_MAX_MEMORY_TYPES];
+ enum radeon_bo_flag memory_flags[VK_MAX_MEMORY_TYPES];
drmPciBusInfo bus_info;
VkAllocationCallbacks alloc;
uint32_t apiVersion;
- int physicalDeviceCount;
- struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
char * engineName;
uint32_t engineVersion;
struct radv_physical_device_dispatch_table physical_device_dispatch;
struct radv_device_dispatch_table device_dispatch;
+ bool physical_devices_enumerated;
+ struct list_head physical_devices;
+
struct driOptionCache dri_options;
struct driOptionCache available_dri_options;
};
pthread_mutex_t mutex;
};
+VkResult radv_bo_list_add(struct radv_device *device,
+ struct radeon_winsys_bo *bo);
+void radv_bo_list_remove(struct radv_device *device,
+ struct radeon_winsys_bo *bo);
+
struct radv_secure_compile_process {
/* Secure process file descriptors. Used to communicate between the
* user facing device and the idle forked device used to fork a clean
void *thread_trace_ptr;
uint32_t thread_trace_buffer_size;
int thread_trace_start_frame;
+
+ /* Overallocation. */
+ bool overallocation_disallowed;
+ uint64_t allocated_memory_size[VK_MAX_MEMORY_HEAPS];
+ mtx_t overallocation_mutex;
};
struct radv_device_memory {
/* for dedicated allocations */
struct radv_image *image;
struct radv_buffer *buffer;
- uint32_t type_index;
- VkDeviceSize map_size;
+ uint32_t heap_index;
+ uint64_t alloc_size;
void * map;
void * user_ptr;
struct radv_descriptor_set {
const struct radv_descriptor_set_layout *layout;
uint32_t size;
+ uint32_t buffer_count;
struct radeon_winsys_bo *bo;
uint64_t va;
VkShaderStageFlags push_constant_stages;
struct radv_descriptor_set meta_push_descriptors;
- struct radv_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
+ struct radv_descriptor_state descriptors[MAX_BIND_POINTS];
struct radv_cmd_buffer_upload upload;
bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
-void si_emit_graphics(struct radv_physical_device *physical_device,
+void si_emit_graphics(struct radv_device *device,
struct radeon_cmdbuf *cs);
void si_emit_compute(struct radv_physical_device *physical_device,
struct radeon_cmdbuf *cs);
bool db_stencil_clear;
bool db_depth_disable_expclear;
bool db_stencil_disable_expclear;
- bool db_flush_depth_inplace;
- bool db_flush_stencil_inplace;
- bool db_resummarize;
+ bool depth_compress_disable;
+ bool stencil_compress_disable;
+ bool resummarize_enable;
uint32_t custom_blend_mode;
};
struct radv_image_plane planes[0];
};
-/* Whether the image has a htile that is known consistent with the contents of
- * the image. */
-bool radv_layout_has_htile(const struct radv_image *image,
- VkImageLayout layout,
- bool in_render_loop,
- unsigned queue_mask);
-
/* Whether the image has a htile that is known consistent with the contents of
* the image and is allowed to be in compressed form.
*
void radv_nir_shader_info_pass(const struct nir_shader *nir,
const struct radv_pipeline_layout *layout,
const struct radv_shader_variant_key *key,
- struct radv_shader_info *info);
+ struct radv_shader_info *info,
+ bool use_aco);
void radv_nir_shader_info_init(struct radv_shader_info *info);