radv: emit shader descriptor pointers consecutively

[mesa.git] / src / amd / vulkan / radv_private.h

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 1869604e9e230a4cdd649163f0bc55cfc09e180a..708cacf7708936faf0b5441cec682ac3f949b586 100644 (file)
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -57,8 +57,10 @@
 #include "ac_nir_to_llvm.h"
 #include "ac_gpu_info.h"
 #include "ac_surface.h"
+#include "ac_llvm_build.h"
 #include "radv_descriptor_set.h"
 #include "radv_extensions.h"
+#include "radv_cs.h"
 
 #include <llvm-c/TargetMachine.h>
 
@@ -295,6 +297,9 @@ struct radv_physical_device {
        bool has_out_of_order_rast;
        bool out_of_order_rast_allowed;
 
+       /* Whether DCC should be enabled for MSAA textures. */
+       bool dcc_msaa_allowed;
+
        /* This is the drivers on-disk cache used as a fallback as opposed to
         * the pipeline cache defined by apps.
         */
@@ -349,6 +354,7 @@ struct radv_pipeline_cache {
 struct radv_pipeline_key {
        uint32_t instance_rate_inputs;
        uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
+       uint64_t vertex_alpha_adjust;
        unsigned tess_input_vertices;
        uint32_t col_format;
        uint32_t is_int8;
@@ -357,6 +363,7 @@ struct radv_pipeline_key {
        uint8_t log2_num_samples;
        uint32_t multisample : 1;
        uint32_t has_multiview_view_index : 1;
+       uint32_t optimisations_disabled : 1;
 };
 
 void
@@ -462,18 +469,18 @@ struct radv_meta_state {
        } blit;
 
        struct {
-               VkRenderPass render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
+               VkPipelineLayout p_layouts[5];
+               VkDescriptorSetLayout ds_layouts[5];
+               VkPipeline pipelines[5][NUM_META_FS_KEYS];
 
-               VkPipelineLayout p_layouts[3];
-               VkDescriptorSetLayout ds_layouts[3];
-               VkPipeline pipelines[3][NUM_META_FS_KEYS];
+               VkPipeline depth_only_pipeline[5];
 
-               VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
-               VkPipeline depth_only_pipeline[3];
+               VkPipeline stencil_only_pipeline[5];
+       } blit2d[1 + MAX_SAMPLES_LOG2];
 
-               VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
-               VkPipeline stencil_only_pipeline[3];
-       } blit2d;
+       VkRenderPass blit2d_render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
+       VkRenderPass blit2d_depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
+       VkRenderPass blit2d_stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
 
        struct {
                VkPipelineLayout                          img_p_layout;
@@ -598,6 +605,12 @@ struct radv_queue {
        struct radeon_winsys_cs *continue_preamble_cs;
 };
 
+struct radv_bo_list {
+       struct radv_winsys_bo_list list;
+       unsigned capacity;
+       pthread_mutex_t mutex;
+};
+
 struct radv_device {
        VK_LOADER_DATA                              _loader_data;
 
@@ -613,7 +626,6 @@ struct radv_device {
        struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
 
        bool always_use_syncobj;
-       bool llvm_supports_spill;
        bool has_distributed_tess;
        bool pbb_allowed;
        bool dfsm_allowed;
@@ -660,6 +672,11 @@ struct radv_device {
        uint64_t dmesg_timestamp;
 
        struct radv_device_extension_table enabled_extensions;
+
+       /* Whether the driver uses a global BO list. */
+       bool use_global_bo_list;
+
+       struct radv_bo_list bo_list;
 };
 
 struct radv_device_memory {
@@ -1113,6 +1130,41 @@ bool radv_get_memory_fd(struct radv_device *device,
                        struct radv_device_memory *memory,
                        int *pFD);
 
+static inline void
+radv_emit_shader_pointer_head(struct radeon_winsys_cs *cs,
+                             unsigned sh_offset, unsigned pointer_count,
+                             bool use_32bit_pointers)
+{
+       radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count * (use_32bit_pointers ? 1 : 2), 0));
+       radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
+}
+
+static inline void
+radv_emit_shader_pointer_body(struct radv_device *device,
+                             struct radeon_winsys_cs *cs,
+                             uint64_t va, bool use_32bit_pointers)
+{
+       radeon_emit(cs, va);
+
+       if (use_32bit_pointers) {
+               assert(va == 0 ||
+                      (va >> 32) == device->physical_device->rad_info.address32_hi);
+       } else {
+               radeon_emit(cs, va >> 32);
+       }
+}
+
+static inline void
+radv_emit_shader_pointer(struct radv_device *device,
+                        struct radeon_winsys_cs *cs,
+                        uint32_t sh_offset, uint64_t va, bool global)
+{
+       bool use_32bit_pointers = HAVE_32BIT_POINTERS && !global;
+
+       radv_emit_shader_pointer_head(cs, sh_offset, 1, use_32bit_pointers);
+       radv_emit_shader_pointer_body(device, cs, va, use_32bit_pointers);
+}
+
 static inline struct radv_descriptor_state *
 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
                           VkPipelineBindPoint bind_point)