#define VG(x)
#endif
+#include "c11/threads.h"
#include <amdgpu.h>
#include "compiler/shader_enums.h"
#include "util/macros.h"
#include "ac_nir_to_llvm.h"
#include "ac_gpu_info.h"
#include "ac_surface.h"
+#include "ac_llvm_build.h"
#include "radv_descriptor_set.h"
#include "radv_extensions.h"
+#include "radv_cs.h"
#include <llvm-c/TargetMachine.h>
bool has_out_of_order_rast;
bool out_of_order_rast_allowed;
+ /* Whether DCC should be enabled for MSAA textures. */
+ bool dcc_msaa_allowed;
+
/* This is the drivers on-disk cache used as a fallback as opposed to
* the pipeline cache defined by apps.
*/
struct radv_pipeline_key {
uint32_t instance_rate_inputs;
+ uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
+ uint64_t vertex_alpha_adjust;
unsigned tess_input_vertices;
uint32_t col_format;
uint32_t is_int8;
uint8_t log2_num_samples;
uint32_t multisample : 1;
uint32_t has_multiview_view_index : 1;
+ uint32_t optimisations_disabled : 1;
};
void
} blit;
struct {
- VkRenderPass render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
+ VkPipelineLayout p_layouts[5];
+ VkDescriptorSetLayout ds_layouts[5];
+ VkPipeline pipelines[5][NUM_META_FS_KEYS];
- VkPipelineLayout p_layouts[3];
- VkDescriptorSetLayout ds_layouts[3];
- VkPipeline pipelines[3][NUM_META_FS_KEYS];
+ VkPipeline depth_only_pipeline[5];
- VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
- VkPipeline depth_only_pipeline[3];
+ VkPipeline stencil_only_pipeline[5];
+ } blit2d[1 + MAX_SAMPLES_LOG2];
- VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
- VkPipeline stencil_only_pipeline[3];
- } blit2d;
+ VkRenderPass blit2d_render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
+ VkRenderPass blit2d_depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
+ VkRenderPass blit2d_stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
struct {
VkPipelineLayout img_p_layout;
struct radeon_winsys_cs *continue_preamble_cs;
};
+struct radv_bo_list {
+ struct radv_winsys_bo_list list;
+ unsigned capacity;
+ pthread_mutex_t mutex;
+};
+
struct radv_device {
VK_LOADER_DATA _loader_data;
struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
bool always_use_syncobj;
- bool llvm_supports_spill;
bool has_distributed_tess;
bool pbb_allowed;
bool dfsm_allowed;
uint64_t dmesg_timestamp;
struct radv_device_extension_table enabled_extensions;
+
+ /* Whether the driver uses a global BO list. */
+ bool use_global_bo_list;
+
+ struct radv_bo_list bo_list;
};
struct radv_device_memory {
struct radv_device_memory *memory,
int *pFD);
+static inline void
+radv_emit_shader_pointer_head(struct radeon_winsys_cs *cs,
+ unsigned sh_offset, unsigned pointer_count,
+ bool use_32bit_pointers)
+{
+ radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count * (use_32bit_pointers ? 1 : 2), 0));
+ radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
+}
+
+static inline void
+radv_emit_shader_pointer_body(struct radv_device *device,
+ struct radeon_winsys_cs *cs,
+ uint64_t va, bool use_32bit_pointers)
+{
+ radeon_emit(cs, va);
+
+ if (use_32bit_pointers) {
+ assert(va == 0 ||
+ (va >> 32) == device->physical_device->rad_info.address32_hi);
+ } else {
+ radeon_emit(cs, va >> 32);
+ }
+}
+
+static inline void
+radv_emit_shader_pointer(struct radv_device *device,
+ struct radeon_winsys_cs *cs,
+ uint32_t sh_offset, uint64_t va, bool global)
+{
+ bool use_32bit_pointers = HAVE_32BIT_POINTERS && !global;
+
+ radv_emit_shader_pointer_head(cs, sh_offset, 1, use_32bit_pointers);
+ radv_emit_shader_pointer_body(device, cs, va, use_32bit_pointers);
+}
+
static inline struct radv_descriptor_state *
radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
VkPipelineBindPoint bind_point)
bool can_use_guardband;
uint32_t needed_dynamic_state;
bool disable_out_of_order_rast_for_occlusion;
+
+ /* Used for rbplus */
+ uint32_t col_format;
+ uint32_t cb_target_mask;
} graphics;
};
VkImageLayout layout,
unsigned queue_mask);
-static inline bool
-radv_vi_dcc_enabled(const struct radv_image *image, unsigned level)
-{
- return image->surface.dcc_size && level < image->surface.num_dcc_levels;
-}
-
-static inline bool
-radv_htile_enabled(const struct radv_image *image, unsigned level)
-{
- return image->surface.htile_size && level == 0;
-}
-
/**
* Return whether the image has CMASK metadata for color surfaces.
*/
return image->surface.dcc_size;
}
+/**
+ * Return whether DCC metadata is enabled for a level.
+ */
+static inline bool
+radv_dcc_enabled(const struct radv_image *image, unsigned level)
+{
+ return radv_image_has_dcc(image) &&
+ level < image->surface.num_dcc_levels;
+}
+
/**
* Return whether the image has HTILE metadata for depth surfaces.
*/
return image->surface.htile_size;
}
+/**
+ * Return whether HTILE metadata is enabled for a level.
+ */
+static inline bool
+radv_htile_enabled(const struct radv_image *image, unsigned level)
+{
+ return radv_image_has_htile(image) && level == 0;
+}
+
+/**
+ * Return whether the image is TC-compatible HTILE.
+ */
+static inline bool
+radv_image_is_tc_compat_htile(const struct radv_image *image)
+{
+ return radv_image_has_htile(image) && image->tc_compatible_htile;
+}
+
unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
static inline uint32_t
uint32_t descriptorWriteCount,
const VkWriteDescriptorSet *pDescriptorWrites);
-void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
- struct radv_image *image, uint32_t value);
void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *image, uint32_t value);