#include "ac_nir_to_llvm.h"
#include "ac_gpu_info.h"
#include "ac_surface.h"
+#include "ac_llvm_build.h"
#include "radv_descriptor_set.h"
#include "radv_extensions.h"
+#include "radv_cs.h"
#include <llvm-c/TargetMachine.h>
struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
bool always_use_syncobj;
- bool llvm_supports_spill;
bool has_distributed_tess;
bool pbb_allowed;
bool dfsm_allowed;
struct radv_device_memory *memory,
int *pFD);
+static inline void
+radv_emit_shader_pointer_head(struct radeon_winsys_cs *cs,
+ unsigned sh_offset, unsigned pointer_count,
+ bool use_32bit_pointers)
+{
+ radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count * (use_32bit_pointers ? 1 : 2), 0));
+ radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
+}
+
+static inline void
+radv_emit_shader_pointer_body(struct radv_device *device,
+ struct radeon_winsys_cs *cs,
+ uint64_t va, bool use_32bit_pointers)
+{
+ radeon_emit(cs, va);
+
+ if (use_32bit_pointers) {
+ assert(va == 0 ||
+ (va >> 32) == device->physical_device->rad_info.address32_hi);
+ } else {
+ radeon_emit(cs, va >> 32);
+ }
+}
+
+static inline void
+radv_emit_shader_pointer(struct radv_device *device,
+ struct radeon_winsys_cs *cs,
+ uint32_t sh_offset, uint64_t va, bool global)
+{
+ bool use_32bit_pointers = HAVE_32BIT_POINTERS && !global;
+
+ radv_emit_shader_pointer_head(cs, sh_offset, 1, use_32bit_pointers);
+ radv_emit_shader_pointer_body(device, cs, va, use_32bit_pointers);
+}
+
static inline struct radv_descriptor_state *
radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
VkPipelineBindPoint bind_point)