radv: set correct INDEX_TYPE for indexed indirect draws on GFX9

[mesa.git] / src / amd / vulkan / radv_private.h

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 93898a6ad1329b7b8f843b42cea7fb5ac844e273..70c5c70aaa5df77bd9191deb313c5d4ffb913bc8 100644 (file)
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -277,6 +277,12 @@ struct radv_physical_device {
 
        bool has_rbplus; /* if RB+ register exist */
        bool rbplus_allowed; /* if RB+ is allowed */
+       bool has_clear_state;
+
+       /* This is the drivers on-disk cache used as a fallback as opposed to
+        * the pipeline cache defined by apps.
+        */
+       struct disk_cache *                          disk_cache;
 };
 
 struct radv_instance {
@@ -396,7 +402,6 @@ struct radv_meta_state {
                VkPipeline pipeline;
        } itob;
        struct {
-               VkRenderPass render_pass;
                VkPipelineLayout                          img_p_layout;
                VkDescriptorSetLayout                     img_ds_layout;
                VkPipeline pipeline;
@@ -514,7 +519,6 @@ struct radv_device {
        struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
        int queue_count[RADV_MAX_QUEUE_FAMILIES];
        struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
-       uint64_t debug_flags;
 
        bool llvm_supports_spill;
        bool has_distributed_tess;
@@ -746,10 +750,6 @@ struct radv_dynamic_state {
 
 extern const struct radv_dynamic_state default_dynamic_state;
 
-void radv_dynamic_state_copy(struct radv_dynamic_state *dest,
-                            const struct radv_dynamic_state *src,
-                            uint32_t copy_mask);
-
 const char *
 radv_get_debug_option_name(int id);
 
@@ -962,13 +962,16 @@ struct radv_event {
 struct radv_shader_module;
 struct ac_shader_variant_key;
 
+#define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
+#define RADV_HASH_SHADER_SISCHED             (1 << 1)
+#define RADV_HASH_SHADER_UNSAFE_MATH         (1 << 2)
 void
 radv_hash_shader(unsigned char *hash, struct radv_shader_module *module,
                 const char *entrypoint,
                 const VkSpecializationInfo *spec_info,
                 const struct radv_pipeline_layout *layout,
                 const struct ac_shader_variant_key *key,
-                uint32_t is_geom_copy_shader);
+                uint32_t flags);
 
 static inline gl_shader_stage
 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
@@ -1014,9 +1017,6 @@ unsigned radv_format_meta_fs_key(VkFormat format);
 struct radv_raster_state {
        uint32_t pa_cl_clip_cntl;
        uint32_t spi_interp_control;
-       uint32_t pa_su_point_size;
-       uint32_t pa_su_point_minmax;
-       uint32_t pa_su_line_cntl;
        uint32_t pa_su_vtx_cntl;
        uint32_t pa_su_sc_mode_cntl;
 };
@@ -1103,6 +1103,7 @@ struct radv_pipeline {
                        bool ia_switch_on_eoi;
                        bool partial_vs_wave;
                        uint8_t vtx_emit_num;
+                       uint32_t vtx_reuse_depth;
                        struct radv_prim_vertex_count prim_vertex_count;
                        bool can_use_guardband;
                } graphics;
@@ -1223,6 +1224,7 @@ struct radv_image {
        VkDeviceSize offset;
        uint32_t dcc_offset;
        uint32_t htile_offset;
+       bool tc_compatible_htile;
        struct radeon_surf surface;
 
        struct radv_fmask_info fmask;
@@ -1251,6 +1253,17 @@ bool radv_layout_can_fast_clear(const struct radv_image *image,
                                VkImageLayout layout,
                                unsigned queue_mask);
 
+static inline bool
+radv_vi_dcc_enabled(const struct radv_image *image, unsigned level)
+{
+       return image->surface.dcc_size && level < image->surface.num_dcc_levels;
+}
+
+static inline bool
+radv_htile_enabled(const struct radv_image *image, unsigned level)
+{
+       return image->surface.htile_size && level == 0;
+}
 
 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);