#include "ac_nir_to_llvm.h"
#include "ac_gpu_info.h"
#include "ac_surface.h"
-#include "radv_debug.h"
#include "radv_descriptor_set.h"
#include <llvm-c/TargetMachine.h>
#define MAX_PUSH_DESCRIPTORS 32
#define MAX_DYNAMIC_BUFFERS 16
#define MAX_SAMPLES_LOG2 4
-#define NUM_META_FS_KEYS 11
+#define NUM_META_FS_KEYS 13
#define RADV_MAX_DRM_DEVICES 8
+#define MAX_VIEWS 8
#define NUM_DEPTH_CLEAR_PIPELINES 3
struct radeon_info rad_info;
char path[20];
const char * name;
- uint8_t uuid[VK_UUID_SIZE];
+ uint8_t driver_uuid[VK_UUID_SIZE];
uint8_t device_uuid[VK_UUID_SIZE];
+ uint8_t cache_uuid[VK_UUID_SIZE];
int local_fd;
struct wsi_device wsi_device;
struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
uint64_t debug_flags;
+ uint64_t perftest_flags;
};
VkResult radv_init_wsi(struct radv_physical_device *physical_device);
VkPipelineLayout p_layout;
struct {
- VkRenderPass srgb_render_pass;
- VkPipeline srgb_pipeline;
VkRenderPass render_pass[NUM_META_FS_KEYS];
VkPipeline pipeline[NUM_META_FS_KEYS];
} rc[MAX_SAMPLES_LOG2];
VkPipeline decompress_pipeline;
VkPipeline resummarize_pipeline;
VkRenderPass pass;
- } depth_decomp;
+ } depth_decomp[1 + MAX_SAMPLES_LOG2];
struct {
VkPipeline cmask_eliminate_pipeline;
/* Backup in-memory cache to be used if the app doesn't provide one */
struct radv_pipeline_cache * mem_cache;
+
+ /*
+ * use different counters so MSAA MRTs get consecutive surface indices,
+ * even if MASK is allocated in between.
+ */
+ uint32_t image_mrt_offset_counter;
+ uint32_t fmask_mrt_offset_counter;
+ struct list_head shader_slabs;
+ mtx_t shader_slab_mutex;
};
struct radv_device_memory {
*/
struct radv_attachment_state {
VkImageAspectFlags pending_clear_aspects;
+ uint32_t cleared_views;
VkClearValue clear_value;
VkImageLayout current_layout;
};
struct radv_descriptor_set * descriptors[MAX_SETS];
struct radv_attachment_state * attachments;
VkRect2D render_area;
- struct radv_buffer * index_buffer;
uint32_t index_type;
- uint32_t index_offset;
+ uint64_t index_va;
+ uint32_t max_index_count;
int32_t last_primitive_reset_en;
uint32_t last_primitive_reset_index;
enum radv_cmd_flush_bits flush_bits;
uint32_t descriptors_dirty;
uint32_t trace_id;
uint32_t last_ia_multi_vgt_param;
+ bool predicating;
};
struct radv_cmd_pool {
bool tess_rings_needed;
bool sample_positions_needed;
- bool record_fail;
+ VkResult record_result;
int ring_offsets_idx; /* just used for verification */
uint32_t gfx9_fence_offset;
bool instanced_draw, bool indirect_draw,
uint32_t draw_vertex_count);
void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
+ bool predicated,
enum chip_class chip_class,
bool is_mec,
unsigned event, unsigned event_flags,
uint32_t new_fence);
void si_emit_wait_fence(struct radeon_winsys_cs *cs,
+ bool predicated,
uint64_t va, uint32_t ref,
uint32_t mask);
void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
+ bool predicated,
enum chip_class chip_class,
uint32_t *fence_ptr, uint64_t va,
bool is_mec,
enum radv_cmd_flush_bits flush_bits);
void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
+void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va);
void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
uint64_t src_va, uint64_t dest_va,
uint64_t size);
struct radv_image *image,
int idx,
uint32_t color_values[2]);
+void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
+ struct radv_image *image,
+ bool value);
void radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
struct radeon_winsys_bo *bo,
uint64_t offset, uint64_t size, uint32_t value);
char data[0];
};
-union ac_shader_variant_key;
+struct ac_shader_variant_key;
void
radv_hash_shader(unsigned char *hash, struct radv_shader_module *module,
const char *entrypoint,
const VkSpecializationInfo *spec_info,
const struct radv_pipeline_layout *layout,
- const union ac_shader_variant_key *key,
+ const struct ac_shader_variant_key *key,
uint32_t is_geom_copy_shader);
static inline gl_shader_stage
stage = __builtin_ffs(__tmp) - 1, __tmp; \
__tmp &= ~(1 << (stage)))
+
+struct radv_shader_slab {
+ struct list_head slabs;
+ struct list_head shaders;
+ struct radeon_winsys_bo *bo;
+ uint64_t size;
+ char *ptr;
+};
+
struct radv_shader_variant {
uint32_t ref_count;
struct radeon_winsys_bo *bo;
+ uint64_t bo_offset;
struct ac_shader_config config;
struct ac_shader_variant_info info;
unsigned rsrc1;
unsigned rsrc2;
uint32_t code_size;
+
+ struct list_head slab_list;
};
+
+void *radv_alloc_shader_memory(struct radv_device *device,
+ struct radv_shader_variant *shader);
+
+void radv_destroy_shader_slabs(struct radv_device *device);
+
struct radv_depth_stencil_state {
uint32_t db_depth_control;
uint32_t db_stencil_control;
struct radv_blend_state {
uint32_t cb_color_control;
uint32_t cb_target_mask;
- uint32_t sx_mrt0_blend_opt[8];
+ uint32_t sx_mrt_blend_opt[8];
uint32_t cb_blend_control[8];
uint32_t spi_shader_col_format;
unsigned prim;
unsigned gs_out;
uint32_t vgt_gs_mode;
+ bool vgt_primitiveid_en;
bool prim_restart_enable;
unsigned esgs_ring_size;
unsigned gsvs_ring_size;
unsigned bank_height;
unsigned slice_tile_max;
unsigned tile_mode_index;
+ unsigned tile_swizzle;
};
struct radv_cmask_info {
bool exclusive;
unsigned queue_family_mask;
+ bool shareable;
+
/* Set when bound */
struct radeon_winsys_bo *bo;
VkDeviceSize offset;
struct radv_fmask_info fmask;
struct radv_cmask_info cmask;
uint32_t clear_value_offset;
+ uint32_t dcc_pred_offset;
};
/* Whether the image has a htile that is known consistent with the contents of
uint32_t base_layer;
uint32_t layer_count;
uint32_t base_mip;
+ uint32_t level_count;
VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
uint32_t descriptor[8];
uint32_t fmask_descriptor[8];
+
+ /* Descriptor for use as a storage image as opposed to a sampled image.
+ * This has a few differences for cube maps (e.g. type).
+ */
+ uint32_t storage_descriptor[8];
+ uint32_t storage_fmask_descriptor[8];
};
struct radv_image_create_info {
void radv_image_view_init(struct radv_image_view *view,
struct radv_device *device,
- const VkImageViewCreateInfo* pCreateInfo,
- struct radv_cmd_buffer *cmd_buffer,
- VkImageUsageFlags usage_mask);
+ const VkImageViewCreateInfo* pCreateInfo);
struct radv_buffer_view {
struct radeon_winsys_bo *bo;
bool has_resolve;
struct radv_subpass_barrier start_barrier;
+
+ uint32_t view_mask;
};
struct radv_render_pass_attachment {
VkAttachmentLoadOp stencil_load_op;
VkImageLayout initial_layout;
VkImageLayout final_layout;
+ uint32_t view_mask;
};
struct radv_render_pass {
uint32_t pipeline_stats_mask;
};
+struct radv_semaphore {
+ /* use a winsys sem for non-exportable */
+ struct radeon_winsys_sem *sem;
+ uint32_t syncobj;
+ uint32_t temp_syncobj;
+};
+
+VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
+ int num_wait_sems,
+ const VkSemaphore *wait_sems,
+ int num_signal_sems,
+ const VkSemaphore *signal_sems);
+void radv_free_sem_info(struct radv_winsys_sem_info *sem_info);
+
void
radv_update_descriptor_sets(struct radv_device *device,
struct radv_cmd_buffer *cmd_buffer,
RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
-RADV_DEFINE_NONDISP_HANDLE_CASTS(radeon_winsys_sem, VkSemaphore)
+RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
#endif /* RADV_PRIVATE_H */
projects / mesa.git / blobdiff