#include "compiler/shader_enums.h"
#include "util/macros.h"
#include "util/list.h"
-#include "util/vk_alloc.h"
#include "main/macros.h"
+#include "vk_alloc.h"
#include "radv_radeon_winsys.h"
#include "ac_binary.h"
#include "ac_nir_to_llvm.h"
-#include "radv_debug.h"
+#include "ac_gpu_info.h"
+#include "ac_surface.h"
#include "radv_descriptor_set.h"
#include <llvm-c/TargetMachine.h>
#define MAX_VIEWPORTS 16
#define MAX_SCISSORS 16
#define MAX_PUSH_CONSTANTS_SIZE 128
+#define MAX_PUSH_DESCRIPTORS 32
#define MAX_DYNAMIC_BUFFERS 16
#define MAX_SAMPLES_LOG2 4
-#define NUM_META_FS_KEYS 11
+#define NUM_META_FS_KEYS 13
#define RADV_MAX_DRM_DEVICES 8
+#define MAX_VIEWS 8
#define NUM_DEPTH_CLEAR_PIPELINES 3
struct radeon_info rad_info;
char path[20];
const char * name;
- uint8_t uuid[VK_UUID_SIZE];
+ uint8_t driver_uuid[VK_UUID_SIZE];
+ uint8_t device_uuid[VK_UUID_SIZE];
+ uint8_t cache_uuid[VK_UUID_SIZE];
int local_fd;
struct wsi_device wsi_device;
struct radv_extensions extensions;
+
+ bool has_rbplus; /* if RB+ register exist */
+ bool rbplus_allowed; /* if RB+ is allowed */
};
struct radv_instance {
struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
uint64_t debug_flags;
+ uint64_t perftest_flags;
};
VkResult radv_init_wsi(struct radv_physical_device *physical_device);
struct radv_pipeline *depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
} clear[1 + MAX_SAMPLES_LOG2];
+ VkPipelineLayout clear_color_p_layout;
+ VkPipelineLayout clear_depth_p_layout;
struct {
VkRenderPass render_pass[NUM_META_FS_KEYS];
struct {
VkPipeline pipeline;
VkPipeline i_pipeline;
+ VkPipeline srgb_pipeline;
} rc[MAX_SAMPLES_LOG2];
} resolve_compute;
+ struct {
+ VkDescriptorSetLayout ds_layout;
+ VkPipelineLayout p_layout;
+
+ struct {
+ VkRenderPass render_pass[NUM_META_FS_KEYS];
+ VkPipeline pipeline[NUM_META_FS_KEYS];
+ } rc[MAX_SAMPLES_LOG2];
+ } resolve_fragment;
+
struct {
VkPipeline decompress_pipeline;
VkPipeline resummarize_pipeline;
VkRenderPass pass;
- } depth_decomp;
+ } depth_decomp[1 + MAX_SAMPLES_LOG2];
struct {
VkPipeline cmask_eliminate_pipeline;
VkPipeline fill_pipeline;
VkPipeline copy_pipeline;
} buffer;
+
+ struct {
+ VkDescriptorSetLayout ds_layout;
+ VkPipelineLayout p_layout;
+ VkPipeline occlusion_query_pipeline;
+ VkPipeline pipeline_statistics_query_pipeline;
+ } query;
};
/* queue types */
uint32_t compute_scratch_size;
uint32_t esgs_ring_size;
uint32_t gsvs_ring_size;
+ bool has_tess_rings;
+ bool has_sample_positions;
struct radeon_winsys_bo *scratch_bo;
struct radeon_winsys_bo *descriptor_bo;
struct radeon_winsys_bo *compute_scratch_bo;
struct radeon_winsys_bo *esgs_ring_bo;
struct radeon_winsys_bo *gsvs_ring_bo;
+ struct radeon_winsys_bo *tess_factor_ring_bo;
+ struct radeon_winsys_bo *tess_offchip_ring_bo;
struct radeon_winsys_cs *initial_preamble_cs;
struct radeon_winsys_cs *continue_preamble_cs;
};
int queue_count[RADV_MAX_QUEUE_FAMILIES];
struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
struct radeon_winsys_cs *flush_cs[RADV_MAX_QUEUE_FAMILIES];
-
+ struct radeon_winsys_cs *flush_shader_cs[RADV_MAX_QUEUE_FAMILIES];
uint64_t debug_flags;
bool llvm_supports_spill;
+ bool has_distributed_tess;
+ uint32_t tess_offchip_block_dw_size;
uint32_t scratch_waves;
uint32_t gs_table_depth;
uint32_t *trace_id_ptr;
struct radv_physical_device *physical_device;
+
+ /* Backup in-memory cache to be used if the app doesn't provide one */
+ struct radv_pipeline_cache * mem_cache;
+
+ /*
+ * use different counters so MSAA MRTs get consecutive surface indices,
+ * even if MASK is allocated in between.
+ */
+ uint32_t image_mrt_offset_counter;
+ uint32_t fmask_mrt_offset_counter;
+ struct list_head shader_slabs;
+ mtx_t shader_slab_mutex;
};
struct radv_device_memory {
const struct radv_descriptor_set_layout *layout;
uint32_t size;
- struct radv_buffer_view *buffer_views;
struct radeon_winsys_bo *bo;
uint64_t va;
uint32_t *mapped_ptr;
struct radeon_winsys_bo *descriptors[0];
};
+struct radv_push_descriptor_set
+{
+ struct radv_descriptor_set set;
+ uint32_t capacity;
+};
+
struct radv_descriptor_pool {
struct radeon_winsys_bo *bo;
uint8_t *mapped_ptr;
uint64_t size;
struct list_head vram_list;
+
+ uint8_t *host_memory_base;
+ uint8_t *host_memory_ptr;
+ uint8_t *host_memory_end;
+};
+
+struct radv_descriptor_update_template_entry {
+ VkDescriptorType descriptor_type;
+
+ /* The number of descriptors to update */
+ uint32_t descriptor_count;
+
+ /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
+ uint32_t dst_offset;
+
+ /* In dwords. Not valid/used for dynamic descriptors */
+ uint32_t dst_stride;
+
+ uint32_t buffer_offset;
+
+ /* Only valid for combined image samplers and samplers */
+ uint16_t has_sampler;
+
+ /* In bytes */
+ size_t src_offset;
+ size_t src_stride;
+
+ /* For push descriptors */
+ const uint32_t *immutable_samplers;
+};
+
+struct radv_descriptor_update_template {
+ uint32_t entry_count;
+ struct radv_descriptor_update_template_entry entry[0];
};
struct radv_buffer {
VkDeviceSize size;
VkBufferUsageFlags usage;
+ VkBufferCreateFlags flags;
/* Set when bound */
struct radeon_winsys_bo * bo;
*/
struct radv_attachment_state {
VkImageAspectFlags pending_clear_aspects;
+ uint32_t cleared_views;
VkClearValue clear_value;
VkImageLayout current_layout;
};
struct radv_cmd_state {
uint32_t vb_dirty;
radv_cmd_dirty_mask_t dirty;
- bool vertex_descriptors_dirty;
+ bool push_descriptors_dirty;
struct radv_pipeline * pipeline;
struct radv_pipeline * emitted_pipeline;
struct radv_descriptor_set * descriptors[MAX_SETS];
struct radv_attachment_state * attachments;
VkRect2D render_area;
- struct radv_buffer * index_buffer;
uint32_t index_type;
- uint32_t index_offset;
+ uint64_t index_va;
+ uint32_t max_index_count;
+ int32_t last_primitive_reset_en;
uint32_t last_primitive_reset_index;
enum radv_cmd_flush_bits flush_bits;
unsigned active_occlusion_queries;
uint32_t descriptors_dirty;
uint32_t trace_id;
uint32_t last_ia_multi_vgt_param;
+ bool predicating;
};
struct radv_cmd_pool {
uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
VkShaderStageFlags push_constant_stages;
+ struct radv_push_descriptor_set push_descriptors;
+ struct radv_descriptor_set meta_push_descriptors;
struct radv_cmd_buffer_upload upload;
- bool record_fail;
-
uint32_t scratch_size_needed;
uint32_t compute_scratch_size_needed;
uint32_t esgs_ring_size_needed;
uint32_t gsvs_ring_size_needed;
+ bool tess_rings_needed;
+ bool sample_positions_needed;
+
+ VkResult record_result;
int ring_offsets_idx; /* just used for verification */
+ uint32_t gfx9_fence_offset;
+ struct radeon_winsys_bo *gfx9_fence_bo;
+ uint32_t gfx9_fence_idx;
};
struct radv_image;
void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
int count, const VkViewport *viewports);
void si_write_scissors(struct radeon_winsys_cs *cs, int first,
- int count, const VkRect2D *scissors);
+ int count, const VkRect2D *scissors,
+ const VkViewport *viewports, bool can_use_guardband);
uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
- bool instanced_or_indirect_draw, uint32_t draw_vertex_count);
-void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
- enum chip_class chip_class,
- bool is_mec,
- enum radv_cmd_flush_bits flush_bits);
+ bool instanced_draw, bool indirect_draw,
+ uint32_t draw_vertex_count);
+void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
+ bool predicated,
+ enum chip_class chip_class,
+ bool is_mec,
+ unsigned event, unsigned event_flags,
+ unsigned data_sel,
+ uint64_t va,
+ uint32_t old_fence,
+ uint32_t new_fence);
+
+void si_emit_wait_fence(struct radeon_winsys_cs *cs,
+ bool predicated,
+ uint64_t va, uint32_t ref,
+ uint32_t mask);
void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
- enum chip_class chip_class,
- bool is_mec,
- enum radv_cmd_flush_bits flush_bits);
+ bool predicated,
+ enum chip_class chip_class,
+ uint32_t *fence_ptr, uint64_t va,
+ bool is_mec,
+ enum radv_cmd_flush_bits flush_bits);
void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
+void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va);
void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
uint64_t src_va, uint64_t dest_va,
uint64_t size);
+void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
+ unsigned size);
void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
uint64_t size, unsigned value);
void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer);
void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
+void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
+void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
unsigned radv_cayman_get_maxdist(int log_samples);
void radv_device_init_msaa(struct radv_device *device);
struct radv_image *image,
int idx,
uint32_t color_values[2]);
+void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
+ struct radv_image *image,
+ bool value);
void radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
struct radeon_winsys_bo *bo,
uint64_t offset, uint64_t size, uint32_t value);
char data[0];
};
-union ac_shader_variant_key;
+struct ac_shader_variant_key;
void
radv_hash_shader(unsigned char *hash, struct radv_shader_module *module,
const char *entrypoint,
const VkSpecializationInfo *spec_info,
const struct radv_pipeline_layout *layout,
- const union ac_shader_variant_key *key,
+ const struct ac_shader_variant_key *key,
uint32_t is_geom_copy_shader);
static inline gl_shader_stage
stage = __builtin_ffs(__tmp) - 1, __tmp; \
__tmp &= ~(1 << (stage)))
+
+struct radv_shader_slab {
+ struct list_head slabs;
+ struct list_head shaders;
+ struct radeon_winsys_bo *bo;
+ uint64_t size;
+ char *ptr;
+};
+
struct radv_shader_variant {
uint32_t ref_count;
struct radeon_winsys_bo *bo;
+ uint64_t bo_offset;
struct ac_shader_config config;
struct ac_shader_variant_info info;
unsigned rsrc1;
unsigned rsrc2;
uint32_t code_size;
+
+ struct list_head slab_list;
};
+
+void *radv_alloc_shader_memory(struct radv_device *device,
+ struct radv_shader_variant *shader);
+
+void radv_destroy_shader_slabs(struct radv_device *device);
+
struct radv_depth_stencil_state {
uint32_t db_depth_control;
uint32_t db_stencil_control;
struct radv_blend_state {
uint32_t cb_color_control;
uint32_t cb_target_mask;
- uint32_t sx_mrt0_blend_opt[8];
+ uint32_t sx_mrt_blend_opt[8];
uint32_t cb_blend_control[8];
uint32_t spi_shader_col_format;
struct radv_raster_state {
uint32_t pa_cl_clip_cntl;
- uint32_t pa_cl_vs_out_cntl;
uint32_t spi_interp_control;
uint32_t pa_su_point_size;
uint32_t pa_su_point_minmax;
uint8_t incr;
};
+struct radv_tessellation_state {
+ uint32_t ls_hs_config;
+ uint32_t tcs_in_layout;
+ uint32_t tcs_out_layout;
+ uint32_t tcs_out_offsets;
+ uint32_t offchip_layout;
+ unsigned num_patches;
+ unsigned lds_size;
+ unsigned num_tcs_input_cp;
+ uint32_t tf_param;
+};
+
struct radv_pipeline {
struct radv_device * device;
uint32_t dynamic_state_mask;
struct radv_pipeline_layout * layout;
bool needs_data_cache;
-
+ bool need_indirect_descriptor_sets;
struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
struct radv_shader_variant *gs_copy_shader;
VkShaderStageFlags active_stages;
struct radv_depth_stencil_state ds;
struct radv_raster_state raster;
struct radv_multisample_state ms;
+ struct radv_tessellation_state tess;
+ uint32_t db_shader_control;
+ uint32_t shader_z_format;
unsigned prim;
unsigned gs_out;
+ uint32_t vgt_gs_mode;
+ bool vgt_primitiveid_en;
bool prim_restart_enable;
unsigned esgs_ring_size;
unsigned gsvs_ring_size;
+ uint32_t ps_input_cntl[32];
+ uint32_t ps_input_cntl_num;
+ uint32_t pa_cl_vs_out_cntl;
+ uint32_t vgt_shader_stages_en;
+ uint32_t vtx_base_sgpr;
+ uint8_t vtx_emit_num;
struct radv_prim_vertex_count prim_vertex_count;
+ bool can_use_guardband;
} graphics;
};
return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
}
+static inline bool radv_pipeline_has_tess(struct radv_pipeline *pipeline)
+{
+ return pipeline->shaders[MESA_SHADER_TESS_EVAL] ? true : false;
+}
+
+uint32_t radv_shader_stage_to_user_data_0(gl_shader_stage stage, bool has_gs, bool has_tess);
+struct ac_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
+ gl_shader_stage stage,
+ int idx);
+
struct radv_graphics_pipeline_create_info {
bool use_rectlist;
bool db_depth_clear;
unsigned bank_height;
unsigned slice_tile_max;
unsigned tile_mode_index;
+ unsigned tile_swizzle;
};
struct radv_cmask_info {
*/
VkFormat vk_format;
VkImageAspectFlags aspects;
- VkExtent3D extent;
- uint32_t levels;
- uint32_t array_size;
- uint32_t samples; /**< VkImageCreateInfo::samples */
+ struct ac_surf_info info;
VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
VkImageTiling tiling; /** VkImageCreateInfo::tiling */
+ VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
VkDeviceSize size;
uint32_t alignment;
bool exclusive;
unsigned queue_family_mask;
+ bool shareable;
+
/* Set when bound */
struct radeon_winsys_bo *bo;
VkDeviceSize offset;
struct radv_fmask_info fmask;
struct radv_cmask_info cmask;
uint32_t clear_value_offset;
+ uint32_t dcc_pred_offset;
};
+/* Whether the image has a htile that is known consistent with the contents of
+ * the image. */
bool radv_layout_has_htile(const struct radv_image *image,
- VkImageLayout layout);
+ VkImageLayout layout,
+ unsigned queue_mask);
+
+/* Whether the image has a htile that is known consistent with the contents of
+ * the image and is allowed to be in compressed form.
+ *
+ * If this is false reads that don't use the htile should be able to return
+ * correct results.
+ */
bool radv_layout_is_htile_compressed(const struct radv_image *image,
- VkImageLayout layout);
-bool radv_layout_can_expclear(const struct radv_image *image,
- VkImageLayout layout);
+ VkImageLayout layout,
+ unsigned queue_mask);
+
bool radv_layout_can_fast_clear(const struct radv_image *image,
VkImageLayout layout,
unsigned queue_mask);
const VkImageSubresourceRange *range)
{
return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
- image->array_size - range->baseArrayLayer : range->layerCount;
+ image->info.array_size - range->baseArrayLayer : range->layerCount;
}
static inline uint32_t
const VkImageSubresourceRange *range)
{
return range->levelCount == VK_REMAINING_MIP_LEVELS ?
- image->levels - range->baseMipLevel : range->levelCount;
+ image->info.levels - range->baseMipLevel : range->levelCount;
}
struct radeon_bo_metadata;
uint32_t base_layer;
uint32_t layer_count;
uint32_t base_mip;
+ uint32_t level_count;
VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
uint32_t descriptor[8];
uint32_t fmask_descriptor[8];
+
+ /* Descriptor for use as a storage image as opposed to a sampled image.
+ * This has a few differences for cube maps (e.g. type).
+ */
+ uint32_t storage_descriptor[8];
+ uint32_t storage_fmask_descriptor[8];
};
struct radv_image_create_info {
const VkImageCreateInfo *vk_info;
- uint32_t stride;
bool scanout;
};
void radv_image_view_init(struct radv_image_view *view,
struct radv_device *device,
- const VkImageViewCreateInfo* pCreateInfo,
- struct radv_cmd_buffer *cmd_buffer,
- VkImageUsageFlags usage_mask);
-void radv_image_set_optimal_micro_tile_mode(struct radv_device *device,
- struct radv_image *image, uint32_t micro_tile_mode);
+ const VkImageViewCreateInfo* pCreateInfo);
+
struct radv_buffer_view {
struct radeon_winsys_bo *bo;
VkFormat vk_format;
}
}
+static inline bool
+radv_image_extent_compare(const struct radv_image *image,
+ const VkExtent3D *extent)
+{
+ if (extent->width != image->info.width ||
+ extent->height != image->info.height ||
+ extent->depth != image->info.depth)
+ return false;
+ return true;
+}
+
struct radv_sampler {
uint32_t state[4];
};
struct radv_color_buffer_info {
- uint32_t cb_color_base;
+ uint64_t cb_color_base;
+ uint64_t cb_color_cmask;
+ uint64_t cb_color_fmask;
+ uint64_t cb_dcc_base;
uint32_t cb_color_pitch;
uint32_t cb_color_slice;
uint32_t cb_color_view;
uint32_t cb_color_info;
uint32_t cb_color_attrib;
+ uint32_t cb_color_attrib2;
uint32_t cb_dcc_control;
- uint32_t cb_color_cmask;
uint32_t cb_color_cmask_slice;
- uint32_t cb_color_fmask;
uint32_t cb_color_fmask_slice;
uint32_t cb_clear_value0;
uint32_t cb_clear_value1;
- uint32_t cb_dcc_base;
uint32_t micro_tile_mode;
+ uint32_t gfx9_epitch;
};
struct radv_ds_buffer_info {
+ uint64_t db_z_read_base;
+ uint64_t db_stencil_read_base;
+ uint64_t db_z_write_base;
+ uint64_t db_stencil_write_base;
+ uint64_t db_htile_data_base;
uint32_t db_depth_info;
uint32_t db_z_info;
uint32_t db_stencil_info;
- uint32_t db_z_read_base;
- uint32_t db_stencil_read_base;
- uint32_t db_z_write_base;
- uint32_t db_stencil_write_base;
uint32_t db_depth_view;
uint32_t db_depth_size;
uint32_t db_depth_slice;
uint32_t db_htile_surface;
- uint32_t db_htile_data_base;
uint32_t pa_su_poly_offset_db_fmt_cntl;
+ uint32_t db_z_info2;
+ uint32_t db_stencil_info2;
float offset_scale;
};
struct radv_subpass {
uint32_t input_count;
- VkAttachmentReference * input_attachments;
uint32_t color_count;
+ VkAttachmentReference * input_attachments;
VkAttachmentReference * color_attachments;
VkAttachmentReference * resolve_attachments;
VkAttachmentReference depth_stencil_attachment;
bool has_resolve;
struct radv_subpass_barrier start_barrier;
+
+ uint32_t view_mask;
};
struct radv_render_pass_attachment {
VkAttachmentLoadOp stencil_load_op;
VkImageLayout initial_layout;
VkImageLayout final_layout;
+ uint32_t view_mask;
};
struct radv_render_pass {
uint32_t availability_offset;
char *ptr;
VkQueryType type;
+ uint32_t pipeline_stats_mask;
};
-VkResult
-radv_temp_descriptor_set_create(struct radv_device *device,
- struct radv_cmd_buffer *cmd_buffer,
- VkDescriptorSetLayout _layout,
- VkDescriptorSet *_set);
+struct radv_semaphore {
+ /* use a winsys sem for non-exportable */
+ struct radeon_winsys_sem *sem;
+ uint32_t syncobj;
+ uint32_t temp_syncobj;
+};
+
+VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
+ int num_wait_sems,
+ const VkSemaphore *wait_sems,
+ int num_signal_sems,
+ const VkSemaphore *signal_sems);
+void radv_free_sem_info(struct radv_winsys_sem_info *sem_info);
+
+void
+radv_update_descriptor_sets(struct radv_device *device,
+ struct radv_cmd_buffer *cmd_buffer,
+ VkDescriptorSet overrideSet,
+ uint32_t descriptorWriteCount,
+ const VkWriteDescriptorSet *pDescriptorWrites,
+ uint32_t descriptorCopyCount,
+ const VkCopyDescriptorSet *pDescriptorCopies);
void
-radv_temp_descriptor_set_destroy(struct radv_device *device,
- VkDescriptorSet _set);
+radv_update_descriptor_set_with_template(struct radv_device *device,
+ struct radv_cmd_buffer *cmd_buffer,
+ struct radv_descriptor_set *set,
+ VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
+ const void *pData);
+
+void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
+ VkPipelineBindPoint pipelineBindPoint,
+ VkPipelineLayout _layout,
+ uint32_t set,
+ uint32_t descriptorWriteCount,
+ const VkWriteDescriptorSet *pDescriptorWrites);
+
void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *image, uint32_t value);
void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
+RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
-RADV_DEFINE_NONDISP_HANDLE_CASTS(radeon_winsys_sem, VkSemaphore)
+RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
#endif /* RADV_PRIVATE_H */
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